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原始內容

ANCHOR REPORT

Global Markets Research 24 July 2026

Advanced Semi Testing

Chip upgrade; testing ahead

Our team has been positive on the semiconductor testing sector since 4Q25, based on our view that: 1) the value of back-end processes as a portion of chip manufacturing costs is increasing in the AI chip era, 2) the streamlining of leading players and spillover effect should benefit overall supply chain players. In this report, we extend our coverage from OSATs to test interface and equipment makers in Taiwan, as they are key enablers in the chip testing process, work as gatekeepers and ensure fewer failures in later stages. We also notice that key vendors command vital strategic value in an industry-wide supply-constrained environment. We maintain our perspective outlined in our most recent sector view (end-June) that we haven't reached AI cycle peak, initiate coverage of MPI, WinWay, Hon Precision, and resume coverage of Chroma, all with Buy ratings.

Key themes and analysis of this report:

• Our understanding of CPO testing flow and potential suppliers ·
• Analysis of testing content in GPU by generation ·
• A natural rise in testing process sophistication along with advanced packaging ·
• Upgrade trend of test hardware to cope with stringent requirements ·
• Observation on test hardware market and related peers ·
• Comparison of major Taiwanese test hardware players ·

Research Analysts

Semiconductor

Vivian Yang - NITB

vivian.yang@nomura.com +886(2) 21769970

Eric Chen, CFA - NITB eric.chen@nomura.com +886(2) 21769965

Aaron Jeng, CFA - NITB

aaron.jeng@nomura.com +886(2) 21769962

Production Complete: 2026-07-23 20:41 UTC

EQUITY: TECHNOLOGY

Advanced Semi Testing

EQUITY: TECHNOLOGY

Chip upgrade; testing ahead

Buy on testing process sophistication, spec upgrade, share gain/order overflow, and supply constraints

In a nutshell, testing is now in the driver's seat

Our team has been positive on the semiconductor OSAT sector since 4Q25 (when we upgraded ASE [3711 TT, Buy] ), on our view that: 1) the value of back-end processing as a portion of chip manufacturing costs continues to rise along with advanced packaging; 2) the streamlining of leading players and spillover effect is likely benefiting overall supply chain players. We further upgraded KYEC (2449 TT, Buy) in Mar-26 following product mix optimization and margin expansions for both the companies. As devices become more complex, testing duration will naturally extend; and, if we take nVidia's (NVDA US, Not rated) AI GPUs as an example, and index the final test (FT) time of Hopper to 1, we estimate 4x for Blackwell and ~7x for Rubin. For system-level test (SLT), if we set Hopper to 1, we estimate 1.5x for Blackwell's SLT time and 2.5x for Rubin's. For burn-in test (BIT), we estimate the test time to likely double from Blackwell to Rubin as well. The extended testing times should be reflected as increased testing content in the cost structure; furthermore, considering the higher hourly rates, we estimate the testing content costs (defined as the sum of FT, BIT and SLT) in nVidia Rubin could rise to 3.3% of the total cost vs. 2.5% for Blackwell and 1.9% for Hopper , leveraging our supply chain analysis (Fig. 15 ).

Complexity of testing processes - from advanced packaging and additional insertions; necessary test hardware upgrades to address testing challenges

Advanced packaging is driving testing complexity as well, given that: 1) as mentioned, with devices becoming more complex, the testing duration will naturally extend; 2) testing challenges to cope with new packaging trends such as larger package size, high pin count, and fine pitches, etc (Fig. 25 ); 3) power and thermal management is becoming increasingly important for surging chip TDP (Fig. 26 ), and notably, if GPU-on-GPU stacking comes through (we likely estimate in Feynman, see report ), and; 4) more highend PCB/interposer materials are used for ultra-high speed signal transmission (see report for PCB material upgrade trend). We observe the following emerging trends in the testing process: 1) increasing efforts around chip probing (the 'shifting-left' trend to ensure KGD [known good die]), 2) additional insertions to be added to the existing IC testing flow such as BIT and SLT, following extreme user cases such as AI/HPC, and higher requirements to address multi-core coherency, and higher-speed interfaces, etc. The chip testing process needs to be optimized to cope with advanced packaging technologies, and it is necessary to upgrade test hardware such as test equipment and interface as well. Beyond standard specification and material upgrades, we anticipate growing adoption of MEMS probes in probe cards , enhanced thermal/high-speed and high-current capabilities in sockets , and improved tray sizing with thermal management systems in handlers - all driving increased customization requirements.

CPO still in early stages; but substantial opportunities beyond

TSMC (2330 TT, Buy) first introduced the concept of Compact Universal Photonic Engine (COUPE) in 2021. It then debuted COUPE based on hybrid bonding to directly bond electric IC (EIC) and photonic (PIC) together in 2023. At the North America Technology Symposium in 2026, TSMC announced it would bring the world's first 200G micro-ring modulator (MRM) with COUPE into production in 2026, adding to further scale up to a 400G modulator with multiple wavelengths and multi-row fiber array units (FAUs) by 2030. TSMC believes co-packaged optics (CPO) with COUPE on substrate provide 4x power efficiency and 10x latency reduction vs. copper wire, and COUPE on interposer could further enhance performance to 10x power efficiency and 20x latency reduction. Two separate dies (EIC and PIC) comprise the important parts of optical

Research Analysts

Semiconductor

Vivian Yang - NITB vivian.yang@nomura.com

+886(2) 21769970

Eric Chen, CFA - NITB eric.chen@nomura.com +886(2) 21769965

Aaron Jeng, CFA - NITB aaron.jeng@nomura.com +886(2) 21769962

engines (OE), and the optical engines will then be put on the same interposer or substrate with the ASIC (application-specific integrated IC). The optical engine (OE) will need to go through a series of testing at both component level and module/system level to ensure that it can successfully communicate with the ASIC that sits next to it (usually are switch chips, at current development status). As well, the system as a whole requires additional testing. Our understanding of CPO testing insertion is as follows and as shown in Fig. 6 : Insertion 1 is PIC and EIC single-sided wafer-level test; Insertion 2 is double-sided wafer-level test after hybrid bonding; Insertion 3 may include two optical engine (OE)level testing steps after singulation - before and after packaging (attach FAU [fiber array unit]/receptacle/structural reinforcements), and Insertion 4 is the module-level test after the optical engine is mounted on the substrate. While final testing flows and vendor selection could vary by customer, we provide potential candidates for CPO insertions in Fig. 18 .

Stock calls: remain positive on testing supply chain players in our coverage

In this report, we extend our coverage from OSATs to test interface and equipment makers in Taiwan, as we believe they are key enablers in the chip testing process, to work as gatekeepers and ensure fewer failures in later stages. We also notice that vendors command vital strategic value in an industry-wide supply-constrained environment, and they have better pricing power than before. We believe that testing process sophistication, spec/content upgrades, share gain and order overflow from AI ripple effect, and supply constraints should elevate testing supply chain vendors to a pivotal seat. We keep our view from our latest sector view (end-June) that we haven't reached AI cycle peak , initiate coverage of MPI (6223 TT) , WinWay (6515 TT) , Hon Precision (7769 TT) , and resume coverage of Chroma (2360 TT) , all with Buy ratings. We also reiterate Buy on ASE and KYEC . Excluding innovative products still in the incubation stage, these companies already posses substantial project pipelines serving a diverse range of AI chip customers, providing strong order visibility for the next several years (judging from their capacity expansion plans).

Key risks to our investment theme

Major risks include: 1) hyperscalers' capex outlook and comments on AI; 2) an overall slowdown in AI demand along with disappointing monetization progress; 3) a deceleration in new product migration and upgrade cycles, limiting value content growth, and; 4) delays or reductions in capacity expansion plans.

Fig. 1: Stocks for action

Company description:

ASE

The world's largest outsourced semiconductor assembly and test (OSAT) vendor

Hon Precision

FT/SLT handler provider with 70-80% FT and 20-30% SLT

Chroma

Power test (~50% of parent) and semi/photonic test (~45%) equipment maker

MPI

Leading probe card supplier with 70% of total revenue; rest from testing equipment

KYEC

World's top 10 outsourced semiconductor assembly and test (OSAT) firm

WinWay

Leading test interface suppliers with combined 70% of total revenue from sockets and probe cards

Note: Priced as of 22 July 2026.

Source: Bloomberg Finance L.P., Nomura estimates

Fig. 2: Semi test sector valuation comparison

Note: Priced as of 22 July 2026.

Source: Company data, Bloomberg Finance L.P., Nomura estimates

Advanced Semi Testing: Chip upgrade; testing ahead

Our theme in charts

Fig. 3: Core thesis of this report

Multiple designs

Large package

recommendations substrate

PLP

large form factor

Advanced packaging methods innovate every day...

Source: Nomura research

CPO

electro-optical integration

Find failures before packaging to reduce scrap costs and maximize package yield

Fig. 4: Additional testing required in AI era

New Insertion

Wafer

Fabrication

Mission

Model

Probe?

HBM Wafer Sort

Source: Teradyne, Nomura research

Fig. 5: Semiconductor test equipment and interface maker overview

Source: Company data, Nomura research

Fig. 6: CPO insertion flow

EIC

Respective EIC & PIC

wafer-level test

Silicon

EIC Silicon

Note: This is a conceptual illustration, not specific to any company or project.

Source: Nomura research

Fig. 7: CPO insertion flow and potential suppliers

Source: Nomura research

Fig. 8: Comparison of major global tester and handler makers

Note: Market cap data as of 17 July 2026.

Source: Company data, Bloomberg Finance LP, Nomura estimates

Insertion 2

Insertion 3

Insertion 4

Active Thermal Control (ATC) Roadmap

TDP (W)

7,500

Fig. 9: Major logic chip products and their testing platforms

B series

R series

F series

Dual-temp

(25~150°C)

Tri-temp

(-80~180°C)

Source: Hon Precision, Nomura research

Source: Company data, Nomura estimates

Fig. 10: Thermal control becomes more critical along with AI/HPC chip performance advancements

Source: Hon Precision, Nomura research

Fig. 11: TDP of nVidia products

Source: Company data, Nomura estimates

6kW?

Paulanges are Malcalve, bouruales between aujavell lech ologies ale tans ton contes Whele solutions Uvellap lest Halawale die shipped belore Chip Mass proauction

Cantilever (peripheral pad)

Fig. 12: Comparison of major Taiwanese test interface suppliers

MEMS probe card

+

wafer-level (probe card)

-12m

Test interface

Note: Market cap is as of 22 July 2026.

Source: Company data, Bloomberg, Nomura research

Fig. 13: Typical pitch regimes and corresponding test interface solutions

Pitch ranges are indicative; boundaries between adjacent technologies are transition zones where solutions overlap

Note: This is a conceptual illustration, not specific to any company or project.

Source: Nomura research

Fig. 14: Timeline of testing equipment and interface preparation

Test hardware are shipped before chip mass production

Note: This is a conceptual illustration, not specific to any company or project. Source: Nomura research

+

shipment

-

100%

80%

60%

40%

20%

0%

vve lematively dooulle oux tom substiale oice lur reyman

10,000

9,000

8,000

7,000

6,000

Fig. 15: Increasing testing content in the logic manufacturing cost of nVidia AI GPUs

3,000

2,000

1,000

Source: Company data, Nomura estimates

Fig. 16: Key GPUs substrate size is growing We tentatively assume 80x115mm substrate size for Feynman

Pascal

Source: Company data, Nomura estimates

Source: Company data, Nomura estimates

Silicon photonics to lead the next frontier

Increased testing demand from unprecedented testing process flows

SiPh/CPO, due to its advantage of power saving and the natural advantage of longdistance data transmission of optics (vs. copper), will likely be the next big thing in semiconductor advanced packaging area, in our view. nVidia's Ethernet scale-out CPO switch is expected to launch from 2H26E along with the Vera Rubin platform (nVidia's first CPO switch Spectrum-6 was announced to be in full production in Mar-2026 , according to Jensen Huang). While a significant volume ramp-up may not happen in 2026, the complexity of the component and high material/production costs enhances the costs of failure - which is the key driver of testing intensity. In our view, the CPO testing ecosystem is now taking shape and will eventually fully unlock business opportunities for testing players.

TSMC first introduced the concept of Compact Universal Photonic Engine (COUPE) in 2021. It then debuted COUPE based on hybrid bonding to directly bond electric IC (EIC) and photonic (PIC) together in 2023. At the North America Technology Symposium in 2026, TSMC announced it would bring the world's first 200G micro-ring modulator (MRM) with COUPE into production in 2026, adding to further scale up to a 400G modulator with multiple wavelengths and multi-row fiber array units (FAUs) by 2030. TSMC believes copackaged optics (CPO) with COUPE on substrate provide 4x power efficiency and 10x latency reduction vs. copper wire, and COUPE on interposer could further enhance performance to 10x power efficiency and 20x latency reduction.

Two separate dies (EIC and PIC) comprise the important parts of optical engines (OE), and the optical engines will then be put on the same interposer or substrate with the ASIC (application-specific integrated IC). The optical engine (OE) will need to go through a series of testing at both component level and module/system level to ensure it could successfully communicate with the ASIC that sits next to it (usually are switch chips, at current development status). As well, the system as a whole requires additional testing.

The process flow of these CPO components could be split into 4-5 test insertions, depending on the way they are sliced. At every stage, different equipment and test interface will be adopted. Although traditional test insertion still exists in some steps, a brand-new market emerges for testing equipment and interface suppliers, that is, cotesting for optical and electrical signals (i.e., electro-optical test). Also note that either wafer probing or final testing require ATE (automated test equipment) to run a specific testing program designed for the wafer or chip, fueling strong tester demand. Usually a tester compiles a series of instrument cards, but to address severe signal attenuation and optical alignment challenges, external, high-frequency/optical measure instruments will be augmented to standard ATE and probers, ensuring signal integrity and testing fidelity. See more details on testing process and hardware in Key test consumables and equipment within the testing process .

A typical process flow, potential suppliers, and industry dynamics could be as follows:

Insertion 1: Respective EIC & PIC wafer-level test

The first step in the CPO test flow is a separate test for both the EIC and PIC wafers. The insertion is sometimes known as a PIC wafer test only, as EIC wafer test has long been a mature technology. At this stage, PIC and EIC will each require their own probe card and prober. The wafer test at this stage is single-sided (i.e. upper end surface)

Insertion 2: EIC die on PIC wafer's wafer-level test

After running through wafer probing for the two respective wafers, the EIC wafer will be singulated into dies, after which good dies will be stacked onto the PIC wafer through hybrid bonding (making it an EPIC wafer). At this stage, a silicon carrier will also be added. The EPIC wafer will then undergo an electro-optical test. Double-sided wafer level testing needs to be here, during which electrical probing is done from the top side while optical probing is conducted from the bottom side. Many suppliers are developing their resources for this stage given its complexity and it is highly value-added. A specific probe card design would then follow after a decision is made on equipment.

Insertion 3: Optical Engine (OE) singulated-die-level test

Post hybrid-bonding, the stacked PIC-EIC would be singulated to an OE chip. At this stage, whether the OE chip needs to be tested before attaching FAU/receptacle/structural

Insertion 2

Insertion 3

reinforcements remains to be seen, and thus some refer the stage as Insertion 3/3.5 (preand post- packaging). From this stage, a testing insertion will take place in OSATs. Whether a FAU or a receptacle will be attached to the diced OE chip would depend on each vendor's architecture. Thereafter, the entire OE chip will undergo testing. Pre- and post-packaging will have different equipment and test interface, with the former resembling die-level test (more like wafer probe) and the latter more similar to chip-level probing. Usually from this stage, an optical test will be conducted for the top surface while an electrical test will be conducted for the bottom surface. EIC Silicon On substrate

Insertion 4: Module/System-Level Test

PIC

After OEs are tested, good OEs will then be mounted on substrate (or interposer in the future). Here, the OEs will be on the same surface with ASICs, working as a CPO module. This insertion needs to ensure the whole module works smoothly, and smooth communication between ASICs and OEs. After this stage, whether a CPO module would then be put on a larger board for System-Level -Test (SLT) remains to be seen.

In our view, the first two insertions will be conducted/handled by foundries, as it is more like wafer-level process and it incorporates EIC and PIC stacking. From Insertion 3, OSATs can play a role. We believe SPIL (under ASE) could be a major service provider initially, but it's also likely that other OSATs can participate after production volume rampup or when more vendors join the field with new projects.

Although mass production is nearing, our industry channel checks suggest there remains significant uncertainties. The testing process is not determined yet, including but not limited to: 1) a good solution for Insertion 2, given highly demanding requirements for double-sided wafer test; 2) whether to go through both die-level and package-level tests for Insertion 3; and 3) whether SLT is necessary after module-level-test in Insertion 4. Also, even if the process flow is determined, what would be the yield? Apart from the above-mentioned, vendor selection for each stage is another uncertainty, and equipment selections will impact the adoption of test interface.

That said, we believe CPO is a painful yet inevitable shift in semi manufacturing. The unstoppable tide of change will provide a brand-new market for testing suppliers. All participants are pushing to innovate and breakthrough engineering limitations, and once they break through technical bottlenecks, and when the market gradually gets matured, these suppliers could enjoy a new landscape of opportunities, in our view.

Fig. 17 - Fig. 18 illustrate our expected insertion flow and potential supplier candidates.

Fig. 17: CPO insertion flow

Note: This is a conceptual illustration, not specific to any company or project.

Source: Nomura research

Insertion 4

Silicon

EIC Silicon

PIC

ASIC

Substrate

Module/System-level test

Teoung proctooes are muleaslyly complatel along wial compier paunagily

Fig. 18: CPO insertion flow and potential suppliers

Source: Nomura estimates

C4 bump or C2 bump Cavity

Fig. 19: An example of CPO testing flow

Microbump

Waveguide ckt switch

Glass Interposer

Microbump

TGV

TEIC

Testing processes are increasingly complicated along with complex packaging

Test 5 & 6

Glass Interposer

Fiber Coupler

• Fibers

PIC Wafer Testing

PIC Wafer Level

Source: ASEH, Nomura research

TSV

HBM STACK

Test 7

Is a Key Strategic Component

Traditionall chipmaking

value chain

Packaging Ecosystem

Testing, now much more important than before

80%

Advanced chipmaking

value chain

60%

40%

20%

time to market.

0%

Role of back-end process is playing an increasingly critical role in chip manufacturing for advanced chips

We maintain our view that the role of back-end process (both assembly and testing) is increasingly important within the semi manufacturing process (Fig. 17 - Fig. 18 ); we highlighted that production of AI chips would benefit back-end packing-and-testing process significantly more than that of smartphone chips (a growth driver in the past decade) in our ASE upgrade report in Oct-2025. Sources: Capital IQ, Gartner, 2019 split; BCG analysis.

Materials

Increasing on estabbished

front end co-development

of packaging technology

materials

• Small increase

As devices become more complex, testing duration will naturally extend; and, if we take nVidia's (NVDA US, Not rated) AI GPUs as an example, and index the final test (FT) time of Hopper to 1, we estimate 4x for Blackwell and ~7x for Rubin. For system-level test (SLT), if we set Hopper to 1, we estimate 1.5x for Blackwell's SLT time and 2.5x for Rubin's. For burn-in test (BIT), we estimate the test time to likely double from Blackwell to Rubin as well. The extended testing times should be reflected as increased testing content in the cost structure; furthermore, considering the higher hourly rates, we estimate the testing content costs (defined as the sum of FT, BIT and SLT) in nVidia Rubin could rise to 3.3% of the total cost vs. 2.5% for Blackwell and 1.9% for Hopper , leveraging our supply chain analysis (Fig. 22 ).

Fig. 20: Back-end process is increasing value with advanced packaging

Source: BCG analysis, Nomura research

Fig. 21: BoM share of back-end process will increase along with advanced packaging

Source: Capital IQ, Gartner, BCG analysis, Nomura research

Fig. 22: Increasing testing content in the logic manufacturing cost of nVidia AI GPUs

Source: Company data, Nomura estimates

Ole/

System / Chiplet resign Desig

Value shift from single die design

(area reduction)

to full system design

3 No significant change

Die/Chiplet

Mig

Shift to smaller dies with larger

nodes due to heterogeneous

integration

Packaging

Package Design

Complex packages

determinants of become key

chip performance

Dil ullis

2,500

2,000

1,500

1,000

500

120

Advanced packaging drives testing intensity

5Y CAGR: 31%

Advanced packaging is still a small portion of total semi packages, but will grow rapidly

2024

2029E

•High-end Packaging

Advanced packaging is driving testing complexity as well, given that: 1) device complexity increase will require a longer testing time; 2) testing challenges to cope with new packaging trends such as larger package size, high pin count, and fine pitches (Fig. 25 ), etc; 3) power and thermal management is increasingly important for surging chip TDP ( Fig. 26 ), and; 4) more high-end PCB/interposer materials are used for ultra-high speed signal transmission (see report for PCB upgrade trend). Advanced packaging technologies such as 2.5D/3D packaging, chiplet architectures, hybrid bonding, and multidie systems will increase interconnect density and complexity significantly. According to Yole's forecasts, the number of high-end performance packages units was just <2% of total IC units in 2024, but it may grow to ~5% of total ICs by 2028E. Given the wellacknowledged physical limit on front-end manufacturing process, we believe advanced packaging will continue to increase its value proportion in semi manufacturing, and subsequently drives testing intensities.

The yield cliff and the criticality of CP KGD in advanced packaging

As the semiconductor industry shifts toward advanced packaging and Multichip Modules (MCM), manufacturers face a severe "yield cliff (Fig. 28 )". Because the overall module yield is the cumulative yield of all individual dies (a multiplier principle, i.e., if two dies, each with an individual yield of 0,9, the package yield will be 0.9*0.9), integrating multiple components significantly amplifies the impact of any defect. For instance, assembling ten dies with each having a 90% individual yield causes the final module yield to plummet below 35% (Fig. 28 ), meaning a single defective die will force the scrapping of an entire expensive package. This geometric yield loss makes the identification of Known Good Dies (KGD) during the Chip Probing (CP) phase absolutely critical. Consequently, CP testing must deploy unprecedented rigour and high-density interface hardware to screen out all marginal defects prior to assembly, ensuring that only 100% functional dies enter the packaging flow to prevent catastrophic cost overruns. This leads to the emerging trend of 'shifting left' as described below.

Fig. 23: Advanced packages account for only a small proportion of total semi packages

Bn units

Source: Yole, Nomura research

Fig. 24: High-end advanced packaging units recorded a 31% CAGR over 2024-2029E

Source: Yole, Nomura research

M wafers, 300mm Eq.

160

140

120|

100

60|

40|

interconnects. Micro and Nanotechnologies/Microelectronics.

100um

20um

(M wafers, 300mm eq.)

Fig. 25: Bump pitch is shrinking

ПІШІ

2018

2019

02634259

Source: TechInsights, Nomura research

Iivuule yelu will oly mically plunge witlout ules will yoon chloug" yielu

Multichip Module Yield vs. Single Die Yield

TDP (W)

100%

7,500

90%

80%

70%

6,000

70%

4,500

2um Pitch

60%

50%

40%

60%

Source: Imed Jani, Nomura research

Source: Imed Jani, Nomura research

Fig. 27: Advanced packaging share of total silicon is increasing rapidly

The ratio to reach 50% in 2026E

Source: TechInsights, Nomura research

50%

3,000

40%

30%

20%

1,500

10%

0%

0

Advanced Packaging Share (%)

99% Die Yield

Fig. 26: TDP of nVidia products

Ampere

A FAIL

6kW?

Source: Company data, Nomura estimates

Fig. 28: Advanced packaging drives importance of KGD

Module yield will significantly plunge without dies with good enough yield

Source: Delphon Industries, Nomura research

Testing process changes along with chip complexity

We briefly introduced the semiconductor testing process in our Dec 2024 report (see KYEC initiation ). Typical semiconductor testing could be divided into chip probing (wafer sort/CP) and final testing (FT), and FT could include/be extended to burn-in test (BIT)/system-level -test (SLT). Along with higher chip complexity, and thus higher chip contents from advanced technologies, some changes have emerged in testing flows:

Growing trend of testing flow: additional test insertions and trend of shifting left

New technologies such as CPO will create brand-new testing insertions (see Silicon photonics to lead the next frontier ), which are totally different from the traditional testing process, creating more opportunities for the testing supply chain. Apart from CPO, many new technologies are under development such as panel-level-packaging (PLP), SoIC/3D stacking, glass core substrate (see Fig. 32 ; we mentioned some technologies in our Apr and June Anchor reports). New packaging methods will require new testing techniques (equipment, consumables, and processes). As many of these methods are still under development, we would only have clarity on the testing process when mass production approaches.

As for the existing testing flow, in the monolithic die era, assembly defects and functionality at speed are tested at package level, and functional requirements for these packages parts are similar to those at the die level. Migrating to the heterogeneous package era, when dies in different process nodes or even from different manufacturers (e.g. HBM) are put together in one package, more comprehensive testing for individual dies is necessary. Some assembly defects after the package of a particular die is hard to detect, and functionality of each single die could be different from the packaged level IC.

As shown in the yield cliff effect (Fig. 28 ), all of these result in an emerging trend of

Te tollu Ul ormully loll

BACK END

Front End Test coverage

'shifting left', namely the front-end testing process is increasingly critical: one die defect in a package will create waste of other good dies, and the cost of yield increases exponentially. More front-end testing demand is leading to higher demand for probe cards (Fig. 29 - Fig. 31 ). However, increasing the focus on wafer probing does not necessarily mean it would be at the expense of final test , as single ICs function, speed, tolerance, electronic consumption, electronic emission and heat diffusion, etc, are also crucial to be reviewed at the package level, as well as seamlessly integration between different dies. The die-to-die interconnect within a package also requires additional testing efforts. The assessment metric, Defective Parts Per Million (DPPM), would be reviewed in both individual die level and packaged IC level.

Fig. 29: Frond-end test becomes more critical in the chiplet era

The trend of shifting left

Final Testing

Level

Large Yield Impact

For each mis-screened die:

Front End Test coverage

Fig. 31: Shifting left drives more probe card demand

Source: Technoprobe, Nomura research

Fig. 30: Cost of yield increases exponentially in the APT era

Source: Technoprobe, Nomura research

Source: Technoprobe, Nomura research

Fig. 32: Packaging technology trends

Advanced packaging will drive innovations in testing as well

Source: Yole, Nomura research

SoIC also drives test complexity, along with thermal management

We believe the development of SoIC at TSMC is worth tracking and the die stacking is driving test complexity because it buries critical die-to-die interconnects deep within silicons, which are physically inaccessible to traditional test probes. Testing must therefore shift to a more rigorous, pre-bonding wafer-level test (i.e., 'shifting left') to guarantee known good dies, since any single defective layer will ruin an entire costly multi-chip stack. Furthermore, stacking inevitably creates extreme thermal-density bottlenecks and structural stresses, forcing test systems to implement complex and possibly dual-sided probing as well as real-time thermal monitoring to identify detects.

TSMC is committed to further shrinking bond pitches for logic devices, and is currently targeting N2-on-N2 with a 6um bond pitch to be in production in 2028E, and A14-on-A14 with a 4.5um bond pitch to be in production by 2029E. TSMC has been producing N7-onN7 with a 9um bond pitch since 2023, and stacking with a 6um bond pitch has also been in volume production since 2025. The vertical logic stacking of SoIC theoretically could augment transistor counts per package, an outright indicator of computing power, without extra footprints (vs CoWoS/2.5D packaging that expands horizontally to accommodate more chips).

We foresee further elevating thermal challenges moving to Feynman (F100), slated for 2028E. nVidia at the GPU Technology Conference (GTC) unveiled tplans to adopt 3D stacking starting from the Feynman platform (report ). Currently, AMD (AMD US, Not rated) leads the adoption of SoIC at TSMC (starting from MI300-series), and in the latest MI450, we believe AMD stacks four top dies (four XCD) on two reticle-sized active interposers (I/O dies), in which each top die scales to about 1/3 reticle size (Fig. 92 ). Our channel checks suggest nVidia will be more aggressive in chip specs by stacking a reticle-sized GPU die on top of another for the Feynman platform, the first-ever GPU-onGPU SoIC stacking, which would lead to higher computational power even with limited growth in interposer reticle stitching size (c.6x reticle, see footprint in Fig. 93 ; up from c.5x in Rubin). Such a practice theoretically exacerbates thermal dissipation challenges.

We note there are also variants of SoIC for a broadening application base. As discussed in our 'Global Advanced Packaging - The evolution of CoWoS, SoIC and InFO ' report, our supply chain checks suggested Apple (AAPL US, Not rated) has been likely working on a few hybrid bonding/SoIC projects for M-series silicon. Apple debuted M5 Pro and M5 Max in March 2026 (press ), and we witness that Apple disaggregates CPU and GPU blocks in the previous monolithic die into discrete sub-dies, and TSMC uses SoIC-MH to bond CPU and GPU chiplets onto a passive interposer using bump-less face-to-face hybrid bonding (Fig. 39 ). While the SoIC-MH architecture is somewhat similar to 2.5D CoW, the M5 Pro/M5 Max can achieve substantially higher die-to-die interconnect density by replacing micro-bumps (2.5D CoW) with bump-less hybrid bonding, and reduce the parasitic losses (or 'chiplet tax') in chiplet-based layout.

Apart from logic-on-logic stacking, TSMC's COUPE could also serve as a key capacity

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TERADYNE

High End Performance Packaging 2023 | Report| wwwvolearoup.com |02023

Source: Yole, Nomura research

Fig. 35: Evolution of packaging method

Source: ASEH, Nomura research

Fig. 36: Interposer on Substrate packaging technologies From CoWoS to CoPoS

Source: Teradyne, Nomura research

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Integration driver of SoIC, in our view, and the company is exploring DRAM-on-logic for high bandwidth and low latency for future AI inference decoding applications. TSMC has laid out the plan to grow SoIC capacity at a >90% CAGR over 2022-27E (report ). Our current assumption is that TSMC could install >40kwpm of SoIC capacity by end-2028F, from 5kwpm by end-2025. (3D Fabric) Intel: overad CAR 22-26 3996 $1OM, $716M e.g. TSMC CoPoS

TSMC

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$26M

Source: Yole. Nomura research

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Source: Yole, Nomura research

• Co-EMIB

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Samsung.

X-Cuba

Source: Teradyne, Nomura research

Find failures before packaging to reduce scrap costs and maximize package yield

Fig. 38: Additional testing required in AI era

New Insertion

LPDDR

Wafer

Fabrication

LPDDR

Mission

Model

Probe?

Source: TechSearch International

HBM Wafer Sort smaller chips

Source: Teradyne, Nomura research

Fig. 39: A cross section of SoIC-MH in Apple M5 Pro and M5 Max

Source: Besi, TechSearch International, Nomura research

Testing equipment and consumables are clear beneficiaries under the big theme of advanced testing

We have been turning increasingly positive on the overall back-end supply chain since 4Q25. Previously, we mainly focused on OSAT vendors, given its high correlation with front-end manufacturing. However, we now expand our coverage to testing equipment and consumables. Yole estimates that the cost of testing high-end performance packages (equipment and consumables) could be between 10% and 15% of current total test costs, and the institution also forecasts that overall test equipment and test consumables to witness a 5%+ CAGR over 2025-30E, reaching USD23bn in 2030E . TechInsights also projects test hardware spending to exceed USD20bn-plus in 2029E, from slightly higher than USD15bn in 2025E, at a 10% CAGR (Fig. 40 ).

Coupled with rising BOM share, we believe testing equipment and consumables could be

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Test Equipment a market with considerable upside potential. Other than the overall TAM increase and new testing opportunities from innovative testing methods, we have witnessed market share gains for key Taiwan suppliers, either because: 1) their key customers gain share in the AI chip space; or 2) they gain share from overseas vendors. See Taiwanese players are gaining traction in the sector for details.

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Thus, we initiate coverage on key testing interface vendors WinWay and MPI, as well as initiate/resume leading testing equipment vendors Hon Precision and Chroma . We expect these companies' top line and bottom line to both outgrow the market's, mainly driven by share gains. We also reiterate Buy on ASE and KYEC . SoC Test

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Fig. 40: Test hardware spending trend

Source: TechInsights, Nomura research

Fig. 42: Both test equipment and test consumables to record a 6%+ CAGR over 2023-28E

Source: Yole, Nomura research

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+

800

8.70%

pogo pin

2024

•Other Test

•Test sockets

Burn in sockets

•Probe cards

Interface boards

•Test related equipment pitch (um)

2025

2026E

Handlers

• Probers

Source: TechInsights, Nomura research

Fig. 43: Cost of test equipment and consumables

Total market revenue was USD15.4bn in 2024

Source: Yole, Nomura research

Fig. 44: Typical pitch regimes and corresponding test interface solutions

Pitch ranges are indicative; boundaries between adjacent technologies are transition zones where solutions overlap

Note: This is a conceptual illustration, not specific to any company or project.

Source: Nomura research

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Fig. 45: Timeline of testing equipment and interface preparation

-12m

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Note: This is a conceptual illustration, not specific to any company or project. Source: Nomura research

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How big is the test consumable market?

Test interface, or test connectivity/test consumables, are components used during test processes, between testers and devices under test (DUT), and these components enable electrical connections/signal transmission between devices and equipment. TechInsights estimates the test connectivity market reached over USD5.5bn in 2025, and it will reach USD8bn by 2028E (Fig. 46 ). Probe cards, sockets and device interface boards (DIB) are the three major categories, with probe cards accounting for 40%+ of the market in 2023-25. Test sockets exceeded DIB to become the second-largest segment in 2024, recording 21% of the test connectivity market, and in 2025, wafer-level-burn-in (WLBI) and BI sockets gained share (Fig. 48 - Fig. 49 ). That said, both market researches from Yole and TechInsights suggest probe cards would record the highest revenue CAGR over 2025-30E (Fig. 47 ) - underscoring the views of putting more focus on wafer sort and that competition in the probe card segment will intensify.

Fig. 46: Semiconductor sales vs. test connectivity sales

Note: TCS: Test Connectivity System

Source: TechInsights, Nomura research

Fig. 48: Test connectivity market - 2025

Probe card maintains the largest segment while burn-in socket is gaining share

Source: TechInsights, Nomura research

2030

21%

•Test Sockets

•Probe cards

Fig. 47: Test connectivity - relative 5-year growth trends

Source: Yole, Nomura research

Fig. 49: Test connectivity market - 2024

Test socket exceeded DIB in 2024

Source: TechInsights, Nomura research

9000

1.6

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17%

Test Sockets: 7.0% CAGR

4%

Burn-in Sockets: 5.3% CAGR

Test Interface Boards: 4.9% CAGR

6%

7%

Probe card accounts for 40%+ of the test connectivity market

Probe card market to grow from ~USD2.8bn in 2025 to USD4.5bn+ in 2030E

According to TechInsights' statistics, total semiconductor probe card market sales recorded ~USD2.8bn in 2025. Within the probe card market, nearly USD2bn was MEMS probe cards, accounting for around 70%. TechInsights projects that the probe card market will exceed USD4.5bn in 2030E, recording a 11.1% CAGR over 2025-30E ( Fig. 50 ).

FormFactor, a leading probe card vendor, compared semi probe card sales with total semi sales, and concludes that over the past 16 years, investment in probe cards has tripled, and test intensity is increasing to avoid chip failures. The trend is fueled by increased adoption of advanced packaging. The intensity increased 10% to ~0.4% in 2024 (Fig. 51 ).

Two global players leads the sector - Technoprobe and FormFactor; MPI follows in non-memory sector

There are two leading probe card vendors globally - Technoprobe (TPRO IM, Not rated) and FormFactor (FORM US, Not rated). Yole's statistics show that FormFactor leads in total own make IC probe card vendors, but if excluding memory probe cards, Technoprobe would take the lead. Based on 2025 probe card revenue, FormFactor recorded USD638 mn, taking a 23% share of the probe card market, and Technoprobe stood at the second place with a ~17% share. The top 5 vendors took a combined 73% share in 2025 (Fig. 52 - Fig. 53 )

FormFactor excels in both logic and memory: A key memory supplier accounted for ~30% of its total revenue in 1Q26, and nVidia surpassed 10% for the first time in the same quarter thanks to networking applications. Besides, Intel (INTC US, Not rated), Samsung (005930 KS, Buy), and TSMC are also its top customers. Compared to Taiwan peers, FormFactor has more standard products (e.g.memory) and could be less willing to offer customization. However, the company has begun to ramp test system for CPO Insertion 1 and raised CPO revenue guidance during its April earnings call, and CPO is a segment we believe has significant growth potential for the testing supply chain (as mentioned in Silicon photonics to lead the next frontier ).

Technoprobe dominates in MEMS: Technoprobe has in-house MEMS fab utilizing semiconductor lithographic precision technologies, and its expertise in MEMS technology supported its share gain from ~8% in 2018 to ~16.5% in 2025, according to Dataintelo Analysis; specifically, it took 60% of the MEMS logic probe card market in 2024 (USD937mn market size). It sells not only turnkey probe cards, but also sell probes externally.

Micronics Japan (MJC) and Japan Electronic Materials (JEM) specialize in memory probe cards: these two Japanese players have niche in the memory probe card segment. MJC (6871 JP, Rating suspended) concentrates on the high-end memory/HBM segment which has a larger revenue scale, while JEM (6855 JP, Not rated) slightly lacks behind MJC and FormFactor, but it has higher exposure to NAND.

MPI aggressively catches up in the MEMS market: MPI leads in cantilever and vertical probe cards in terms of market share (Fig. 56 ), but the company is also proactively expanding MEMS capacity to catch up with testing requirements for AI chips, and to compete with top suppliers.

We see more Taiwanese players targeting the probe card market

Given that probe card is the largest segment in the test connectivity market, and with the market expecting the probe card market to outgrow other segments despite having a large base (per abovementioned reasons and trends), we see more activities in the field.

We see MPI gradually take share in the self-made IC probe card market, from No.5 in 2021 to No.4 since 2023 (surpassed JEM in 2023, Fig. 54 ). MPI's revenue share in the probe card market grew from ~6% in 2023 to ~10% in 2025 (Fig. 53 ). Excluding memory probe cards, MPI has maintained its position at No.3 (Fig. 55 ), after Technoprobe and Form Factor. WinWay and CHP T (6510 TT, Rating suspended) are also good examples, both of which have their own expertise with decent market position (socket and PCB), but they are actively pursuing opportunities to make inroads in the probe card market. WinWay's progress is ahead of CHPT with its probe card vendor (non-memory) ranking jumping from No.19 in 2021 to No.5 in 2025 (Fig. 55 ), mainly on strong demand from gaming graphics. See Taiwanese players are gaining traction in the sector sections for details between these Taiwanese suppliers and their offerings.

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MEMS continues to be major type, roughly 70%

2019

• FormFactor

JEM

FormFactor

Source: TechInsight, Nomura research

75%

70%

Source: TechInsight, Nomura research

Fig. 52: Total probe card market by vendor

Despite stable ranking, MPI is gradually gaining share

Source: Company data, Nomura research

Fig. 54: Global own make IC probe cards venders ranking MPI is gradually gaining share

Source: Company data, Nomura research

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Fig. 51: Investments in probe is increasing in recent years

0.41%

• Technoprobe

Source: FormFactor, Nomura research

Fig. 53: Market share split of 2025 total probe card market

Top 5 players account for ~70% of the market

Source: Company data, Nomura research

Fig. 55: Global non-memory probe cards venders ranking

Taiwanese players mainly address non-memory market

Source: Company data, Nomura research

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Fig. 56: Probe card competitive landscape in 2024

TPI and FormFactor leads non-memory MEMS market

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Source: TechInsights, Nomura research

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Fig. 57: Global probe card market by revenue from vendors' headquarters (2025)

Europe

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Source: TechInsiahts. Nomura research

Source: TechInsights, Nomura research

Socket market size relatively stable with shifting market share

Total test socket market revenue to witness mid-single-digit CAGR over 2025-30E

Sales of combined test sockets (including packaging testing, SLT and engineering testing) and burn-in sockets were estimated at ~USD1.9-2bn in 2025E (~36% of the test connectivity market), and are projected to reach USD2.4bn in 2030E, at a ~5% CAGR over 2025-30E, according to TechInsights. Test sockets account for ~70% of total socket market, and burn-in sockets the remaining ~30%. Similar to the market for other testing hardware, that for sockets is also growing in tandem with advanced packaging units (Fig. 23 - Fig. 24 ), and TechInsights forecasts BI socket revenue to slightly outgrow the test socket market's revenue over 2025-2030E, at 5% and 4% CAGRs, respectively ( Fig. 58 ). However, Yole's projection suggests test sockets could outgrow BI sockets over 2025-30E, at 7% and 5.3% CAGRs, respectively ( Fig. 61 ) , citing reasons such as increased use of SLT and WLBI (WLBI uses specialized probe cards), and relatively stable burn-in testing time.

Test socket usage increases rapidly with longer testing times, larger package sizes, complicated package methods and increased test insertions (for example, additional insertions for CPO). On the other hand, we expect more AI chips to adopt the burn-in process, penetrating gradually from nVidia GPUs to key ASICs such as TPUs/CPUs, and conducting burn-in could potentially increase FT processes as well (FT1 and FT2, before and after burn-in). We believe different vendors have their own considerations on testing processes, also depending on end application and user scenarios, but we expect an increase in testing intensity overall. We therefore like the overall testing sector, spanning from OSATs and equipment vendors, to consumables suppliers.

Different vendors specialize in different types of sockets

There are many socket players in the world, focusing on separate fields, with no single player dominating the market (top players each only take a 5-15% share in the test socket market, and each take a 10-20% share in the burn-in market) ; thus, the gaps between players are also relatively small, especially after the AI/HPC boom - the ones that win key projects will show significant revenue expansion with market share gains in the periods of test interface shipment (usually before chip mass production), in our view.

Key players in the field include:

Yamaichi (6941 TT, Not rated): a leading Japanese vendor in both test and burn-in socket markets with diversified end-application exposure, spanning from auto to smartphones. Yamaichi specializes in fine-pitch pogo pin test and burn-in sockets, and has close relationships with IDMs/automakers. It also engages the AI/HPC sector through HBM (primarily Samsung). Other notable customers include TSMC and Apple. Yamaichi and Enplas both have expertise in precision engineering.

LEENO (058470 KS, Buy): LEENO is a vertically integrated socket player based in South Korea, mainly in test sockets field with less burn-in exposure. 100% in-house manufacturing drives its industry-leading profitability and supports the shortest lead time, in our view. LEENO provides solutions to both memory and logic product makers; its flagship smartphone AP is one of its key revenue growth drivers (e.g., from Apple, Samsung, MediaTek and Qualcomm [QCOM US, Not rated]).

FEINMETALL

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

1%

Enplas (6961 JP, Not rated): another Japanese socket vendor, but highly skewed to burn-in sockets with proprietary micro fabrication technology. Other than GPUs, Enplas has been expanding its exposure to AI ASICs and they set SLT market as a growing area to address, besides burn-in. Automotive SoCs are also one key driver of its semiconductor business.

Yokowo (6800 JP, Not rated): Yokowo specializes in micro precision processing technology, offering a broad range of contact probes and circuit testing connectors. It provides sockets itself, but it also sells pins to external vendors such as WinWay. In addition, Yokowo also provides pogo pins to probe card vendors for RF applications due to high-current features. Well-known customers include Intel and Qualcomm.

ISC (095340 KS, Not rated): ISC is aggressively pushing its proprietary elastomer-based conductive silicone rubber technology, with one notable partner Samsung. Following SKC's (a subsidiary of SK Group) acquisition of ISC in 2023, the latter (ISC) has become more structurally aligned with the memory sector.

Smiths/IDI (SMIN LN, Not rated): Smiths Group purchased IDI (Interconnect Devices) in 2010 and transformed it to Smiths Interconnect. In 2025, the Smiths Interconnect division was sold to Molex. The company is well known for its DaVinci series coaxial sockets, focusing on high-frequency connectivity. The company are key suppliers to key GPU and ASIC vendors.

WinWay: WinWay mainly focuses on logic space test sockets, and its close relationship with top key fabless vendors has led the company to rapidly gain share in the market, along with the AI/HPC/advanced packaging trend. The company has expertise in highdensity coaxial sockets, and it has further enhanced its proprietary product, HyperSocket, to capture further testing challenges.

Cohu (COHU US, Not rated): Cohu has broad product portfolio covering ATEs, handlers, sockets, burn-in boards, and thermal solutions. Due to its heavy exposure to more legacy products (auto, industrial, RF), its market share in sockets has gradually faded.

AI/HPC set the stage for high-performance socket players such as WinWay

Compared to the probe card market, the socket market is relatively dynamic, as shown in Yole's peer ranking over the past several years, with a reshuffle almost every year (Fig. 62 - Fig. 64 ). In our view, two factors impacted the competitive landscape: the consumer/mobile downturn in 2023, and the AI/HPC boom that followed which rewarded vendors positioned in high-performance test sockets.

The top vendor has alternated between Yamaichi and LEENO: The likely explanation lies in their different end-market exposures. The 2023 downturn hit memory, smartphones, and consumer semiconductors hard (segments in which Yamaichi has deep roots), while LEENO's strong position in probe pins and sockets tied to the Korean memory ecosystem let it hold up relatively better and claim the 2023 crown. As memory (particularly HBM for AI) rebounded strongly in 2024-25, LEENO regained momentum and retook the first place in the preliminary 2025 ranking.

Yokowo's and Cohu's disappearances: Fourth overall in 2022, Yokowo fell out of the top five entirely from 2023 onwards, which is consistent with heavy exposure to smartphone and consumer applications that never recovered to pre-2023 levels (Fig. 62 ). Cohu climbed from third to second in 2023 but then fell back to the third place in 2024 and fifth in 2025 (Fig. 63 ) - a pattern consistent with its broader exposure to automotive and industrial test, both of which did not see strong demand recovery in 2024-25 while AI boomed.

The AI-driven winners: WinWay and Smiths Interconnect are widely associated with high-performance test sockets for AI accelerators and HPC devices, where socket content per device (larger packages, more pins, higher power and bandwidth requirements) is far more valuable than in consumer parts. We observe the two companies ranking gradually rose in past several years (Fig. 63 ).

Compared with the test-socket market, burn-in sockets look remarkably calm: The same large names appear nearly every year as market share leaders, with only the order changing (Fig. 64 ). As mentioned above, more and more AI chip companies have adopted the burn-in process, but different technology focuses in burn-in (qualification cycles, reliability requirements, long-standing customer relationships) have kept the same players entrenched, while the test socket segment is where share seems to us to be genuinely up for grabs, because AI design wins can transform a vendor's revenue in a

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Fig. 58: Global test and burn in socket revenue

Total socket revenue to reach USD2.4bn in 2030E

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Source: Yole, Nomura research

Burn in socket suppliers are relatively stable

1

2

3

2023

2024

Probe Cards: 8.7% CAGR

Test Sockets: 7.0% CAGR

Burn-in Sockets: 5.3% CAGR

Fig. 59: Global socket market by application

Memory market has outgrown non-memory despite smaller portion

......... Smiths Interconnect

• Yamaichi

• Enplas

• Okins

Source: TechInsights, Nomura research

Fig. 61: Yole projects higher revenue growth for test sockets vs. burn-in sockets

Source: Yole, Nomura research

Fig. 63: Global test socket market ranking WinWay and LEENO took the lead in the past two years

Note: *2025 ranking is preliminary.

Source: Yole, Nomura research

Fig. 64: Global burn in socket market ranking

Burn in socket suppliers are relatively stable

Note: *2025 ranking is preliminary.

Source: Yole, Nomura research

2022

Source: TechInsights, Nomura research

Fig. 60: High-performance socket market to grow at 9% over 2025-30E

While traditional socket market may stablise or even decline

Source: Yole, Nomura research

Fig. 62: Global test and burn in socket market ranking

Ranking changes every year in total socket market

Note: *2025 ranking is preliminary.

Source: Yole, Nomura research

2025

.........•

2025

2022

2023

High Performance

• Smiths Interconnect yealo

Cooperation between testing industry players

An interesting point within the testing sector is the close relationships between companies. We see a wave of consolidation (Fig. 65 ) and strategic alliances, possibly driven by the need to tightly integrate ATE with test sockets and probe cards to address the complexities of advanced packaging (like chiplets and CoWoS), HBM, and silicon photonics. We also see substantial outsourcing activities between the players, likely due to the supply-constrained environment, even though turnkey/total solutions still produce higher margins/ASPs.

External procurement of probes increasingly common

In Aug 2025, WinWay and Yokowo announced an MOU on a strategic alliance. Based on our understanding, WinWay outsources a part of its socket pogo pin from Yokowo. In Oct 2025, CHPT and Yokowo signed an investment deal in which CHPT will invest USD2mn in Yokowo via subsidiary TestPro (unlisted), and Yokowo will invest USD2mn in CHPT. The cooperation between CHPT and Yokowo could be traced back to 2018, as CHPT wanted to focus on MEMS pins, but still needed pogo pins to test large pitch wafers for RFFE, power devices and/or sensors. Yokowo is one of the most vertically integrated probe manufacturers - it runs large fleets of probe-making lathes with fully automated assembly and inspection lines, plus in-house moulding and plating. Through external procurement from Yokowo, the two players can either relieve capacity shortage, or spend more time on focus areas. On the other hand, Yokowo can broader its customer base and penetrate into the AI/HPC market through the two key players.

In Dec 2025, Technoprobe and WinWay signed an agreement for TPI to act as a developer and manufacturer of testing solutions, granting WinWay the right of use for fiveyear period. Via the agreement, WinWay secures necessary probes to support its business ambition in the MEMS probe card market targeting the most advanced AI chips.

ATE vendors divest test interface divisions for hyper-specialisation while making equity investments to strengthen collaboration toward advanced packaging

We observe some industry dynamics in the test hardware markets, between ATE and probe card vendors. In 2020, FormFactor acquired probe card assets from Advantest (6857 JP, Buy) to increase exposure in the NAND Flash market. In Nov 2023, Teradyne (TER US, Not rated) and Technoprobe announced a strategic partnership in which Teradyne invested USD516mn in TPI, and TPI acquired TER's Device Interface Solutions (DIS) business for USD85mn, only several months after they acquired TIB maker Harbor Electronics (unlisted) in Aug 2023.

Advantest is also aggressive, after assembling Advantest Interconnect (AIS) through serial acquisitions (Essai sockets, R&D Altanova boards, Shin Puu test-board PCB), it invested in early 2025 in both Technoprobe and FormFactor , with technology and PCB manufacturing partnerships. In our view, these activities imply two converging forces: hyper-specialization and consolidation. ATE manufacturers are increasingly shedding peripheral hardware divisions to focus exclusively on their core competency, i.e. complex system architecture and software. On the other hand, interface providers concentrate purely on micro-mechanical and metallurgical innovations. Simultaneously, this extreme division of labor has triggered a wave of strategic M&A and cross-investments among key players. By joining forces, we believe these market leaders are aiming to ensure that highly specialized test instruments and interface hardware are co-engineered seamlessly to deliver turnkey, high-yield solutions for the next generation of silicon.

The ecosystem co-engineering trend is particularly pronounced in the era of advanced packaging and when complex testing processes are required. Given higher and higher costs of failure, all players within the testing supply chain are activity forming crossboarder cooperation. One example is FormFactor's TRITON system (a comprehensive test-cell), developed by FormFactor (interface/prober), Advantest (ATE), and Tokyo Electron (8035 JP, Buy; prober) to address single-sided wafer testing (Insertion 1, in our view, see Silicon photonics to lead the next frontier ). In the AI test era, co-design value across tester, boards, and probes has risen sharply, elevating interface hardware from consumables to a strategic layer to be owned or bound.

Fig. 65: Major M&As in testing sector

Cancadel Axext!

Advantest acquires essai

Teradyne acquires Lemsys

ADVANTEST

2016

Advantest acquires

R&D Altanova

ADVANTEST

Zero One acquires advanced PCB

Source: TestConX, Nomura research essai

REDE

Vitanova

Technoprobe acquires Harbor

Electonics

HARBOR

Cohu acquitesMCT

Taiwanese players are gaining traction in the sector

Along with this report, we initiate coverage of four companies with Buy rating s : MPI (6223 TT), WinWay (6515 TT), Hon Precision (7769 TT), and resume coverage of Chroma (2360 TT) , which has products spanning probe cards, sockets, and testing equipments, respectively. We hold an overall positive view on the testing sector and each player, as each specializes in different segments, and has own long-term partnership ecosystem and customer base. They may compete in some specific projects, but as long as AI/HPC chip demand sustains, we see the market keep enlarging and can fit many players in the field. Also, we believe Taiwanese players as a whole will gradually gain share from overseas leading players, likely due to close relationships with key fabless and spillover effect from capacity optimization, share gains of their customers, and advantage to provide on-site real-time support in the Taiwan semiconductor ecosystem.

Test interface quartet: MPI, WinWay, CHPT, and Keystone

Taiwan hosts a distinctive cluster of semiconductor test-interface suppliers that emerged around the comprehensive ecosystem (foundries/fabless/OSATs). The four companies are usually discussed together, but they occupy different positions along the test-interface stack: probe cards, load boards, sockets etc. See Fig. 66: Comparison of major Taiwanese test interface suppliers .

All four companies sell device-specific, design-to-order test interfaces: each new chip design requires a newly engineered card, board, or socket, and large volume pull in usually happens before chip production ramp-up (repeated orders are placed after mass production whenever necessary). In this framework, MPI dominates US ASIC vendors with in-house probe cards, with CPO equipment opportunities emerging. WinWay's socket business mainly ties to major US GPU suppliers and some ASIC vendors, and it has obvious progress in MEMS probe cards as well. CHPT concentrates on high-end custom boards with in-house manufacturing depth, proactively developing more turn-key opportunities. Keystone wraps its board portfolio in an on-site service model.

By scale and market cap, MPI is the largest of the four (Fig. 66 ), and relatively diversified (it derives 20-30% of sales from equipment), followed by WinWay, CHPT and Keystone. Their overlapped business is the probe card business, and we think the major differences are: MPI has a broad customer base with relatively small MEMS penetration now (we see the migration is gradually happening), and it has 100% in-house probes and substrate fabrication. WinWay's probe card business is anchored on nVidia, and it purchases MEMS probes from Technoporbe. CHPT's revenue from probe cards and load boards accounts for 60%+ of total revenue, and its relationships with key fabless are determinants of its future project wins. KSMT operates a fabless business model (it does not have fabs for probe cards and boards). It has a higher revenue proportion from load boards than probe cards, and is well-known for its R&D resources integration capabilities.

Fig. 66: Comparison of major Taiwanese test interface suppliers

Source: Company data, Bloomberg Finance L.P., Nomura research

Chroma vs. Hon - little overlap in business scope

A frequently asked question by investors is whether and where Chroma competes with another Taiwan-based backend testing equipment maker Hon. Precision (7769 TT, Buy). Admittedly, both the companies have ATC/handler offerings for FT and SLT, but we believe they have fairly little business overlap given Chroma's focus on SLT handlers (we estimate 60-70% of Chroma's semiconductor testing revenue comes from SLT) vs Hon's focus on FT handlers (70-80% of handler revenue comes from FT).

Hon has been making inroads into the SLT handler market by leveraging its competency in customization and ATC, and we believe AMD is one of its longstanding customers in SLT handlers, although we think Chroma could have secured SLT handlers for AMD's latest MI400-series. We are aware that Hon has started engineering collaboration with nVidia in SLT handlers for the future generation of AI GPUs, but we are uncertain about whether Hon could really challenge Chroma's dominance in this segment. In our view, Hon's new SLT handler opportunities could lie squarely within ASIC customers whose broader adoptions of SLT, apart from mandatory FT, have significantly increased.

Key test consumables and equipment within the testing process

How does test hardware work together in the testing process?

A typical testing process including chip probing (CP) during wafer stage (before dicing, before packaging or after wafer-level packaging) and final testing (after dicing), see our Dec 2024 KYEC initiation report, as well as the Testing process changes along with chip complexity section of this report for more details on testing flows.

A tester (also called Automatic Test Equipment [ATE]), usually from Advantest or Teradyne, is used in both the CP and FT stages, while it needs to work with prober/handler respectively, as well as different test interfaces:

IC test trios: ATE, prober/handler, and test interface

Semiconductor testing is not carried out by one single tool but by a tightly integrated system also known as a 'test cell'. The test cell consists of three major parts: automated test equipment (ATE), prober/handler, and application-specific test interfaces. In SLT, the ATE is replaced with a system test board on which test sockets are equipped, housed inside an SLT handler.

• Automated test equipment (ATE): ATE, or simply 'tester', is the sophisticated core workstation of the test cell that feeds precise electrical stimulus signals (e.g., voltages, currents, or high-frequency waveforms) into the device under test (DUT) and monitors the output responses. The tester compares the chip's real-time performance running on pre-programmed inputs against engineering design specifications to identify defectives. In the ATE architecture, the mainframe houses the tester's power supply, central cooling unit and the system controllers, and the test head houses the test interfaces. ·
• Prober/handler: The prober or the handler is the mechanical automation arm of the test cell that operates with the ATE to ensure a continuous, high-speed, and unmanned silicon test flows. The test head is flipped and pneumatically or hydraulically docked into the core mechanical nest of the prober/handler. The prober and the handler are used in different testing scenarios the prober is present in CP and handles uncut wafers, using microscopic pins to physically contact with individual die before they are singulated, while the handler picks up chip packages (in FT or SLT) from trays, inserts them into the test sockets, and physically sorts them into different bins based on the tester's verdict. ·
• Test interface: The test interface is the physical and electrical 'bridge', customized based on the silicon layout/package, to connect the generic tester to the DUT. A probe card paired with pogo pins (or MEMS pins for fine-pitch applications) is being used in CP, while a load board with test sockets is adopted in FT. ·

The IC test squad is not complete without 'role players'

Beside the aforementioned trios, we note there are also tools supplementing temperature management to prevent undesired shifts in chip performance and physical properties under different thermal conditions, and specialized plug-in modules to expand or reconfigure the tester's scope.

• Thermal chuck: During CP, the chuck is the flat, rigid metallic platform that holds the silicon wafer in place using vacuum suction. A thermal chuck is a chuck with built-in heating elements and internal cooling channels to uniformly control the temperature of the wafer under test when mimicking different thermal conditions in operations. A thermal chuck must demonstrate extreme planarity (i.e., very meager warpage) at extreme temperature swings to avoid poor electrical contacts or wafer crack by probe needles. ·
• Active thermal control system (ATC): ATC is a dynamic temperature management system integrated into the handler. When a tester boots up workloads, the DUT could undergo a spike in internal power density and instantaneously heat up. ATC detects the thermal conditions of the chip under test and instantly adjusts its cooling/heating action to counteract the chip's internal power fluctuations. ·
• Instruments: The tester is essentially a modular chassis populated by a cluster of instruments that define its initial testing scope. However, if a silicon requires test ·

Main board (PCB)

LSI tester

Fixing implement coverage beyond this built-in set, specialized instruments can be added to the tester to extend its capabilities. These modular instruments are notably critical for highperformance domains such as analog/mixed-signal and high-speed digital, and instruments are introduced in CPO test insertions to assist with photonic test items. Performance board

Signal path and space transformation in ATE systems

Wafer prober

The signal path within the ATE flows sequentially from the tester to the device under test (DUT). Initially, the ATE's internal instrument cards generate and measure the necessary testing signals. These signals are transmitted through thousands of double-ended spring pins (pogo pins) housed within the pogo block on the test head interface. Internally, the upward-facing ends of these pins make direct physical contact with the ATE's precision instrument cards or internal cable routing boards. Subsequently, the signals are routed and fanned out by a highly customized printed circuit board . Depending on the test phase, this is either a probe card PCB mounted on a wafer prober for Wafer Sort (CP), or a load board docked with an IC handler for Final Test (FT). For advanced CP applications, a space transformer (such as MLO or MLC) is further utilized to drastically reduce the routing pitch before reaching the final contact elements, which consist of micro-probe needles for CP or socket pins for FT. The primary objective of every structural layer is space transformation: shrinking the tester's coarse, millimeter-scale pin grid down to the microscopic die pad pitch (~40-100 µm) or package ball pitch (above 100 µm), while rigorously preserving signal integrity and power delivery efficiency.

Mechanical actuation and system communication

On the mechanical front, the heavy test head is maneuvered by a manipulator and precisely docked onto the automation equipment - either the prober or the handler -applying controlled compression to the pogo pins against the interface board. The physical contact mechanisms differ fundamentally in their directional approach depending on the automation platform. During CP, the prober employs a bottom-up approach, stepping the wafer chuck upward to make contact with the stationary probe needles, touchdown by touchdown. Conversely, during FT, the handler utilizes a top-down approach, picking up the packaged components with a robotic arm and plunging them downward into the test socket.

Throughout this physical operation, the tester and the automation equipment (prober or handler) maintain continuous synchronization. The automation equipment first signals that the "part is in place," triggering the tester to execute the test program. Upon completion, the tester transmits the "binning result" back to the equipment, prompting the prober to update the electronic wafer map (or physically ink the die), or directing the handler to mechanically sort the packaged part into the appropriate output tray.

Fig. 67: Testing interface and equipment overview for CP/FT

Handier

Test head

Probe card

Wafer

Stage

Packages

Test socket

System Level Tester

Fig. 68: Comparison of testing processes

Tri-Temp handler

1 site in parallel

$$$$ / site

~<2 min TT

electronics

Burn-in

Non-automated oven, thermal,

electronics

Source: Advantest, Nomura research

Probe cards are key components for chip probing

Chip probing: finding the bad dies before they get expensive

Chip probing (CP) is the first electrical test in a chip's production flow - performed before dicing and packaging to screen out defective dies before packaging costs are incurred. To do this, the probe card must make physical contact with the wafer, maintaining stable, uniform contact across tens of thousands of pads and micro-bumps, often under demanding temperature conditions. Testing typically runs in multiple passes (for example, separate hot and room-temperature insertions) and proceeds from basic to deep: first confirming each die's fundamental electrical integrity - opens, shorts, and leakage then verifying the internal circuitry using the chip's built-in test structures, which allow far more thorough fault coverage than external testing alone. For analog and memory circuits, CP goes beyond measurement to active correction: on-chip settings are trimmed and calibrated into spec, and failing memory cells are mapped and repaired through builtin redundant circuits. Advanced packaging has raised the stakes considerably as a single defective GPU or HBM die entering a CoWoS assembly scraps a module worth thousands of dollars (see Testing process changes along with chip complexity ) - so the flow increasingly adds wafer-level stress and burn-in (WLBI), applying elevated voltage and temperature to surface early-life failures before packaging; this practice is most established for HBM and power devices. The end result is a wafer map classifying every die as passing, scrap, or repaired - elevating CP's mission from basic defect screening to guaranteeing that only Known Good Die (KGD) proceed to assembly.

A probe card consists of probe head, interposers, and probe card PCB (PIB)

During the chip probing process, a probe card is used for electrical connection and verification. The probes on the probe head contact with the terminals (pad or bump) on the die of semi wafer/device under test (DUT), sending the signal to the tester to assess its electricity and functionality. A probe card consists of a probe head (with pins), an interposer (also called substrate), and a probe card PCB underneath (Fig. 69 - Fig. 71 ).

Probe head: A probe head is composed of contact probes (needles) and ceramic plates (guide plates). The probe head is the most valuable part in the probe card, it can account for 40-50%+ of the content value of the probe card. Usually, the higher the pin count, the higher the value of the probe head (assuming they use the same kinds of pins). For highpin-count products (30-40k or above), the content value of the probe head can exceed half of the total probe card value. Some probe card vendors will outsource pins (procure pins externally), only providing probe head assembly services (see Fig. 72 ). Different probes suit different ICs and vary by application.

Interposers/Interconnection: Interposer is typically an ABF substrate. Common interposers include MLO (Multi-Layer Organic) or MLC (Multi-Layer Ceramic). The layer tends to serve as a space transformer to bridge probe head and probe card PCB, as its device pitch is much smaller than ATE pin pitch. One major job of a space transformer is to convert/redistribute the coarse pitch of testers to the fine pitch that the device requires.

Probe card PCB: Probe card PCB is at the bottom of the probe card structure, directly contacting the test head of the ATE. Typical layer count for a probe card PCB ranges from 40-70, whereas some engineering/R&D or very small volume projects may exceed 100

Mechanics

PCB

Fig. 69: Probe card structure

Ceramic plates

Probe Head

Tester Side

Stiffener

_ Contact probes

Source: Technoprobe, Nomura research

Backer

PIB

MLO/MLC

Probe unit

Test Head

Probe head unit layers. See more details in Hidden heroes in testing process: test interface boards .

Probe technology on Ceramic

Wafer

Plates of the Probe Heads

Printed Circuit Board (PCB)

Partially outsourced

Vertical Probe Card

Assembly of the ceramid

Ceramic Plates

Plates on which

Probes are then

Board uniti

Probe Head with the probes

Weiding and connection of the Muti Layer produced in the

Organic (MLO) to the Panted Circul board (ru

Fig. 70: Probe card structure with pins

Substrate Unit

Cobra

MEMS

Multi Layer Organic (MLO)

on the market, used in the production process

Source: WinWay, Nomura research

Source: WinWay, Nomura research

Fig. 72: Probe card manufacturing process

Source: Technoprobe, Nomura research

Different kinds of probe cards; MEMS probe cards are gaining more traction

Probe cards are highly customized products, and usually need to be designed before an IC enters mass production. Usually, a probe card vendor will produce an engineering sample 3-4 months after an IC tapes out, but the chip vendor needs to the contact probe card vendor 1-2 quarters before an IC tapes out (Fig. 14 ). Different ICs fit different types of probe cards, and three major probe cards categories are cantilever probe cards (CPC), vertical probe cards (VPC), and MEMS probe cards. There are still other probe card categories such as membrane probe cards (MPC) for some high-end DDICs or high-frequency RF applications.

CPC and VPC are names of probe card structure, as they actually describe how probes contact the wafers. On the other hand, MEMS is a manufacturing technology for probes. The probes used for a device tend to be highly associated with devices' end applications. Required speed, frequency, device complexity, device density, pin count, and costs all have to be taken into consideration when choosing probes/designing probe cards.

Cantilever probe card (CPC): CPC is suitable for large solder pad/bump size devices. CPC is now mostly used for legacy chips such as logic chips, DDIC, analog ICs, and power ICs. A common type of CPC is an epoxy probe card.

Vertical probe card (VPC): Probes are vertically aligned, and perpendicular to the substrate. VPC is suitable for high-frequency, high-density chips such as SoCs/processors. Some AI chips are still using VPC currently.

MEMS probe card: MEMS is a technology to produce probes, so there could be vertical

Source: ZENFOCUS, Nomura research

Fig. 71: Probe card structure

Source: Technoprobe, Nomura research

Certificate unit

Final quality testing o the mechanical and

electrical features of assembled probe card

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MEMS probe cards and non-vertical MEMS probe cards, but current common MEMS probe cards adopted in mass production volume for high-end chips are usually vertical MEMS probe cards, as non-vertical MEMS probe cards cannot meet high pin count and I/O requirements physically for advanced ICs. Therefore, we are only referring to vertical MEMS probe cards when we mention MEMS probe cards in this report. MEMS probe cards are for even finer pitch than classical VPC due to its probe features. As discussed above, MEMS probe cards now account for ~70% of the total probe card market ( Fig. 50 ).

Comparison between different probe cards

• 1) Costs: CPC probe cards are usually cheaper than VPC and MEMS probe cards, and are thus relatively economical.
• 2) Probe mark: As the probes directly contact the devices, it will leave marks on the wafers (i.e. probe marks). CPC probe marks are usually larger/deeper than VPC, and significant probe marks increase the possibility of ruining the wafers.
• 3) Replacement: CPC probes replacement is more difficult than for VPC, and thus incur higher maintenance costs. MEMS probes are sometimes integrated with the space transformer, electroformed or bonded directly on the substrate, making them difficult to be changed. This kind of MEMS probe card doesn't need guide plates.

Fig. 73: Cantilever probe card

Probes cantilever out from the substrate horizontally

Source: Venture Electronics, Nomura research

Fig. 75: Cantilever probe card

Source: Seiken, Nomura research

Fig. 74: Vertical probe card

Probes are vertically aligned

Source: Venture Electronics, Nomura research

Fig. 76: Vertical probe card

Source: Seiken, Nomura research

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Vertical MEMS probe card

Fig. 77: How different probe cards work

ATE inteface

ATE interface is the area where pogo blocks on ATE test head contacts PIB

High-voltage

standoff

Source: Elena Venuti, Probe Card Technologies in Advanced Semiconductor Testing for Wide Band Gap Devices, Nomura research

Device pitch shrinkage drives unavoidable usage of MEMS probes

Many forces are driving the shift toward MEMS probe cards: array scale and uniformity (tens of thousands of probes per touchdown with tightly matched spring characteristics, such as in full-wafer memory contact), engineered contact mechanics (precisely controlled force and scrub on delicate low-k pads, and tailored current-carrying geometry for high-power devices), and, at the leading edge processes, pitches below 50 µm where conventionally manufactured probe cards simply cannot deliver the required positional accuracy. Fine pitch virtually mandates MEMS; MEMS, however, is routinely chosen at ordinary pitches for scale and consistency alone.

Device pad pitch is the single strongest driver of probe card architecture, because it simultaneously dictates pin technology, pin count, and mechanical complexity. At coarse geometries (peripheral pads at 60-100 µm pitch typically), simple cantilever needles suffice. Once designs shift to area arrays, like flip-chip C4 bumps at 100-150 µm pitch, angled needles physically cannot reach interior contacts. This forces a transition to vertical cobra pins guided by drilled plates; pin counts jump to 10-50k for large logic dies, and the total contact force reaches tens of kilograms, requiring massive stiffeners. Below 50 µm (e.g., HBM micro-bumps at 40-55 µm), only mask-defined MEMS probes can hold the strict few-micron tip-placement budget. Here, parallelism pushes pin counts to the extreme. See Fig. 78: Typical pitch regimes and corresponding test interface solutions .

Cantilever needle: formed from a bent metal wire, it operates as a flexing beam. When driven against a pad, it creates a "scrubbing" action to break through native oxides. Because of its size and manual alignment requirements, it is strictly limited to peripheral pad layouts and larger pitches (60-100 µm typically). Its primary advantages are low cost and easy repairability, making it the standard choice for analog, power, and legacy devices.

Cobra / vertical buckling-beam pin: Utilizing a short, straight metal wire, the entire pin buckles elastically sideways under pressure. This buckling mechanism delivers highly uniform contact force across non-planar wafer surfaces while producing only a minimal wipe that won't damage solder bumps. Flooring at an 80-150 µm area-array pitch, it is now the industry workhorse for flip-chip CPU, GPU, and SoC testing.

MEMS probe: MEMS probes are microstructures built using semiconductor photolithography and micro-electromechanical techniques. This mask-defined process ensures sub-micron consistency across hundreds of thousands of pins. It produces nearzero scrub (protecting fragile low-k dielectrics) and is the only architecture capable of reaching sub-40-50 µm area-array pitches. Despite its high cost, it is the only viable

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Fixing Plate solution for HBM, micro-bumps, and advanced process nodes (Fig. 25 ). Classical VPC probes could not satisfy costs-performance, contact force, and/or probe density requirements, and the probes are not thin and short enough physically for high frequency signal transmission. MEMS probes with extreme fine pitch, better planarity, and extremely shallow probe marks are suitable for high-pin-count, high frequency, high precision devices such as highly advanced processors/AI chips. WLCSP Chip

Note that probe card pin count does not necessarily equal device pin count; how many dies are tested at one time (single-DUT or multi-DUT) will impact total probe card pin count. The equation holds true under single-DUT test (multi-DUT probe card will have more pin count vs. device pin count to test multiple dies at the same time). CPC pin count is usually 1k-2k (although some players can do 7-8k), VPC pin count could be several thousands or ~10k+, and MEMS probe cards pin count could exceed tens of thousands.

Currently, advanced SP AP bump pitch is around 80 µm, and HPC/AI chips pitch is around 100um, thus vertical probe cards are still widely adopted, though the trend is toward MEMS. Based on our industry survey, nVidia is adopting MEMS (sharp tip to contact pad) for AI GPUs/CPUs and networking products, staying at cobra pins (flat tip to contact bump) for gaming GPUs, and ASICs are gradually migrating to MEMS, depending on fabless vendor. Pin count for AI ASICs is also growing, from 20-25k VPC pin sto 30-40k MEMS pins, all the way toward 90-100k+ pins.

Hybrid probe cards adopt mixed-pin technology to incorporate different types of pins on the same probe card to balance cost and performance, such as only adopt MEMS for fine pitch signals and use cobra for surrounded power signal, or adopt cobra for high current signals.

Fig. 78: Typical pitch regimes and corresponding test interface solutions

Pitch ranges are indicative; boundaries between adjacent technologies are transition zones where solutions overlap

Note: This is a conceptual illustration, not specific to any company or project. Source: Nomura research

Fig. 79: Different kinds of pins

Source: ProbeLeader, Nomura research pills

800

pogo pin

Pressure

Fig. 80: Elastic buckling of cobra pins

Source: MEMSFLEX, Nomura research

Elastic

Change

Elastic

Recovery pitch (um)

Fig. 81: Key probes technologies

Source: Nomura research

An overview of the IC test process and required hardware

The IC test process consists of package test, burn-in, and SLT

FT is a mandatory procedure , and depending on IC customers' configurations, there could be two or more FT steps during the manufacturing cycle (e.g., nVidia's AI GPUs require two FT steps, one before BIT and the other after BIT). FT is carried out after IC assembly (on substrates, lead frames, or wire bond), and chip packages are capable of accommodating larger input voltages or electric current than bare dies. FT measures electrical properties of chips given pre-programmed inputs to identify product functionality ('pass or fail' is the terminology) and sort functional products by grade (also known as 'binning'), all within the shortest possible time frame (usually hundreds or thousands of seconds) , as chip vendors may want to control test charges (measured by 'hourly rates') which are amortized expenses of costly testers.

We note below three primary parameters form a sequential filtering system in FT for logic circuits, the focus of which is on whether outputs are 'correct'. By contrast, analog/mixedsignal IC testing places more emphasis on the 'measurement accuracy' of select parameters (e.g., linearity and signal-to-noise ratio).

• Direct current (DC) test: The DC test is the first phase in FT and consumes the least time among the three phases. It measures the steady-state electrical characteristics of the chip using direct current and ensures the physical silicon structure is intact. The DC test does not validate logic or speed, however. The primary metrics measured during this phase include: 1) Open/Short test , which verifies that all pins are properly connected to the internal circuitry (no 'open') and that no pins are accidentally welded together (no 'short'); 2) Leakage current , which ensures a pin does not 'bleed' excessive current into the substrate when it is given a specific voltage level; 3) Power consumption , which detects the electric current drain inefficiency; and 4) Output voltage level which confirms the chip can drive signals out at the correct voltage thresholds required to communicate with other components. 1.
• Function test: The subsequent function test is to check whether the logic operation works properly. During the function test, the tester floods the chip with preprogrammed binary inputs (i.e., test vectors) and records the outputs generated by the chip to compare the results against the expected mathematical truth table. Function tests are typically executed at a nominal, conservative clock speeds to isolate pure logical errors from high-speed timing anomalies. 2.
• Alternating current (AC) test: The AC test introduces the critical dimension of 'time', evaluating how the chip performs under dynamic, high-frequency AC conditions and checking the output signals' 'waveform', because a chip might have perfect structure and flawless logic responses at slow speeds. AC test pushes the silicon to its physical limits by measuring sub-nanosecond timing parameters to ensure signals propagate cleanly across the die without corruption. Major test items include propagation delay, setup and hold times, rise and fall times, and maximum frequency. The AC test is also the foundation of 'binning' , sorting out the best-performing chips and lower-tiered ones. 3.

On the other hand, burn-in test (BI) and SLT are optional procedures, but gradually gaining more traction

Burn-in is a reliability screen step, in which chips are operated at extreme temperature (typically 100+ ℃ ) and above-nominal voltage for hours (if not longer). The stress accelerates aging of the chips, forcing latent manufacturing defects to fail during the process (rather than after shipment to customers). BI test is usually mandatory for automotive, aerospace, medical applications, but it is also increasingly important for AI/HPC chips given extremely high content value per package. A high-end GPU requires several hours of BI, compared with FT measuring in seconds, and BI ovens are required in this stage, along with BI boards and BI sockets.

Compared to FT and SLT, where testing processes verify that a chip works correctly currently, infant mortality means working now and failing later. It's impossible for a test coverage to detect a defect that has not yet happened, thus the only remedy is to force it to happen early through stress. Memory and advanced packaging are driving demand for BI test, given that: 1) an HBM stack contains a dozen-plus dies and tens of thousands of bonding interfaces, and one early failure scraps an entire CoWoS module, so screening is shifting earlier to wafer-level burn-in (WLBI) with intensity rising rather than falling; and

•

End CPU TDP

Typical High-

End GPU TDP

8000-

2) datacenter accelerators run in clusters of tens of thousands, where a single early failure interrupts an entire training job, pushing operators' tolerance toward zero. These applications have a high cost of failure combined with time-dependent onset, failure types that BI can address. The increased adoption of BI reflects the rising share of highreliability applications in the semiconductor market.

HPC Chip Power Trends

In design

During SLT, the chip is inserted into a system test board designated by the chip vendor to simulate how it works in a real-world scenario. The test board is a modified version of the actual commercial motherboard that eventually houses the silicon and is equipped with other components such as memory and peripherals. The SLT boots a full operating system such as Linux or Android and runs heavy, asynchronous software workloads to replicate genuine user environments. Throughout the process, SLT measures functional and behavioral metrics rather than raw structural data, including system stability, workload execution throughput, thermal throttling thresholds, and high-speed interface bit error rates (BER). Year Failure modes shifting

SLT has gained traction industry-wide because it exposes defect classes that the preceding stages structurally cannot. DC test, Function test, and AC test are largely deterministic and exercise the device in isolation, at fixed patterns and controlled conditions. They are effective at catching hard, static failures but are poorly suited to intermittent, workload-dependent or interaction-level defects - issues only manifest when multiple IP blocks operate concurrently under realistic power, thermal, and timing stress, or under specific software-induced corner cases. As chip complexity has grown with heterogeneous integration, multi-core coherency, and higher-speed interfaces, these system-level 'test escapes' could result in a larger share of field returns, which has steered SLT from a niche practice in automotive/mobile applications toward broader adoption across compute, AI accelerator, and networking chips, where the cost of a return merchandise authorization (RMA) far outweighs the cost of additional test screening.

The SLT phase is less expensive than FT given no usage of multi-million-dollar testers, but it is very time-consuming and could take minutes or even hours to execute per device. At high volumes, the throughput mismatch could become the binding constraint on SLT adoption, since running every unit through hours of system-level workloads is economically impractical for most product lines. As such, the industry leans toward parallel testing inside automated SLT handlers, and potentially the integration of adaptive testing backed by machine learning algorithms that selectively route only silicons at risk to extended SLT screening while the bulk of the chips proceed through a shortened or standard flow. This 'smart SLT' approach preserves most of the defect-screening benefit while containing the test time and cost overhead, and is emerging as a key differentiator among OSATs and IDMs competing on both quality (defined by defective parts per million, or DPPM) and test cost per unit.

Fig. 82: Chip TDP surge increases importance of burn-in

Average

2028

2030

Key Trend

2026

SLT Tester Site

Test

High Speed Interface

(USB, Ethernet, PCle)

Test Protocols

Test Time / Test Cost

Fig. 83: SLT acknowledges that software is part of the system, and recreates the end-use environment as closely as possible DRAM A

Test Site API

Program

Voltage Source

600-2000W package

Liquid cooled in field

Chiplet mesh fabric

Hyperscaler critical

PMIC

Chip Set

Source: Teradyne, Nomura research

Fig. 84: Decision matrix of testing process

Source: ASEH, Nomura research

Fig. 85: Optimizing cost and quality when deciding testing process

Source: TER, Nomura research

DUT

Consolidated Decision Matrix

WLBI

Test

Processor

Mock 1/0

ATE

X

PLBI

possible

SLT

Serial Scan,

Mission-mode

Functio

MBIST,

Dynamic Test Coverage

A Limited realism possible

Total Cost Target Line (ATÉ+SLT)

possible

SLT

Best option

Quality

Fault coverage

SLBI/SLT

Optional

Testing

Interposer Size

2026 TSMC, Ltd.

Cowos-s

CoWos-L/R

CoWos-s

1.5-reticie

4 HBM2

N16 SoC

'16

Adaptive

CoWos® Enables Al Compute Scaling

Functional Testing

(ATE)

CoWoS® Enables Al Compute Scaling

• World's largest 5.5-reticle size CoWo in production with >98% yield in 2026

• Continue scaling with larger interposer size for growing Al compute demand,

Product

Ship with 14-reticle (20xHBM) ready by 2028 and >14-reticle (24xHBM) by 2029

Fig. 86: Adaptive SLT could further reduce the overall cost (time) of test

A16 SoC/SoiC

212 HBM4E|

Source: AEM, Nomura research

Handlers are more than mechanical arms

While IC test handlers alone might initially seem like simple mechanical automation which is often oversimplified as mere robotic arms picking and placing devices under test, the reality under the hood is a sophisticated combination of high-precision micro-mechanics and solid knowledge in thermal physics.

We highlight that FT handlers could eventually undergo mechanical redesign and OSATs have to upgrade the tools if chip packages expand to a certain bar. Thus far, AI/HPC is the primary driver of package footprints. With logic dies already approaching a physical limit closer to the reticle size, nVidia and other AI accelerator makers understand incremental performance gains must come at the sub-system level rather than the chip level, and consequently are targeting to stack more logic dies and more HBM cubes onto interposers to construct a more powerful computing chip system. nVidia has moved from Ampere/Hopper (both 2x reticle-size interposer), to Blackwell in 2024 which houses two reticle-size compute complexes and eight HBM cubes on a 3.3x reticle-size interposer, and soon to Rubin in 2026E which houses two reticle-size compute complexes, two I/O dies, and eight HBM cubes on a 5x reticle-size interposer.

We believe the horizontal expansion of AI chip footprint is unlikely to halt as TSMC continues to unfold its CoWoS roadmap to introduce larger interposers (and therefore larger IC substrates underneath). According to TSMC, it is bringing 5.5x reticle size CoWoS into production in 2026 with a >98% yield. Previously TSMC suggested its 9.5x CoWoS-L with SoIC and 12 HBM stacks would enter production in 2027E (Fig. 87 ; Tech Symposium 2025 ), and during the symposium this year, the company extends the roadmap to 14x reticle size CoWoS (20 HBM stacks) production by 2028 and aims for >14x reticle size CoWoS (24 HBM stacks) in production by 2029 (Fig. 88 ).

Fig. 87: TSMC's CoWoS roadmap laid out in 2025 Technology Symposium

Source: TSMC, Nomura research

Fig. 88: TSMC updates its CoWoS roadmap

Source: TSMC, Nomura research

Healthy

2025

5.5-reticle

12xHBM3E/4

2026

9.5-reticle

12xHBM4E

2027

14-reticle

20xHBM5

2028

>14-reticle

2029

258x537.6mm and the right one measures to 380x387.6mm

L. SIDE

VIEW

We note 'the bar' is correlated to 'how many chip packages that a matrix tray can accommodate' during the FT stage. A matrix tray is a plastic carrier that holds IC packages in a rigid grid of rows and columns, and the robotic arm of a handler will move the vacuum suction nozzle over the input matrix tray, suctions up untested chips (DUT), and places DUT into the test socket. The dimension of the tray generally conforms to the standard proposed by the Joint Electron Device Engineering Council Solid State Technology Association (JEDEC in short). The current standard tray is specified at 135.9x322.6mm , but if a chip package measures 120x125mm, one standard tray can carry only two pieces of DUT. The JEDEC acknowledges the industry trend of moving toward larger package footprints (notably in recent years, propelled by AI/HPC), and has added two new types of tray (also known as 'mega tray') in recent issues: 258x537.6mm and 380x387.6mm . CH

Based on our understanding, Hon has progressed the development of large-package handlers based on the new JEDEC standards given its substantial exposure to AI/HPC applications (~80% of tool orders in 1Q26). The current planning is to begin shipments of tools capable of handling >120x150mm packages in 2H26E, and a handler solution for 250x250mm package in 2H27E, to position itself early for the next round of handler upgrades. Hon also targets to add more automation functionalities for better integration with unmanned factories (e.g. overhead hoist transfer [OHT] and autonomous mobile robot [AMR]) to boost throughputs. Our 'napkin math' indicates that a 120x150mm package could house an interposer sizing up to 10-11x reticle, which ties with TSMC's CoWoS roadmap in 2027-28, whereas our supply chain checks have not yet picked up such a large AI chip in the pipeline.

Fig. 89: IC matrix tray

Source: Sunrise, Nomura research

Fig. 90: JEDEC adds two new types of tray to address larger package size

The left one is the current standard tray (135.9x322.6mm), and the one in the middle measures to 258x537.6mm and the right one measures to 380x387.6mm

Source: JEDEC, Nomura research

Intel's EMIB might open a new window for large AI chip test demand. We believe some AI ASIC customers might have started evaluating Intel's EMIB-T (embedded multi-die interconnect bridge with TSV) as a logic+HBM integration alternative because of concerns about insufficient capacity support at TSMC. According to Intel, EMIB-T targets HBM4/4E and logic chiplet interconnectivity with the lowest possible cost, and the company's roadmap is to scale to the integration of >8x reticle size total top silicon area on a ~120x120mm substrate by 2026E and >12x reticle size top silicon area on a >120x180mm substrate by 2028E (Fig. 91 ). If successful, Intel's EMIB-T might open a new demand window for large AI chip testing.

We think Google's potential reliance on Intel's EMIB-T for the next-generation TPU v9 (partnering with MediaTek) could be a critical litmus test for Intel's advanced packaging capabilities. Based on our supply chain analysis, this signpost project will feature a substrate body size within 120x120mm (see the floorplan in our report ), not yet necessitating the transition to mega tray configuration.

B-1

A 3.0045 - 1

JIRLE

230.0.

24120.0

12-40 0)

FIGURE 4.10- 19 TYPICAL TRAY CX TOP AND LONG SIDE VIEWS

-4x

Reticle

Fig. 91: EMIB roadmap

8

12

-8x

-120x120

HBMs size

intelfoundry

EMIBs

Reticle size

Package size

12

HBMs

20

EMIBs

-12x

Reticle size

2028 +

-120*x180+

24

Package size

HBMs

38

EMIBS

40 x+

Reticle size

Future

-241x240

Package size

200+

EMIBS

Source: Intel, Nomura research

Another driver of upgrades comes from AI/HPC customers' migration to more powerful ATC (greater cooling capacity), since the sub-system performance gain from more dies in a package comes at the cost of more stringent thermal requirements.

Using nVidia AI GPUs as an example, the maximum TDP of Blackwell Ultra (B300) is 1,400W, which can be supported by Hon's ATC3.5 (cooling capacity of up to 2,000W) during the FT stage. However, we think the TDP of Rubin (R100) may start from 1,800W, leaving little margin for ATC3.5 and likely initiating an upgrade to ATC3.6 (up to 3,000W). Admittedly, comparing TDP to ATC maximum cooling capacity is sometimes more biased than 'power density' (also better known as 'heat flux' in thermal physics), because TDP only tells us 'how much heat is generated' and power density/heat flux provides us 'how concentrated the hotspot is' and 'how fast the heat transfer is'.

nVidia will be more aggressive in chip specs by stacking a reticle-sized GPU die on top of another for the Feynman platform, the first-ever GPU-on-GPU SoIC stacking (report ), which would lead to higher computational power even with limited growth in interposer reticle stitching size (c.6x reticle, see footprint in Fig. 93 ; up from c.5x in Rubin). Such a practice theoretically exacerbates thermal dissipation challenges, and we expect it could trigger a migration to more powerful ATC3.7 . According to Hon, it has ATC with a max imum cooling capacity of up to 7,000-8,000W ready, and is working on engineering en route to >10kW (Fig. 94 ).

The similar rationale applies to SLT handler as well. We believe SLT handler upgrades are primarily driven by the tight coupling between the handler's mechanical and thermal interface and the physical design of each new AI chip platform. Unlike FT, which tests a packaged die in a relatively standardized form factor, SLT validates the chip at the full system or module level , indicating socket pin count, board layout, power delivery, and thermal load are all specific to that generation's module configurations. Altogether will further compound the changes for more challenging hand-in-hand engineering efforts by SLT handler makers with end customers.

Dummy

HBM4

HBM4

HBM4

Dual-temp

HBM4

(25~150°C)

Power Density

HBM4

XCD

(N2)

HBM4

Tri-temp

(-80~180°C)

HBM4

Fig. 92: Floorplan of AMD MI455 and cross section

(N2)

Reconstituted interposer (5.5x ret.)|

B series

R series

Source: Company data, Nomura research

SiC thermal plate to function as an intergrated silicon carrier (fill up the

1/O

HBM4E

HBM4E

1/0

Fig. 93: The floor plan and cross-section chart of nVidia's Feynman GPU

SiC thermal plate to function as an intergrated silicon carrier (fill up the height gap in between GPU and HBM) and thermal interface material (TIM)

HBM4E

Structure

Source: Company data, Nomura estimates

Fig. 94: Hon's ATC roadmap to address greater TDP by AI/HPC chips

Source: Company data, Nomura research

Theoretically the tier-one ATE maker Advantest could have enjoyed a natural installed base advantage in test handlers sales since handlers are used along with tester, and Advantest has advanced technological capabilities in mechatronics to optimize the coordination of handlers and testers. This is particularly valid in memory testing, where the testing relies on extreme parallelism (i.e. high throughputs on fairly standardized interfaces). Advantest was able to build up a large handler market share in the past when it leveraged its memory tester installed base, before it gradually lost ground to emerging memory handler specialists like Techwing (089030 KS, Not rated).

Hon's ATC/handler business serves primarily logic semi (it only had 1-2% of tool orders from memory in 2025), where the inherent advantage of Advantest disappears entirely. Logic packages are of high varieties than commodity memory, featuring varying physical dimensions, ball counts/pitches, etc., and this requires deep, early-stage collaboration during the new product introduction (NPI) phase as well as close-knit communication with specialized test interfaces (load boards and sockets) to build bespoke mechanics inside handlers. Specialized handler makers such as Hon can thrive on engineering fluidity. By contrast, Advantest does not devote many resources to tailor handlers given that handlers are essentially 'sidekicks' (1-2% of total revenue) and IC testers are its core business lines. This may also explain why Teradyne does not have its own handler business units given a great exposure to logic testing.

Handler customization is especially important and necessary in the realm of AI/HPC and ASICs due to large die sizes, complex multi-die packaging (e.g. 2.5D/CoWoS) and ultra-

HBM4

Microbump

F series

Dummy

20

15

10

5

0

high pin counts, and Hon is an expert in these areas (72% of tool orders from AI/HPC and ASICs in 2025). Hon engages directly into the embryonic development phases of AI/HPC and ASICs through tight NPI collaborations with end customers backed by a robust IP portfolio of more than 600 patents filed globally across thermal control, high-throughput, and active optical inspection (AOI), and ships early configurations to end customers' R&D labs for engineering validation and joint developments. We summarize Hon's NPI status (data as of 2Q25) in Fig. 95 .

Furthermore, the handler is more than a sheer mechanical sorter in AI/HPC testing as the accompanying ATC becomes an active execution environment. Hon's dual-temp and tritemp ATC cover a broad spectrum of operating temperatures and cooling systems (liquidcooling, refrigerant-cooling, and air-cooling), and the company continues to move forward in capabilities with an extended roadmap to 7,000-8,000W readiness and >10kW in the engineering pipeline (Fig. 94 ). A clear visibility of ATC roadmap and well execution, in our view, puts Hon in a more favorable position for AI/HPC clients looking to initiate new chip development.

Fig. 95: Hon's NPI status by application and end-customer location

Note: Data as of 2Q25.

Source: Company data, Nomura research

Fig. 96: Comparison of major global tester and handler makers (ex-China)

Note: Market cap data as of July 17, 2026.

Source: Company data, Bloomberg Finance LP, Nomura research

Socket

Device Under Test (DUT)

The role and structure of testing sockets

Sockets are used in all three processes (FT, BIT, SLT), and a socket tends to combine electrical, mechanical, and thermal aspects into a single structure. The socket is an interface between the DUT and the test equipment, sitting between the DUT and the load board. A socket requires precise contact resistance and shielding effectiveness measurements to ensure reliability. The signal is transmitted from PCB (load board) to device and return to PCB. The DUT is aligned to the floating plate on the socket, and the floating plate aligns the springs to the center of the solder ball (BGA)/pads(LGA). A handler pushes the DUT into the socket.

Core components of a socket include:

Socket lid/clamshell/latch: usually necessary in burn-in sockets (when sockets are lidless, the handler's plunger will press the device down). The lid physically presses the IC package done into the contactors and ensures uniform force distribution across all pins.

Housing/socket body: the main structure of a socket, usually a precison-machined or molded insulating frame (using advanced engineering plastics). For coaxial test sockets, the housing is made of machined aluminum or brass. In some cases, ceramic or glassfilled composites are utilized.

Alignment plate/floating guide: to hold the DUT in place and keep the solder balls/pads aligned with the socket's contact pins.

Thermal features: Sockets sometimes incorporate a thermal control unit (TCU), directly pressing on DUT for heat dissipation.

Contact elements: the pins or elastomer that carry signals, a conductive pathway to bridge the chip to PCB.

Fig. 97: Typical socket construction

Source: PTSL, Nomura research

Different sockets are adopted in FT/SLT and BI processes

FT and SLT sockets are relatively similar, and thus market research institutions tend to combine the two types together when calculating market size, while leaving BI sockets as another category (see Socket market size relatively stable with shifting market share ).

Test sockets are used for relatively short-term testing cycles, and optimized for signal accuracy, high-frequency capacity, high insertion durability, and minimal contact resistance. On the other hand, given the longer testing time and tough testing environment, BI sockets need to bear extreme temperature and electrical stress physically and are equipped with thermal-management solutions. The BI process will test a substantial amount of chips at the same time (massive parallelism), thus BI sockets sacrifice speed/frequency and signal integrity, resulting in lower costs and a much simpler manufacturing process. SLT requires chips to run in a mimic environment as real use cases, thus the socket needs to run all required functions. As SLT testing time is also longer than for FT, parallel testing is also required to increase throughput, and thus more SLT opportunities benefits socket suppliers in terms of volume.

Source: DediProg, Nomura research

• Lid

• Socket

• Pogo Pin

• Load board (PCB)

After packaging

Fig. 99: Different types of sockets in different testing steps

Introduction

Products

SLT

Burn-in Test

Source: Smiths Interconnect, Nomura research

Two major contact elements - spring probes and elastomer

The contact elements in a socket predominately indicate pogo pins and elastomer (silicone rubber), while cantilever pin sockets are used mostly for legacy product/memory testing (relatively rare).

Spring probe (or pogo pins) are the most common type of probes used for AI chips currently, and common base materials for spring probes include brass, bronze, copper, plated nickel silver, and gold. All components are gold finished for excellent electrical conductivity, durability, and corrosion protection. Spring probes are spring-loaded electrical contacts, due to inclusion of a spring. A constant normal force on target surfaces can enable consistent electrical performance during testing. A typical pogo pin consists of plunger, barrel, and spring (Fig. 100 - Fig. 101 ). When force is applied, the spring compresses and the plunger moves inside the barrel. Pogo pins have a longer lifespan, and individual probe replacement is possible, while the physical signal path is longer. The shape of the tip on a pogo pin is application-specific: crown/cup/concave tips are standard for BGA solder balls or WLCSP packaging, flat or round tips match LGA or QFN packaging, and pointed tips fit coarse pads or via/through-holes (Fig. 102 ).

Elastomer is another contact element alternative. It replaces mechanical springs with a composite material - non-conductive silicone rubber matrix embedded with conductive particles (rubber is an insulator). When the IC is pressed down, the particles contact each other, and creating a conductive vertical path. Elastomer causes near-zero mechanical damage due to its even distribution of stress, and creates a short signal path, also improving signal integrity for high-frequency/RF/mmWave testing. However, its lifespan is shorter, and replacement would have to be more frequent and less flexible (whole layer).

WinWay's proprietary HyperSocket is a mix of pure spring probe and elastomer solutions (we provide more details in the company section of this report).

Some common related tip type.

-A concave

-J round

-D spherical round

-E Conical

-F Flat

-V 4 - point crown

-H 9 - point crown

-T Pyramid

As little as 3 components. But some probes have 30+

BGA

Fig. 100: Spring probe is also known as pogo pin

• The plunger is the moving part that makes contact with the DUT thru the. It is biased to ensure contact

DUT side

DUT Side

DUT

Plunger

BGA

BGA

BGAS CBGA

Fig. 101: Spring probe introduction

Spring

PCB side

Source: Uyemura USA, Nomura research

Fig. 103: Pogo vs elastomer type of socket

Source: Junyong Park, Modeling and measurement of high-bandwidth and high-density silicone rubber socket for 100Gbps transceiver IC test, Nomura research

Source: Junyong Park, Modeling and measurement of high-bandwidth and high-density silicone rubber socket for

Source: INGUN USA, Nomura research

Source: INGUN USA, Nomura research

Fig. 102: Different packaging methods suit different probe tips

Source: SFENG, Nomura research

Coaxial sockets are now mainstream for advanced logic chips

A coaxial socket is actually a structure, not a type of contact element. In this architecture, each signal contact is enclosed in a dielectric insulator, and then runs inside a grounded metal shield. The structure prevents crosstalk and noise, and matches the required impedance. Major AI accelerators/CPUs now predominantly use coaxial socket architectures, given the better signal integrity, high-speed compatibility, high-frequency, high power-consumption logic and RF/networking chips (Fig. 104 - Fig. 105 ). Coaxial sockets utilize nearly 100% pogo pins (coaxial elastomer sockets exist, but are very uncommon).

Non-coaxial solutions use standard pogo pins or unshielded pins, and common elastomer sockets are non-coaxial, as the physical path is already short.

DUT

BGA

wiew.com (Smiths Intercorne

P G

Air gap

Dielectric

• Top howsing

Metal housing

GND pin

Fig. 104: Coaxial socket structure

Power and

Ime frequency pin

Source: Modus Test, Nomura research

Hidden heroes in testing process: test interface boards

All contact elements require a mounting surface - which necessitates the use of a Test Interface Board (TIB)

The terminology around Test Interface Board (TIB) is a frequent source of confusion. Specifically defined (by Technoprobe, Fig. 106 ), a Device Interface Board (DIB) is the load board used in the final testing of the packaged parts, while a Probe Card Interface Board (PCIB) is used to identify the sub-assembly of the probe card PCB (plus a spacetransformer substrate, whenever needed) before the probe head is mounted (see Probe card accounts for 40%+ of the test connectivity market for more details on probe card structure.)

A Probe Interface Board (PIB) , by contrast, is not a mandatory element of the signal chain: it is an optional adapter board inserted between the ATE tester head and the probe card under certain tester configurations - for example, to remap pogo-tower resources or bridge platform incompatibilities - and is absent entirely when the probe card is natively designed for the tester. However, "PIB" is now often used loosely on the wafer-test side to refer to the probe card PCB now (i.e., PCIB).

Recall that the signal path in CP and FT should be:

• For wafer-level-testing: ATE test head (pogo tower) - PIB (not always present) Probe card (probe card PCB + interposer + probe head) - wafer ·
• For packaging testing: DIB - socket - contact elements - chip ·

While DIBs have a relatively smaller value compared with probe cards and sockets, they accounted for ~17% of the total test connectivity market in 2024-2025, at USD900mn-USD1bn (Fig. 48 - Fig. 49 ), growing from USD500mn+ in 2020, according to TechInsights. Yole further projects a 4.9% revenue CAGR (2025-30E) for test interface boards, the lowest growth rate among all test interface categories (Fig. 47 ).

www.COHU.com

DUT

• DaVinci Gen V Socket Structure

IC Device

IMe Material

Fig. 105: Example of high-performance coaxial socket

Cartridge Top

Spring probes

Source: Smiths Interconnect, Nomura research mm

Best

4.70

mm

(Test)

Source: Smiths Interconnect, Nomura research

• Illustration of Probes (0.8-1.0 Pitch)

Fig. 106: Test Interface Boards in testing process

Probe Cards & Tester Components

FINAL TESTING

Final Test Components

Source: Technoprobe, Nomura research

Probe card PCB, burn-in board (BIB), and DIB/load board are distinct components

Test Interface Boards (TIB)- including probe cards, load boards, and burn-in boards serve as the vital electrical bridges during qualification, and they differ radically from the conventional PCBs that host finished chips. The core reason is routing burden. A conventional product board routes one system's signals. A test board must route every tester channel - including thousands of signals, power, and ground connections for an AI accelerator- from a large tester footprint down to a die or socket footprint measuring just a few centimeters across, all impedance-controlled and length-matched. As a result, a chip's test board typically requires several times more layers than the final product in which that chip will be integrated.

Probe Card PCB: Operating at the wafer level, the PCB is the large round or square board onto which the probe head and stiffener are mounted; it fans out signals from the tester's pogo tower to the fine-pitch probe area. Since PCB fabrication alone cannot bridge from millimeter-scale board features to the fine pitches of devices, most advanced probe cards incorporate a space transformer - either a multi-layer ceramic (MLC) or multi-layer organic (MLO) substrate - positioned between the PCB and the probe head to complete the pitch translation.

Load Board / DIB: Also called a DUT board, it serves as the critical electrical interface between the ATE tester head and the handler/contactor socket holding the packaged IC. Used in the package-test flow at OSATs, the socket sits on top, while thousands of tester channels are routed underneath. For ICs with high-speed interfaces, load boards carry strict impedance and length-matching requirements so that signals are transferred with minimal distortion. Note that a DIB is delivered as an assembled, electrically verified unit populated with thousands of components rather than just a bare board.

Burn-in Board (BIB): The BIB serves as a robust mechanical and electrical fixture for reliability screening. Dozens of burn-in sockets are soldered onto a single large-format board - often spanning several hundred millimeters to maximize oven throughput which is then loaded into chambers and subjected to extreme high temperatures for hours or days to identify early-life failures. The critical requirement is not signal speed but rather the ability to withstand prolonged and repeated thermal stress.

Probe card PCBs and load boards use the same top-grade materials, but their challenges differ fundamentally. The probe card PCB's fine-pitch burden is absorbed

by the space transformer, so the board itself can use conventional through-hole, singlelamination construction. Its primary challenges are extreme layer count and flatness (tens of thousands of probes pressing down simultaneously, even surface deviations of a few tens of microns can cause contact failures, and the board must hold its shape on a heated chuck.) The load board has no such intermediary because socket contacts land directly on the board surface. Escape routing, GHz impedance control, heavy current delivery, and thousands of assembled components all compete for the same layer budget, often necessitating blind/buried vias and sequential lamination. Its acceptance criteria are electrical : impedance tolerance, signal loss, and channel calibration. The burn-in board carries slow signals, and modest layer counts; its challenge is neither electrical nor precision but rather heat endurance and cost - maintaining structures through days in ovens with temperatures of above 125°C, shipped in dozens to hundreds per program, and competing on durability and price.

Fig. 107: TIB comparison

Load board is the most complicated in terms of design

Source: Nomura research

Difference between common system-level PCB and TIB

The most fundamental difference between the two types of boards is decided at the design intent itself. A conventional PCB (system-level PCB or product board) is designed for production: its mission is to perform one fixed job reliably over the product's lifetime - soldered in, powered up, used for years - so the design goal is to minimize unit cost and maximize yield and throughput while meeting the product spec, with one design replicated hundreds of thousands to millions of times. A TIB is designed for test: it is not a product but a measurement instrument - its mission is to extend the tester's capability to the chip's pins without distortion, and to stay accurate through hundreds of thousands of insertions or hours to days of high-temperature baking. Its design goals are therefore prioritizing performance and precision first, rather than cost considerations, as one design is typically built only a handful of times (much less than mass production volume). Any excess loss, impedance deviation, or thermal warpage in the board itself would result in misjudgements (good chips being classified as bad, or passing bad chips).

Process-wide, TIB adopts subtractive lamination and mechanical drilling similar to traditional PCBs. However, for TIBs, the aspect-ratio requirement for drilling is much higher, and high-end TIBs usually require back-drilling. Material-wise, consumer electronic PCBs use standard FR4 given the lower cost, and high-end servers/switch boards use low-loss laminates (M6/7 series or above) for high-speed signals. Probe card PCBs and load boards adopt a hybrid structure combining low-loss and FR4 materials (uses premium materials only for high-speed layers). In contrast, for BIBs, speed does not matter, but as it has to withstand high temperatures, it usually adopts high Tg FR4 or polyimide (PI). Essentially, BIBs trade electrical performance for enhanced thermal features.

Layer count-wise, it is challenging for a TIB to shrink in size (to accommodate the tester's large footprint and provide mechanical strength), so it typically gains routing space by increasing thickness and layer count.

Common smartphone motherboards adopt 8-12 layers HDI, PC boards could be 6-10 layers, general server is 16-20 layers, while AI servers/switch could be further higher (2040+). A TIB must funnel thousands of tester channels down to the chip footprint, all impedance-controlled and length-matched; thus, a chip's test board typically contains several times more layers than the final product in which that chip will be integrated.

mechanical drilling / laser drilling

Source: Nomura research

Key players and dynamics in TIB market

Though TIB suppliers and volume board fabricators both belong to the PCB industry, their business models differ fundamentally. Volume fabs replicate one design millions of times, competing on yield and scale at 10-30% gross margins (depending on layer count and complexity); a TIB supplier runs a full cycle from design, fabrication, to assembly and calibration (while some players outsource manufacturing, operating a fabless-like business model). The vendor sells the engineering solution rather than the board itself, with gross margins commonly reaching 30-50%. Every device generation and package change requires a fresh board design, creating recurring procurement demand untethered from any single product's volumes.

Two major types of suppliers in the TIB market - captive and merchant

The captive camp - owned by ATE/probe giants: The test-equipment majors have pulled TIBs in-house in recent years: Advantest consolidated R&D Altanova (boards) and Essai (sockets) into its AIS segment, tied to its V93000 tester ecosystem and focused on flagship-processor load boards; Technoprobe (the probe card leader) acquired Harbor Electronics and Teradyne's former DIS board business, keeping probe card PCB flatness yield under its own control. The captive's niche is on co-design and customer lock-in: tester/probe head and board are developed as one, tuned for maximum performance, while keeping customers inside the parent's ecosystem. However, a customer running Teradyne testers may hesitate to buy boards from Advantest.

The merchant camp - independent specialists: Unaligned with any tester brand and open to any customer's silicon, merchant design takes a major share in the TIB design market, clustering along regional chip ecosystems. Notable vendors and projects include CHPT(supplying TIBs to top fabless and foundries), Keystone Microtech (6683 TT, Not rated; operating more like a fabless, mainly focusing on design services [outsourcing manufacturing], major customers are top fabless and foundries as well). The Korea memory chain is anchored by TSE and Daeduck (353200 KS, Not rated) in BIBs and memory test boards, tracking the HBM cycle; China's localization chain is led by Fastprint (002436 CH, Buy) across all board categories; in the other regions, Gorilla Circuits (unlisted) and Esa Electronics (unlisted) serve local customers in North America and SEA. The merchant camp has advantages such as neutrality and fast customization.

We also note that some conventional PCB players are seeking to join the TIB market; however, we think it should take around some time for them to enter, considering the technical challenges and fundamental differences in design goals. Even with the necessary technical capabilities in place, entering the supply chain ecosystem requires substantial additional effort, considering that each key fabless has established long-term partnerships with existing suppliers, and new entrants lack a track record, amid rapid generational transitions in chip technology.

IC substrate

Relative performance chart

EQUITY: OSAT

Price

(TWD)

7000-

6000-

5000-

40001

30001

20001

1000

• 300

• 250

• 200

-150

MPI Corporation 6223.TWO 6223 TT

EQUITY: OSAT

Churra. I CEC Namura

Accelerating growth; initiate with Buy

In-house MEMS needle driving value; serving nearly all AI chip customers with low concentration risks; CPO is next catalyst

Initiate coverage with Buy rating and TP of TWD8,000, implying 33% upside

We initiate coverage of MPI along with our Anchor Report, with a Buy rating. We expect MPI to be one of the key beneficiaries under the big umbrella of semiconductor testing that is getting more and more complicated, and test interfaces need to upgrade to deal with challenges such as fine-pitch, higher speed/frequency, and higher current, etc. We believe the complexity of advanced packaging methods will come in tandem with more difficult testing processes, from the perspective of additional test insertions beyond the current flow, or brand-new insertions that need to be figured out, such as CPO. Test interfaces need to upgraded as well, to avoid any defects in later stages (i.e., after sending to customers). MPI has a broad customer base spanning ASIC vendors, GPU vendors, foundries and OSATs (we estimate the top five customers only contribute 5-15% of revenue each), and we believe the company participates in most key AI chip projects. We also expect MPI has better negotiating power, and may enjoy some spillover effect from its overseas peers, amid a supply-constrained environment. We expect the probe card segment to continue to lead MPI's revenue growth over 2026-28F with a 91%+ revenue CAGR, along with CPO ramps. The improving profitability from increasing penetration of MEMS probe cards and wellcontrolled expenses will support a 95% EPS CAGR over 2026-28F, vs 55% in 2023-25, based on our estimates. We expect MPI's EPS to surge from TWD33 in 2025 to TWD227 in 2028F. Our TP of TWD8,000 is based on 45x average 2027-28F EPS. Major downside risks to our TP include: 1) weaker demand in the AI/HPC market or a slowdown in AI proliferation; 2) fierce competition in the test interface market and share loss; and 3) worse-than-expected CPO progress.

Accelerating probe card capacity target to meet demand; CPO is next catalyst

MPI has accelerated its capacity expansion since 2025, evidenced by a series of land and facilities acquisitions throughout 2025-26, and rising capex. We expect the aggressive capacity build-up will continue in 2027F as well (Fig. 112 ), considering its packed project pipeline. Among these, we believe MEMS probe card expansion will record the strongest growth and fuel MPI's business going forward. We expect MPI to grow its VPC/MEMS probe card needle capacity to 10mn units per month by the end of 2027F (above guidance of 89mn), from 5.5mn by the end of 2026F, to meet strong customer demand (Fig. 112 ). For CPO, MPI is working on Insertion 2 and 3 probers. We estimate sales contribution to start from 2H27F with single-digit contribution in 2028F for the time being.

Source: Company data, Nomura estimates jul

Global Markets Research 24 July 2026

Relative performance chart

Source: LSEG, Nomura

Research Analysts

Semiconductor

Aaron Jeng, CFA - NITB aaron.jeng@nomura.com +886(2) 21769962

Vivian Yang - NITB vivian.yang@nomura.com

+886(2) 21769970

Eric Chen, CFA - NITB

eric.chen@nomura.com +886(2) 21769965

Key data on MPI Corporation

Performance

Income statement (TWDmn)

Source: Company data, Nomura estimates

Cashflow statement (TWDmn)

Source: Company data, Nomura estimates

Company profile

Established in 1995 in Hsinchu, MPI started its business with cantilever probe cards, and subsequently expanded into vertical probe cards (VPC), MEMS probe cards, LED/photonics test and sorting equipment, engineering probers and thermal systems.

Valuation Methodology

Our TP of TWD8,000 is based on 45x 2027-28F average EPS. 45x is at its high end of historical range. The benchmark is TAIEX.

Risks that may impede the achievement of the target price

Major downside risks to our TP include: 1) weaker demand in the AI/HPC market or slowdown of AI proliferation, 2) fierce competition in the test interface market and share loss, and 3) worse-than-expected progress of CPO.

ESG

MPI runs an ESG Committee chaired by the president, which sets short- to long-term sustainability targets and reports to the board at least annually. Environmental priorities cover GHG, water, waste, and hazardous substance management under group-wide carbon reduction plans, disclosed in a sustainability report published since 2023.

Insertion 2

Insertion 3

At the center of CPO testing flow

A key candidate of high-value-added CPO insertions

Silicon Photonics (Siph) / Co-Packaged Optics (CPO) is one of the rising trends in semiconductor manufacturing. We have detailed our understanding of testing flows in CPO testing in our Anchor Report and in Fig. 109 . Our understanding of CPO testing insertion is as follows: Insertion 1 is PIC and EIC single-sided wafer-level test; Insertion 2 is doublesided wafer-level test after hybrid bonding; Insertion 3 may include two optical engine (OE)level testing steps after singulation - before and after packaging (attach FAUs [fiber array units]/receptacle/ structural reinforcements), and Insertion 4 is the module-level test after the optical engine is mounted on the substrate. Silicon

Insertion 4

Silicon

Substrate

While final testing flows and vendor selection could vary by different customers, we expect MPI to leverage its expertise and experience in the PA/LED (Photonics Automation) and AST (Advanced Semiconductor Test) segments, leading to more opportunities to address Insertion 2 - where EPIC wafer is tested (double-sided), and part of Insertion 3 - focusing on die-level-testing, before packaging, given its competency in wafer probing. We believe MPI has commenced small volume Insertion 3 equipment shipments in 2H26, as industry players are still determining the testing flow and will have to carry out many trials before volume production. Insertion 2 is the most critical and complicated part in the process, in our view, and we believe many suppliers are now actively developing suitable equipment for the stage, and MPI also participates.

Our view on the CPO timeline now largely aligns with nVidia's (NVDA US, Not rated) product roadmap - for scale-out switch to ramp in 2H26F along with the Rubin platform (see 2026 GTC note ). However, given that there are many technical challenges for the brand-new architecture, we expect any large volume to come in 2027F and beyond, and the TAM will likely expand further after CPO penetrates into scale-up (likely in Feynman). However, many fabless companies beyond nVidia, such as Marvell (MRVL US, Not rated)/Broadcom (AVGO US, Not rated), as well as foundries such as GlobalFoundries (GFS US, Not rated) and Tower Semi (TSEM US, Not rated), are also developing their own CPO roadmap - not necessarily aligning with TSMC's (2330 TT, Buy) COUPE platform creating substantial future opportunities for supply chain vendors once CPO proliferates.

Fig. 109: CPO insertion flow

Note: This is a conceptual illustration, not specific to any company or project.

Source: Nomura research

Fig. 110: CPO insertion flow and potential suppliers

Source: Nomura research

ASIC

Unabated probe card demand across the board

Probe card to record 91% revenue CAGR over 2026-28F; MEMS's penetration continues to increase

MPI is one of the leading probe card vendors globally - it ranked No.4 in the total ownmake IC probe card market in 2025, according to Yole, mainly providing cantilever probe cards for display driver ICs (DDIC) and vertical probe cards for high-end logic products. We have described the technology trend of a probe card and requirements to migrate to MEMS-type (Micro-Electro-Mechanical Systems) probe cards in our Anchor Report, and fine pitch is one key factor for adoption of MEMS. While there is no precise boundary, conventionally manufactured probes cannot deliver the required positional accuracy after a certain level of pitch (we believe 50-70 µm; see Fig. 113: Typical pitch regimes and corresponding test interface solutions ). Currently, advanced smartphone application processor has a bump pitch of around 80 µm, and HPC/AI chips' pitch is around 100 µm, and hence, vertical probe cards are still widely adopted, though the trend is moving toward MEMS.

MPI is proactively expanding its MEMS capacity to catch up with testing requirements for AI chips, and to compete with overseas suppliers. Considering that MEMS pin's content value could be higher than cobra pins, we expect more projects migrating to MEMS probe card to fuel MPI's probe card segment. MPI is also building its own PCB fab and expects to enter the production stage in 2027E to shorten production lead times (mitigate supply chain bottlenecks), while the company will continue with its dual-source strategy of both in-house manufacturing and external procurement. We expect the probe card segment to show the strongest revenue growth over 2026-28F (91% CAGR), and MEMS penetration to rise continuously.

Probe card value content to surge along with higher testing requirements

Every dimension of advanced silicon is simultaneously raising the bar for probe cards and leading to higher content value

Larger die and package sizes expand the probe array's physical footprint, demanding tighter planarity control across a wider area, since the tolerance for total height deviation does not scale with size. Higher pin counts push arrays into the tens of thousands of probes, multiplying both the precision-manufacturing content and the routing burden on the PCB and space transformer beneath. We believe AI ASIC's pin count would rise from 20-25k to 30-40k+, after migration from cobra to MEMS. Higher current-carrying capacity (CCC) requirements (driven by kilowatt-class power delivery) force redesigned probe geometries with larger cross-sections and thermally robust materials, working directly against the simultaneous demand for fine pitch, where probes must shrink to serve sub-100 µm interfaces. High-speed signals (112G/224G SerDes) impose strict impedance and inductance budgets on contact design, while low contact force becomes mandatory as probes touch fragile low-k pads and micro-bumps that cannot tolerate conventional scrub. Furthermore, the wide temperature operation requires the entire card assembly to hold alignment and planarity across thermal expansion cycles. We believe all these stringent requirements are driving more sophisticated and expensive probe cards.

Advanced packaging's multiplier effect on probe cards

The chiplet architecture actually creates more probe card demand, as separated dies/tiles are integrated on one interposer, meaning that a single end-product no longer maps to a single probe card. The final module integrates multiple components from different wafers and process nodes (e.g., GPU/compute dies, I/O dies, HBM stacks, and a silicon interposer), and each demands its own dedicated probe card for wafer test. A highpin-count, high-current MEMS vertical card for the logic die; memory-class cards with repair flows for HBM; and specialized open/short test solutions for the interposer's fine micro-bumps and TSVs. Beyond the per-die dimension, the test flow adds cards by stage: separate hot and room-temperature insertions may require different thermalcompensation designs, and wafer-level burn-in (WLBI) uses full-wafer contactors built on an entirely different design philosophy from CP cards. Finally, the intermediate test at the CoW stage probes the reconstituted wafer after die attach, whose pad layout differs completely from native wafers and therefore mandates another freshly designed card. In total, a single CoWoS module can be supported by 3-5+ distinct probe card designs, spread across different suppliers and ecosystems. Every additional die in the package,

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Fig. 112: MPI - Probe capacity expansion trend We estimate aggressive expansion plans for MEMS in 2026-28F

WLCSP

Note: Year-end capacity; kpm

Source: Company data, Nomura estimates

Source: Company data, Nomura estimates

Fig. 113: Typical pitch regimes and corresponding test interface solutions

Pitch ranges are indicative; boundaries between adjacent technologies are transition zones where solutions overlap

Note: This is a conceptual illustration, not specific to any company or project. Source: Nomura research

Overflowing pipeline of new projects

Dominant share in US ASIC vendors; packed pipeline of new projects

MPI is major supplier to key US ASIC providers as it specializes in high-speed and highfrequency probe cards, which are most suitable for networking products. Along with the AI boom, we believe these ASIC vendors take critical share of top-4 hyperscalers' ASICs projects, and thus MPI is one of the key beneficiaries under the trend. As probe card shipments usually commence before chip volume ramping (Fig. 114 ), we could already see MPI generating revenue from key ASICs projects starting from end 2025 to early 2026, preparing for those projects expected to ramp in 2H26.

Dynamics between ASICs and test interface suppliers

The decision-making process for test interface procurement is being redrawn in the AI era. In the traditional model, the chip designer largely dictated the choice of test interface vendor: the fabless company or IDM owned the test program and qualified the suppliers, and the rest of the chain followed. The AI chip era has fractured that simplicity. An AI accelerator now passes through the fabless/design service partner defining the test strategy, hyperscalers/end customers whose reliability requirements reach backward into the supply chain, and other supply chain partners may also provide opinions. The result is that no single party fully controls test interface selection. Yet, complexity also provides entry points, since a supplier locked out at the fabless level may still win the project through end customer or manufacturing partners. In addition, chiplet architecture creates demand for multiple probe card designs for a single project, and they could potentially be allocated to different probe card vendors, depending on each probe card's requirements. We believe the trend opens the door to suppliers with technology expertise such as MPI.

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Full range of products for the applications sufficient coverage solutions to IC markets

Not a bystander in key GPU leader's supply chain

production shipment

Along with MPI's in-house manufacturing capability and scale, as well as broad coverage of probes (Fig. 115 ), we believe the company stands in a favorable position to participate in different vendors' projects. Also, given the unprecedented CPU demand from Agentic AI, we believe MPI is enjoying some spillover orders from overseas leading probe card vendors. discussion R&D sample shipment Multimedia

Fig. 114: Timeline of testing equipment and interface preparation

Test hardware is shipped before a chip's mass production

COF / COG

Wire-Bond

Soldering Bumps

Cu-Pillar Bumps

COWOs

MPICORPORATION

Note: This is a conceptual illustration, not specific to any company or project. Source: Nomura research

Fig. 115: MPI provides a broad range of probes

Different types of probes suit different applications and device pitch

Source: Company data, Nomura research

MPU

FPGA

EVS/FCB

Pitch 80um or more

High CCC

+12m chip mass production

repeating orders

Steady growth from other business

Other than probe cards (which accounted for 70+% of total revenue in 1Q26), MPI still has revenue streams from its equipment business, spanning Photonics Automation (LED/PA; ~5% of total revenue), Advanced Semi Test (AST; 10-15% of total revenue), Thermal Test (TS; ~5% of total revenue). Since 2026, MPI has combines its PA (LED) and AST segments, partially because CPO actually utilizes both segments' technology. Among all the equipment segments, we believe PA/AST will show obvious growth once CPO ramps.

Photonics Automation (LED/PA; ~5% of total revenue): mainly serves wafer probing stages, for LEDs and optoelectronic devices, including testers, material handlers, and inspection systems, serving applications such as LEDs, photodetectors, and lasers. The latest technologies such as VCSEL (Vertical-Cavity Surface-Emitting Laser) and Micro LED are now major revenue contributors within the segment.

Advanced Semi Test (AST; 10-15% of total revenue): this segment is more like an extension of the probe card business, in which MPI supplies some testing equipment (probing systems) to IC design houses/foundries for the purpose of detecting failures of sample wafers inside their fabs (not in OSATs). Its silicon photonics test solutions feature flexible-configuration high-precision fiber alignment (single fibers or fiber arrays with one or two positioners), safety mechanisms including fiber-to-wafer distance monitoring and collision avoidance, a broad test temperature range from -50°C to 200°C, and a compact system design integrating silicon photonics control instruments, paired with SENTIO software. The company has also signed an MoU with Lightium AG (unlisted) and Axiomatic_AI (unlisted) to jointly develop an AI-driven Intelligent, Autonomous, and Integrated Test Solution (IAITS) for PIC devices (press release ).

Thermal Test (TS; ~5% of total revenue): MPI supplies thermal systems for chips (after packaging) that will be used in extreme temperature environments, such as autos, satellites, fiber optics, sensing and telecommunication-related (5G/RF) applications. MPI's thermal system can cover temperate range from -100°C to 300°C, and we may also see some growth for the segment due to the rising TDP (thermal design power) of AI/HPC chips, with MPI having a competitive advantage in power saving.

The rest of business: MPI acquired Celadon Systems in 2021. Celadon is a global leader in engineering probe cards for parametric test, wafer-level reliability (WLR), characterization, cryogenic, and high-power applications, known for ultra-highperformance cards that thrive in extreme temperatures. MPI stated the acquisition would strengthen its leading position in test and enable more comprehensive products and services in which Celadon's cards are integrated into MPI's automated probe systems (synergy with AST segment), making high-density, multi-site, high-temperature WLR testing easy and versatile. Besides, MPI has low-single-digit revenue contribution from its overseas subsidiaries for distribution services and after-sales support.

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MPI's share price was relatively stable before 2023 (TWD79 at the beginning of 2020, and TWD113 at end-2022, benefiting from remote working [WFH] demand during COVID but undergoing an inventory correction afterwards). Since then, due to the AI boom (from end-2022), MPI's share price has risen on the AI trend (TWD118 at the beginning of 2023, reaching the TWD6,000-7,000 level in 2Q26), up 60x since 2023 vs TAIEX up 200%+. 1,000,000 600,000 Macro: 1,200,000 800,000 600,000

Along with the company's capacity expansion plans and major clients' project ramp-ups (both graphics and ASICs), MPI's revenue scale also expanded from the TWD500-600mn level in 2023 to TWD1,200-1,400mn in 2025, and exceeded the TWD1,800mn level in May-Jun 2026 (on a monthly basis). Fundamental strength (as shown in monthly revenue) remains one key factor behind its share price uptrend. Despite some correction from time to time, either due to (likely) phased profit taking or macro headwinds, the stock has remained on an upward trajectory over the past few years. 200,000 400,000 200,000

Further, from late 2025 to early 2026, there was increasing market discussion about optical communications/CPO, triggering a share price uptrend, as we believe MPI is participating in the CPO testing process (see At the center of CPO testing flow ). The successful launch of Gemini 3 in Nov-25 jointly ignited the large rally, in our view. Since 2Q26, there has been increasing visibility on MPI's probe card business, and we see continuous upward revisions to capacity expansion plans and capex. We also expect the company to have better pricing power, and some share gain opportunities amid a supply-constrained environment, all leading to share price momentum.

Fig. 116: MPI share price events vs monthly sales, 2023-24

Source: TEJ, company data, Nomura research

Fig. 117: MPI's share price event chart vs monthly sales, 2025-26YTD

Source: TEJ, company data, Nomura research

Discussions on server CPU

share gain; price hike

3Q24|

Analyst meeting

1024 ÷ 20 result with

Analyst meeting

GM beat

Financial analysis and forecasts

76% revenue CAGR over 2026-28F; probe card business to lead growth

We believe MPI has a broad customer base covering ASIC vendors/GPU vendors, for both AI and non-AI applications, and that its in-house manufacturing capability (especially, MEMS probes) will support the company's growth along with stringent requirements for probe cards and the necessity of using MEMS probes. We model a 76% total revenue CAGR over 2026-28F, vs 28% in 2023-25 (Fig. 119 ). Within the segments, we expect the probe card segment to lead the revenue momentum alongside CPO equipment.

Gross margin solid; increasing MEMS penetration to fuel profitability

We detailed the difficulty for probe card design in the above section to cope with advanced chip spec such as larger package size, fine-pitch, and to satisfy higher speed and frequency requirements. Along with complex design, we believe pricing will reflect the company's value. Besides, we also expect the migration to MEMS will result in ASP and margin upside. We expect MPI's GM to improve from 55%+ in 2025 to 61% in 2028F, and coupled with well-controlled expenses, we model EPS to surge from TWD33 in 2025 to TWD227 in 2028F (Fig. 122 ).

Fig. 118: MPI - key financial figures

Source: Company data, Nomura estimates

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Fig. 121: MPI - annual operating profit trend

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Fig. 123: MPI's annual product mix

Source: Company data, Nomura estimates

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Source: Company data, Nomura estimates

Fig. 122: MPI - annual EPS trend

Source: Company data, Nomura estimates

Fig. 124: MPI's annual product mix

Source: Company data, Nomura estimates

Fig. 125: MPI P&L

Source: Company data, Nomura estimates

Fig. 126: Nomura forecasts vs Bloomberg consensus estimates for 2026-28

Source: Company data, Bloomberg Finance L.P., Nomura estimates

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Valuation methodology and risks

Our TP of TWD8,000 is based on 45x 2027-28F average EPS. 45x is at a high end of its historical range (Fig. 127 ). MPI's historical trading range was15-30x in 2H23 to 1H25, before surging to as high as 80x in May 2026. Considering 76%/95% revenue/EPS CAGRs over 2026-28F (vs 28%/55% over 2023-25), we think a multiple slightly geared to the upper end is justified, given its in-house MEMS probe fabrication capability, less concentration risks due to a broad customer base, and key role in CPO testing, not to mention a P/E peak of 80x+ owing to the hype surrounding AI.

Risks to our call

• 2025E EPS

2026E EPS

Major downside risks to MPI include: 1) weaker demand in the AI/HPC market or a slowdown of AI proliferation; 2) fierce competition in the test interface market and share loss; and 3) worse-than-expected CPO progress.

Fig. 127: MPI's consensus 1BF P/E

Source: Bloomberg Finance L.P., Nomura research

Source: Bloomberg Finance L.P., Nomura research

Fig. 129: MPI's share price vs Bloomberg consensus EPS estimate revisions

Source: Bloomberg Finance L.P., Nomura research

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Established in 1995 in Hsinchu, MPI started its business with cantilever probe cards, and subsequently expanded into vertical probe cards (VPC), MEMS probe cards, LED/photonics test and sorting equipment, engineering probers and thermal systems through some M&A activities. MPI was officially listed on the TPEx in 2003, the first probe card company listed in Taiwan. Currently, its major business operations comprise Probe Card, Photonics Automation (PA)/Advanced Semi Test (AST), and Thermal Test divisions.

MPI designs and manufactures probe cards in-house, and can cover broad-based products including logic IC, RF, power/analog IC, CIS, and compound semiconductor/LED devices; its VPC and MEMS probe cards address AI/HPC wafer sort demand. For capacity allocation, manufacturing is mainly based in Hsinchu (MPI further announced that it would purchase land in Hukou in Apr-26), with ongoing capacity expansion for advanced probe cards. By product, probe cards accounted for 71% of the company's 1Q26 revenue, equipment was at 27%, and others at ~2%.

Fig. 130: MPI board of directors

Note: *Representative of MPI Investment Co., Ltd. Data as of Apr 2026. Source: Company data, TEJ, Nomura research

Fig. 131: MPI's share price vs FINI holdings

Source: TEJ, Nomura research

Fig. 132: MPI's top 10 shareholders

Note: Data as of 30 Apr-26

Source: Company data, Nomura research

Relative performance chart

EQUITY: OSAT

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WinWay Technology 6515.TW 6515 TT

EQUITY: OSAT

Churra. I CEC Namura

Attractive valuation; initiate coverage at Buy

Ties with key AI chips to drive growth in probe card and socket businesses; improving risk-reward

Initiate coverage with a Buy rating and a TP of TWD8,315, implying 28% upside

We initiate coverage of WinWay with a Buy rating along with our Anchor Report. Our positive outlook for the company is premised on: 1) strong revenue growth prospects for its probe card segment, driven by AI, high-end graphics and networking products; 2) several upcoming new projects in the socket business, with WinWay enjoying a dominant share within leading GPU vendors, alongside share gains in the system-level-test (SLT) business; the upcoming TPU project likely to augment growth as well; 3) more testing insertions such as burn-in (BI) and SLT being added to the latest AI/HPC chips, and new testing processes such as functional burn-in being under consideration; 4) higher product value content led by requriements to address high pin count, larger package size, higher speed/frequency, and heat density, etc (Fig. 133 ); 5) WinWay's innovative solutions such as HyperSocket potentially taking off in 2028F (Fig. 137 ); and 6) WinWay engaging in high-profile CPO testing insertions, with opportunities for Insertion 3 and Insertion 4 (Fig. 141 Fig. 145 ), in our view. We expect revenues from the probe card and coaxial socket segments (already accounted for a combined 70% of total revenue in 1Q26) to record 67% and 86% CAGRs over 2026-28F, respectively. In terms of new business, we assume HyperSocket would account for ~5% of total revenue in 2028F (Fig. 137 ). Many of the developments discussed here are still at a nascent stage, but their directions are clear, i.e. most are anchored to structural forces and are difficult to reverse, in our view. Our TP of TWD8,315 is based on 32x 2027-28F average EPS. The 32x target multiple is in the middle of its historical trading range. Key risks include: 1) weaker demand in the AI/HPC market or a slowdown of AI proliferation, 2) fierce competition in the test interface market and share loss, and 3) worse-than-expected profitability.

Near-term share price weakness could provide attractive entry opportunity

WinWay's share price has corrected by 27% since July (vs. TAIEX down 5%), as rising macro risks and overall sentiment on AI has taken a slight turn amid concerns about New York's moratorium on data center development and Meta's (META US, Not rated) initiatives around Meta Compute . Its share price also reacted to company-specific issues, in our view, after the release of June earnings. We estimate 2QFY26F GM at 39.7%, considering the preliminary June results. While more clarity will emerge after its 2Q26 earnings release, an increase in revenue contribution from MEMS probe cards, as well as unfavorable product mix (more consumer electronics) are potential drivers for the likely narrowed 2Q26F GM. We expect the impact to be temporary, and GM to gradually trend up in 2H26F. We see short-term share price weakness as buying opportunities.

Source: Company data, Nomura estimates jul

Global Markets Research 24 July 2026

Relative performance chart

Source: LSEG, Nomura

Research Analysts

Semiconductor

Vivian Yang - NITB vivian.yang@nomura.com +886(2) 21769970

Aaron Jeng, CFA - NITB

aaron.jeng@nomura.com +886(2) 21769962

Eric Chen, CFA - NITB

eric.chen@nomura.com +886(2) 21769965

Key data on WinWay Technology

Performance

Income statement (TWDmn)

Source: Company data, Nomura estimates

Cashflow statement (TWDmn)

Source: Company data, Nomura estimates

Company profile

Established in 2001 in Kaohsiung, WinWay started its business with test fixtures for optoelectronic products, and subsequently expanded into highend test sockets for logic ICs, later adding probe cards and thermal control solutions.

Valuation Methodology

Our TP of TWD8,315 is based on 32x average 2027-28F EPS, which is the mid end of its historical range. The benchmark index is TAIEX.

Risks that may impede the achievement of the target price

Major downside risks to WinWay include 1) weaker demand in AI/HPC market or slowdown of AI proliferation, 2) fierce competition in test interface market and share loss, and 3) worse-than-expected profitability

ESG

WinWay's ESG efforts center on operational resource efficiency - in 2023 it cut water usage by 28.9% and sourced 15% of electricity from green energy, alongside ISO 14001/45001 certifications. As a TWSE-listed company it publishes an annual sustainability report, though it has no public RE100 or net-zero commitment, reflecting earlier-stage ESG maturity versus larger peers.

Probe cards to lead next wave of sales growth

Probe cards to contribute 25-30%+ of sales in 2026-28F; MEMS a notable new driver

WinWay's probe card business is highly correlated to nVidia's (NVDA US, Not rated) gaming graphics. Before the AI boom, its probe card revenue largely followed nVidia's two-year graphics launch cadence (the segment showed signifiant revenue growth in 2018/2020/2022).

The company's probe card business grew nearly four-fold in 2025 vs. 2024, primarily driven by high-end graphics and initial volumes of new GPU platform/networking products. Mass production volume (for test interface) of the new GPU platforms (including CPUs) has started since early-2026. Networking products will also sustain their revenue momentum along with new platform ramp-up, in our view. Notably, starting from Vera CPU, nVidia has adopted MEMS technology (vs. Grace CPU that uses cobra pins). We believe WinWay participates in these key projects. As noted in our Asia AI Semi and Server report , we see unprecedented CPU demand driven by agentic AI, and in the same report we specifically acknowledge nVidia CEO and founder Jensen Huang's comment: 'We have visibility to nearly USD20 billion in total CPU revenue this year'. The comment and the demand direction are particularly positive for WinWay, in our view. WinWay's probe card market position has risen significantly - its ranking in non-memory probe card improved from No.19 in 2021 to No.5 in 2025, according to Yole (see our Anchor Report for more illustrations of the probe card market).

ASICs are also gradually migrating to MEMS probes, depending on fabless vendors. We estimate that about 90% of WinWay's probe card business in 2025 came from cobra probe cards (driven by high-end graphics), while the portion of MEMS probe cards will likely reverse and account for 80%+ of the company's probe card business in 2026F, a significant increase, by our estimate. Despite MEMS probe card GM remaining lower than that of cobra probe card, due to its much higher ASP, we expect MEMS probe card revenue to grow significantly into 2026-28F. We also expect new high-end graphic projects to record volume ramp-up in 2027F, together contributing to the probe card segment growth. We estimate probe card segment revenue to grow by 81%/75%/60% in 2026/27F/28F, accounting for 25-30% of total sales.

To cooperate with TPI for MEMS pins to address the demand for most advanced AI chips

WinWay's MEMS probe card shipments commenced in 2024, and its MEMS pins were procured from Technoprobe (TPI; TPRO IM, Not rated). In Phase I of the cooperation, the relatively small scale and the outsourcing business model impacted WinWay's GM for a short period (42-43% in 3Q25-1Q26 vs. 49% in 1H25). In Phase 2, announced in Dec2025 , TPI will grant WinWay the right to use its technology for a five-year period. The cooperation is aimed at addressing demand from most high-end probe cards, as advanced packaging technologies will continue driving the adoption of MEMS probe cards. We believe the business terms of phase 2 are likely to be realtively friendly for WinWay in terms of profitability, despite being still less favorable than non-MEMS probe cards. In our view, the cooperation with TPI provides WinWay opportunities to enter the high-end MEMS probe card segment without substantial upfront investments, and WinWay could assist more onsite services that are complementary to overseas vendors such as TPI, as well as superior customer relationships and broad customer base, given that the agreement is not exclusive to a specific customer.

Test socket business growth trajectory remains intact; further penetrating into key customer's SLT supply chain

Sockets remain WinWay's major business with 60-70% revenue contribution in 2025-28F, and the strong growth trajectory remains intact, supported by: 1) higher test socket content along with packaging complexity; 2) existing customers' market share gains as well as the rollout of new projects; 3) WinWay's share gains in key customers or key projects; and 4) opportunities in BI/SLT segments.

Advanced packaging to drive socket content value

The transition to complex advanced packaging dramatically escalates both the engineering rigor and the commercial value of test sockets, with socket content per device scaling almost directly with package complexity. The exponential rise in pin counts translates one-to-one into more contact elements per socket, while shrinking contact pitch demands ultra-fine, metallurgically advanced probe pins that endure thousands of compression cycles while maintaining microscopic alignment. Expanding package sizes compounds the challenge: large organic substrates are highly susceptible to thermal warpage, so sockets must integrate sophisticated mechanical architectures to guarantee uniform coplanarity across the full array without cracking the silicon, in our view. Besides, power densities above 1,000W for AI accelerators force the integration of active thermal control (ATC), from air-cooled lids to full liquid-cooling solutions. Simultaneously, extreme signal speeds (112G/224G SerDes) and mmWave frequencies push socket design toward electrical limits: pins must be engineered with ultra-short signal paths (coaxial or elastomer structures) and low-dielectric housing materials to contain insertion loss, impedance mismatch, and crosstalk. Overcoming these intersecting mechanical, thermal, and electrical hurdles transforms the test socket from a simple mechanical fixture into a highly customized, high-margin precision instrument.

Depending on specs, we believe the common high performance socket ASP could reach 2-5x that of legacy specs, and because each new project requires device-specific customization on ever-shorter product cycles, this content upgrade trend is continuing, structurally elevating the strategic value of top-tier test interface suppliers across each silicon generation.

Application mix optimization ongoing; HPC/AI exceeded 60% of mix since 4Q25

Consumer electronics contributed about 50-60% of WinWay's total sales before 2023, and the ratio dropped to ~30% in 2025, with the gradual take-off of AI/HPC (28% of total revenue in 2022, and rose to 48% in 2025). We believe MediaTek (2454 TT, Buy), Apple (AAPL US, Not rated) and HiSilicon (unlisted) were notable customers for mobile (AP/modem), with HiSilicon once accounting for higher than 20% of total revenue in 2019 (dropped to none in 2021). However, due to the pandemic, and decoupling of the tech supply chain (along with export control/US sanctions), further fuelled by the booming of AI/HPC, WinWay's customer base has gradually shifted from consumer-electronic focused OEM/OSATs to AI/HPC relevant fabless. That said, WinWay still supplies sockets to key smartphone projects.

For flagship smartphones, socket pin count is around 2-3k. The pin count could be 6-7k for server applications, and further grows to around 10k or more pins for the most advanced AI chips. Therefore, the more AI/HPC application exposure (usually along with higher socket technical requirements thus higher content), the better for overall content value for WinWay. From a product mix perspective, WinWay's RF&plastic sockets are mainly for mobile applications (AP/modem/PA), and AI/HPC applications are largely using coaxial sockets currently. We detail different sockets and probe selection factors in our Anchor Report. The proportion of RF and plastic sockets in WinWay's total revenue declined from 41% in 2019 to 9% in 2025, while that of coaxial socket grew from 29% to 43%.

We believe that the two largest merchant GPU vendors are WinWay's major customers. Currently, based on our industry checks, WinWay supports most of nVidia's FT sockets, and has some market share in AMD's (AMD US, Not rated) sockets. We also expect WinWay to participate in some upcoming TPU projects, as well as Axion CPUs. As sockets will likely be ready at least in 1-2 quarters before chip mass production (Fig. 135 ), we expect socket volumes for these key projects to contribute from 1H26F. Note that other than AI GPUs/ASICs, server CPU is witnessing significant demand growth along

HESM

High Pin Count

High-Speed Testing with agentic AI boom and that bodes well for WinWay as well.

>224Gbps

Besides test sockets, WinWay has ~10% of revenue coming from contact elements. Usually, customers do not replace an entire socket, but would replace pins with issues. A socket's useful life depends on application, but high current is one important factor.

Penetrating into key customer's SLT socket supply chain; functional BI under discussions Warpage

Testing insertions beyond pure final-test (FT) is gaining more traction to avoid defects (the failure costs are higher than that for legacy chips due to the adoption of advanced nodes and packaging technologies, inclusion of expensive external silicon content such as HBM, and the finished products value are also much higher). Not only do suppliers want to detect problems earlier (thus the trend of 'shift-left' and tendency to spend more budgets on chip probing), additional testing process such as burn-in and SLT are increasingly common within final test.

Contact Resistance random fail

New business opportunities have emerged for WinWay; notably, we observe that the company has successfully penetrated into key GPU vendor's SLT sockets supply chain (vs. previously mainly served FT sockets), gaining share from oversea vendors, likely due to their performance issues. Given that SLT testing has features such as longer testing time, and thus strong parallelism (to test lots of chips simultaneously to increase units per hour [UPH]), SLT will drive substantial volume demand of test sockets, in our view.

Another nascent trend is functional burn-in. Recall that burn-in socket is actually a GM dragger for WinWay (its complexity and signal integrity requirement is lower than that for FT/SLT sockets, and thus a lower ASP), and WinWay's exposure to burn-in sockets has always stayed at or below 10% of total sales. However, also due to chip complexity (notably, heat issues and extreme usage environment such as AI/HPC), there are more problems to handle during burn-in test. The new term functional burn-in aims to test more functionality vs. conventional BI (mass production BI), spanning pressure, temperature, humidity, and reliability. The process is likely to conduct system-level-test and burn-in test at the same time, with the objective to lengthen chips' useful lives. Under the new term, socket ASP and GM would be much better than legacy burn-in sockets (stringent requirements for material proprieties and electrical performance). Adding test insertions requires cooperation and coordination between ATE/equipment vendors, OSATs, and test interface suppliers; most importantly, customers need additional efforts for innovative testing programs, thus rigorous technical assessment, and cost/benefits need to be closely evaluated. We believe the actual adoption rate of functional burn-in is another development to watch out for in the coming years, and once production rampsup, it may become another revenue driver for WinWay.

Fig. 133: Challenges of advanced package test solutions

Source: Company data, Nomura research

High Heat Density

>4000W

Socket thermal domain

• Thermal run away

IC>4000W

Socket Power Loss>500W

....

Socket housing thermal distribution

"hultlanyoo are mulcauve, bounuareo

Nelweell aujavell leutmolgleo are tanomuon curleo whlere oorutorlo ovellay

Teot Haluwale ale ohlppeu velule ullp mlass pluuucllul

Cantilever (peripheral pad)

Fig. 134: Typical pitch regimes and corresponding test interface solutions

shipment

Pitch ranges are indicative; boundaries between adjacent technologies are transition zones where solutions overlap

+

-12m

Test interface

Note: This is a conceptual illustration, not specific to any company or project. Source: Nomura research

Fig. 135: Timeline of testing equipment and interface preparation

Test hardware are shipped before chip mass production

Note: This is a conceptual illustration, not specific to any company or project. Source: Nomura research

+

+

10,000

9,000

8,000

7,000

6,000

5,000

4,000

3,000

2,000

1,000

ve coumate tmay leaul Jo ul tular levellue 1l 40401

6%

HyperSocket to bear fruit beyond 2027F

HyperSocket combines pogo pins and elastomer together to address larger and more complicated chip packages

HyperSocket is WinWay's next-generation test socket platform designed for ultra-large package, high-frequency and high-speed applications, targeting AI and HPC devices built on 2.5D/3D advanced packaging. The patented structure was developed to meet sensitive contact-resistance test requirements: it provides a soft contact interface that avoids damage to solder balls, and maximizes production efficiency. 2026F

Conventional elastomer sockets are constrained by film thickness, which limit vertical stroke/compliance (a growing problem as ultra-large AI packages suffer from warpage). Spring probe (pogo pin) sockets offer good compliance but limited contact quality (as a standard crown tip provides only 4-9 contact points per pin, which do not touch the solder ball simultaneously and potentially cap the achievable contact resistance and currentcarrying capability [CCC].) HyperSocket resolves this trade-off by using spring probes to provide stroke/compliance and an elastomer layer to provide surfacearea contact against the solder ball, delivering both low, stable contact resistance and tolerance for large-package warpage ; the platform also extends to dual-layer (upper/lower, e.g. HyperSocket-Dual Film) and liquid-cooled configurations.

Capacity constraint to cap revenue upside

WinWay sees strong demand from customers for HyperSocket to be adopted in mass production volume, and it gave large order projections as early as 2025. However, the current bottleneck mainly falls in elastomer capacity, as this has not been WinWay's focus in the past. Costs will likely be another consideration for customers, as the HyperSocket solution carries a higher initial investment than conventional sockets (HyperSocket ASP is 30% higher), and the elastomer layer also becomes a consumable, requiring periodic replacement.

However, we believe HyperSocket design would be more widely adopted when the package size exceeds 100100mm/120120mm, especially when pin count exceeds 10k20k, while current mainstream GPUs/ASICs substrate size has not yet exceeded the threshold (Fig. 136 ); thus pogo pins are still dominant solutions. We observe some nextgen chips roadmap is approaching the limit (such as upcoming AMD MI455 or TPUv9 series beyond 2027F). Larger package size is an unavoidable trend, and we expect HyperSocket penetration to gradually increase. Note that during 1H26 earnings call, WinWay management set 5% as the high-end segment revenue target for HyperSocket in 2027E. We believe a suitable timeframe to expect a meaningful revenue contribution (say 5% of total revenue) from HyperSocket could be in 2028-29F (considering less than 1% of total revenue contribution in 2025F, still in low-single digit in 2026F, and less than 5% in 2027F, on our estimates, Fig. 137 ).

Fig. 136: Key GPUs substrate size is growing We tentatively assume 80x115mm substrate size for Feynman

Source: Company data, Nomura estimates

Fig. 137: HyperSocket revenue contribution We estimate it may reach ~5% of total revenue in 2028F

Source: Nomura estimates

2027F

2028F

Hyper-UF

Fig. 138: Comparison of different contact elements

CRS (Top)

Top

Housing

Source: Company data, Nomura research

Fig. 140: Requirements for HyperSocket

Source: Company data, Nomura research

Hyper-LF

Fig. 139: Illustration of HyperSocket

Retainer

Hyper-Liquid

Under Validation

Extremely High Power > 2500W

Source: Company data, Nomura research

Insertion 2

Insertion 3

Industry CPO progress worth tracking

Silicon Photonics (Siph)/CPO is another rising trend in semiconductor manufacturing. We have detailed our understanding of testing flows in CPO testing in our Anchor Report and in Fig. 141 . In May-2026, WinWay hosted a forum to discuss 'The Evolution of CoPackaged Optics (CPO) - Advanced Testing Methodologies for Silicon Photonics', in which it presented the reasons to adopt CPO, different approaches from various industry vendors, testing insertions flows, and WinWay's solutions. EIC Silicon

PIC

Our understanding of CPO testing insertion is as follows: Insertion 1 is PIC and EIC single-sided wafer-level test; Insertion 2 is double-sided wafer-level test after hybrid bonding; Insertion 3 may include two optical engine (OE)-level testing steps after singulation - before and after packaging (attach FAU [fiber array unit]/receptacle/structural reinforcements), and Insertion 4 is the module-level test after the optical engine is mounted on the substrate. WinWay showcased its WLCSP pitch probe head for EIC/PIC wafer/die testing, double-sided probing system, as well as optical engine (OE) test socket and HyperSocket.

While final testing flows and vendor selection could vary by customer, we expect WinWay to have more niche on socket opportunities in Insertion 3 and Insertion 4, namely after singulation, and more likely after packaging, as packaging-level-test has long been its core competency.

Our view on the CPO timeline now largely aligns with nVidia's product roadmap - for scale-out switch to ramp up in 2H26 along with Rubin platform (see 2026 GTC note ). However, given there are a lot of technical challenges for the brand-new architecture, we expect any large volume to come in 2027F and beyond, and the TAM will likely be further enlarged after CPO penetrates into scale-up (likely in Feynman).

Fig. 141: CPO insertion flow

Note: This is a conceptual illustration, not specific to any company or project. Source: Nomura research

Fig. 142: CPO insertion flow and potential suppliers

Source: Nomura research

Insertion 4

Silicon

EIC Silicon

PIC

ASIC

Substrate

Module/System-level test

More through sockel (not via prosing system, " our view)

'inWay

Package Level Test

Fig. 143: CPO test flow and WinWay's offerings

4007m

KIC

EIC/PIC

Die

CPC / CPO

LGA Side

Substrate

WLCSP Fine Pitch Probe Head

(EIC/PIC Wafer test)

Double Sided Probing System

Source: Company data, Nomura research nKCAN

Engine

CPO Substrate

CPO Module

Source: Company data, Nomura research

Fig. 145: WinWay should play a role in package-level test

More through socket (not via probing system, in our view)

Source: Company data, Nomura research

Prond Hanc

Module Level

Twray

1 15

4 **

Module Level Test Methodology

Module Test

Die Level Test

Die Level Test Methodology

Test Requirement Test speed, Alignment, Mechanism Design.

Test Requirement Optical at TOP / Electrical at BTM.

Fig. 144: WinWay's probe card solution for die-level test

Fic/eio

EIC/PIC Wafer

WLCSP Fine Pitch Probe Head

(EIC/PIC Wafer Test)

HyperSocket™

Source: Company data, Nomura research

Fig. 146: WinWay proposes HyperSocket for CPO module test

Source: Company data, Nomura research

1,300

1,100

900

700

500

300

Share price recap

B100 cancellation and GB push out

Farm-Payroll

Macro: BOJ, Non-

WinWay was listed in January 2021, but the share price was under pressure initially due to the US imposing restrictions on Huawei (unlisted), and thus it lost some business opportunities. Other than smartphone, PC/gaming was also a major part of its business. As the smartphone business gradually weakened, WinWay shifted gears to AI/HPC step by step. While WinWay's 2022 operating results showed a significant leap vs. 2021, the share price did not perform much due to overall peaking of the semiconductor cycle and macro headwinds. Finally, along with AI's emergence from end-2022, its share price started to climb. Despite the continued strong performance of AI/HPC into 2023, consumer electronics went through a severe inventory correction in 2023 (before bottoming out in 1Q24). That said, WinWay's share price still doubled from ~TWD400 from early-2023 to ~TWD800 at end-2023, benefiting from AI megatrend (vs. the TAIEX which rose 27% in 2023).

The AI/HPC socket business ramp-up brought its average monthly sales to ~TWD500mn in 2024 from ~TWD300mn in 2023. The probe card business further drove strong growth in 2025. Following its solid revenue expansion in 1Q25, the share price rose substantially (up 148% vs. the TAIEX up 26% in 2025). In 1H26, the share price rose sharply on increased expectations and enhanced visibility on upcoming key project ramp-up. It then started to decline from TWD9,000 in early July to TWD6,500 as of 22 July 2026, as rising macro risks and overall sentiment on AI has taken a slight turn amid concerns about New York's moratorium on data center de velopment and Meta's (META US, Not rated) initiatives around Meta Compute . We also note the recent share price pullback is potentially reacting to company-specific issues after the release of June quarter earnings, for which we observe likely worse-than-expected profitability.

Fig. 147: WinWay's share price events vs. monthly sales, 2023-24

Source: TEJ, company data, Nomura research

Analyst meeting i with positive !

outlook

Sales ramp, broker reports

900,000

800,000

700,000

600,000

500,000

400,000

300,000

200,000

100,000

10,000

8,000

6,000

4,000

Fig. 148: WinWay's share price events vs. monthly sales, 2025-26 YTD

and CoWoS cut

Macro: tariff

Jan salesi

2,000

Jan-25

• visibility on Al projects,

Discussions on price hike

1,400,000

1,200,000

Source: TEJ, company data, Nomura research

Brokers updates, sales jump

CPO forum

Financial analysis and risks

We estimate a 69% revenue CAGR over 2026-28F

We expect the two largest segments - probe card and socket - to drive WinWay's revenue expansion in the next 2-3 years, as more and more AI/HPC projects are being added to the pipeline every day, driving higher volume demand and content value, with greater opportunities from additional test insertions such as BI/SLT and the emergence of CPO, and as WinWay itself also gains share from existing suppliers. Currently, due to the packed project pipeline, the largest revenue bottleneck is capacity. We believe WinWay will stay fully-utilized into 2027F (the company's capacity expansion plan is shown in Fig. 164 ), and pricing power could also improve amid the supply-constrained environment. We model WinWay's total revenue to grow by 84%/73%/65% in 2026F/27F/28F, at a 69% CAGR over 2026-28F, vs. 46% over 2023-25.

Temporary profitability headwinds; well-controlled opex to partly offset GM pressure

We estimate that the strong order momentum for MEMS probe card will temporarily temper WinWay's GM, and expect its GM to drop toward the low end of the 40-45% range in 2026F, vs. 45% in 2025. However, we expect that along with product mix improvement (more AI/HPC mix), better business value proposition, improving pricing power, and higher in-sourcing ratio, its GM will gradually get closer to 2025 levels in 2027-28F. We also expect operating leverage to materialize continuously in the forecast period, partially offsetting any GM pressure. We estimate a 94% EPS CAGR over 2026-28F, vs. 86% in 2023-25.

Fig. 149: WinWay's key financial figures

Source: Company data, Nomura estimates

40,000

14,000

40,000

35,000

35,000

12,000

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10,000

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15,000

4,000

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Probe card +

coaxial socket:

20,000

400

100%

90%

18,000

350

16,000

300

60%

10,000

4,000

2,000

0%

Source: Company data, Nomura estimates

Fig. 152: WinWay's annual operating profit trend

TWDmn

Source: Company data, Nomura estimates

Fig. 154: WinWay's annual product mix

TWDmn

Source: Company data, Nomura estimates

40%

/0

150%

Source: Company data, Nomura estimates

Fig. 153: WinWay's annual EPS trend

Source: Company data, Nomura estimates

Source: Company data, Nomura estimates

Fig. 156: WinWay's P&L

Source: Company data, Nomura estimates

Fig. 157: Nomura forecasts vs Bloomberg consensus estimates for 2026-28F