報告_Nomura_AI半導體伺服器循環是否見頂_20260630

PDF 原檔：報告_Nomura_AI半導體伺服器循環是否見頂_20260630_original.pdf

野村《Asia AI Semi & Server — Is the cycle over?》Anchor Report，2026-06-30，119 頁。核心論點：SOX 自 3 月 +85%／自 2025/5 +211% 後近期回檔屬健康修正，但循環尚未見頂（hyperscaler 2027F capex 仍有上修空間、自有資料中心建置追蹤續升、greenfield 需 2 年使供給吃緊延續至 2027F）。瓶頸由 TSMC（CoW）轉向 WoS 與眾多小元件；漲價與獲利上修為最大催化劑。九檔調升目標價：2330_台積電（市）、3711_日月光投控（市）、5274_信驊（市）、2454_聯發科（市）、6488_環球晶圓（市）、2449_京元電（市）、2383_台光電（市）、6274_台燿（櫃）、4958_臻鼎科技（市）。

圖片清單（已驗證 2026-06-30）

size 篩 ≥40KB 候選後逐張 Read 驗證分類。嵌入 lib/ 頁只挑「真資料圖」，圖說照抄親眼所見。其餘未個別列出之圖多為券商評論 / 財報模型表（docling 已 OCR 成文字）或裝飾性投影片。

原始內容

ANCHOR REPORT

Global Markets Research 30 June 2026

Asia AI Semi & Server

Is the cycle over?

With SOX surging by 85% since our last cycle update in March and up 211% since we revisited the AI theme in May 2025, we have noticed a share price collapse of late. To us, a pullback is healthy following such a surge, particularly when some risks have to be digested. However, we do not seem to have reached the cycle peak yet, given hyperscalers' spending upside into 2027F (despite having insufficient FCF), and our global new data center build tracking showing further upside. More importantly, the two years of greenfield build for new capacity from late-2025 suggests insufficient supply heading into 2027F. Price hikes and earnings revision remain the biggest catalysts, in our view.

Key analyses included in this report:

• Update of our proprietary global new data center build tracking ·
• CoWoS 2027F allocation considering the severe shortages of WoS vs CoW ·
• Unprecedented component supply-mismatch from 2H26F with potential to worsen further into 2027F ·
• xPU/ASIC 2027F outlook: when the elephants fight, the grass get trampled ·
• Renewal of our latest view on the AI and general server market outlook ·
• CPU demand upside and (benefiting) OSATs' CoWoS-like process ·
• SoIC and CoPoS to counter EMIB-T; and benefit to relevant supply chains ·

Research Analysts

Asia Technology

Aaron Jeng, CFA - NITB aaron.jeng@nomura.com

+886(2) 21769962

Anne Lee, CFA - NITB anne.lee@nomura.com +886(2) 21769966

Donnie Teng - NIHK donnie.teng@nomura.com +852 2252 1439

Vivian Yang - NITB vivian.yang@nomura.com +886(2) 21769970

Eric Chen, CFA - NITB eric.chen@nomura.com +886(2) 21769965

Carol Hu - NITB carol.r.hu@nomura.com +886(2) 21769963

Production Complete: 2026-06-29 20:51 UTC

EQUITY: TECHNOLOGY

Asia AI Semi & Server

EQUITY: TECHNOLOGY

Is the cycle over?

Research Analysts

There could be a few valid factors that may explain the recent share price pullback, but likely we have not yet reached the peak of this cycle

Where are we in this AI infra investment cycle?

With SOX surging by 85% since our last cycle update in March (report ) (and up 211% since we revisited the AI theme in May 2025; Fig. 76 ), we have noticed a share price collapse of late. To us, a pullback is healthy following such a surge over such a short period, particularly when we see some risks that have to be digested, e.g., the likely biggest-ever component supply mismatch, hyperscalers' 2027F free cash flow (FCF) issue, execution of many cutting-edge technologies beyond 2027F, and macro risks related to a yield uptrend. However, we do not seem to have reached the cycle peak yet given that hyperscalers' spending may need to show upside further into 2027F (despite insufficient FCF particularly driven by surging memory costs, as this might be a 'go big or go home' competition), and our proprietary global new data center build tracking suggesting further upside from our March update . On the supply side, the two years for greenfield build for new capacities from late-2025 suggests insufficient supply into 2027 (and very likely the supply bottleneck shifting from tech giants such as TSMC [2330 TT, Buy] to other, smaller component makers). Furthermore, price hikes and ongoing earnings upward revision would still be the biggest catalysts. As such, we would still be buyers into weakness. We raise target prices for nine AI tech companies (mentioned below) with this Anchor Report.

TSMC turning aggressive on CoW plan, but the bottleneck could shift to WoS

We now expect TSMC to 'target' chip-on-wafer-on-substrate (CoWoS) capacity of 2,000kpcs in 2027F, from 1,100kpcs in 2026F, and forecast that it would need 2,5003,500kpcs of CoWoS output by 2029F, depending on the scale of annual price hikes, to achieve its 'high-50%' AI revenue CAGR over 2024-29E. In addition, if Feynman production fully migrates to chip-on-panel-on-substrate (CoPoS) in 2029F, TSMC would need to build 700-800kpcs CoPoS capacity by 2029F. However, our contrarian view is that 'WoS' and many other small components would very likely become a bigger bottleneck than 'CoW' in the remaining of 2026F and also into 2027F - which is not a bad reading for long-term cycle sustainability, in our view, but would likely drive short-term share price volatility. As such, we only 'model' 1,800kpcs of CoWoS output in 2028F - which would have profound implications for different GPU/ASIC vendors in 2027F, i.e. when the elephants (nVidia [NVDA US, Not rated] and Google [GOOGL US, Not rated]) fight, the grass (other xPU/ASIC) would get trampled, we think. Separately, outsourced semiconductor assembly and test (OSAT) vendors would not only benefit from TSMC's growing WoS outsourcing but also from further price hikes (given ongoing material cost inflation) and upside from their own CoWoS-like full process (driven by CPUs).

SoIC and CoPoS to counter EMIB-T; relevant supply chains to benefit

Intel's (INTC US, Not rated) embedded multi-die interconnect bridge with TSV (EMIB-T) appears to be emerging as potentially the biggest threat to TSMC's advanced packaging. During TSMC's 2026 North America Symposium in April, TSMC launched its 14x reticle size CoWoS roadmap (2028E) vs a prior roadmap for an interposer size up to 9.5x reticle (2027E). However, our view is that system-on-integrated-chips (SoIC) and CoPoS are two equally critical technologies for TSMC to stay ahead of its competition in advanced packaging. We expect Feynman to target the first-ever GPU-on-GPU SoIC stack. In our view, there would be multiple implications from this: First, the bigger footprint and high thermal design power (TDP) of Feynman would start to drive the adoption of silicon carbide (SiC) carrier. Second, SoIC capacity demand would skyrocket through 2028-29F.

Asia Technology

Aaron Jeng, CFA - NITB aaron.jeng@nomura.com +886(2) 21769962

Anne Lee, CFA - NITB anne.lee@nomura.com +886(2) 21769966

Donnie Teng - NIHK donnie.teng@nomura.com

+852 2252 1439

Vivian Yang - NITB vivian.yang@nomura.com +886(2) 21769970

Eric Chen, CFA - NITB eric.chen@nomura.com +886(2) 21769965

Carol Hu - NITB carol.r.hu@nomura.com +886(2) 21769963

TSMC

Delta

Hon Hai

ASE

EMC

Unimicron

Quanta

Lenovo

AVC

BESI

Wiwynn

Zhen Ding

Rating

Market cap

(USDmn)

Target price (LCY)

New

Old

Stocks for action: Raising target prices across nine AI semi/hardware companies

5,800.0

2,800.0

352.0

730.0

6,880.0

1,350.0

479.0

417.0

524.0

35.0

3,130.0

We reiterate our Buy ratings with higher target prices on:

• TSMC: AI chip enabler ·

Buy

Buy

147,569

109,420

• ASE (3711 TT): upside from WoS and CoW ·
• ASPEED (5274 TT): outright CPU beneficiaries ·
• MediaTek (2454 TT): TPU upside ·

45,836

45,810

• GWC (6488 TT): SiC opportunities in Feynman ·
• KYEC (2449 TT): beneficiary of AI chip testing ·

3,400.0

2,800.0

352.0

575.0

5,285.0

1,350.0

479.0

417.0

524.0

35.0

3,130.0

• EMC (2383 TT)/TUC (6274 TT): CCL benefiting from AI upgrade trends and more price upside from being one of the major supply bottlenecks · 720.0 510.0

ASPEED

Wistron

TUC

GWC

KYEC

Bizlink

Soitec

280.0

• ZDT (4958 TT): an emerging AI PCB/HDI maker ·

19,100.0

280.0

We also like the following Buy-rated stocks: BESI (BESI NA; CPO and GPU-on-GPU SoIC), Soitec (SOI FP; SOI wafer for CPO), Unimicron (3037 TT; substrate also benefiting from multiple trends and more price upside from being another major supply bottleneck), Victory Giant (300476 CH / 2476 HK; AI PCB beneficiary), Compeq (2313 TT), Delta (2308 TT; power top pick), AVC (3017 TT; thermal top pick), Samsung Electronics (005930 KS; memory leader), Bizlink (3665 TT; rack power and data upgrades), as well as Hon Hai (2317 TT) and Lenovo (992 HK) in ODMs.

Fig. 1: Stocks for action

Note: Priced as of 26 June 2026.

Source: Bloomberg Finance L.P., Nomura estimates

11,500.0

1

Last close

(LCY, as of

26 June 2026)

2,340.0

339,000.0

3,880.0

1,810.0

248.5

632.0

5,255.0

975.0

342.4

319.6

362.0

23.4

2,255.0

282.7

4,280.0

580.0

15,615.0

153.0

1,580.0

936.0

308.0

1,855.0

222.5

114.4

Downside

46.4%

97.6%

49.5%

54.7%

41.6%

15.5%

30.9%

38.5%

39.9%

30.5%

44.8%

49.3%

38.8%

20.3%

98.6%

24.1%

22.3%

83.0%

33.9%

28.2%

26.6%

72.5%

55.1%

118.6%

Executive summary

Big picture: We believe there are growing signs of the cycle peaking using conventional signals such as price hikes, LTAs, and possible overbooking. However, given our view that AI demand is real (report ) and AI's impact is dramatic, we have refrained from leveraging conventional cycle wisdom (which has helped us come to the correct conclusions during semi cycle peaks and bottoms over the past decade; Fig. 76 ) during this AI-driven cycle over the past two years. Since 4Q25, we have tracked global new data center build plans as a leading demand indicator for the Asia semi hardware supply chain - which enhanced our conviction on AI amid market concerns/noise in December 2025 (report ) and March 2026 (report ), respectively. In this report, we would like to refresh where we are in the AI cycle. On the supply side , it generally takes two years to build new greenfield capacity (which began in late-2025, when all hyperscalers significantly raised their chip/hardware forward demand outlooks; the earliest signal in our coverage was BMC; refer to our August 2025 ASPEED [5274 TT, Buy] report ), which suggests still likely constrained supply over the next year (e.g., TSMC's next big jump in front-end capacities will be in 2028F; Fig. 20 ). What's more, we have noted that WoS (Wafer-on-Substrate) and many other small components could become a bigger bottleneck than CoW (Chip-on-Wafer) in 2027F - which might not be a bad reading for long-term cycle sustainability, but would likely drive short-term share price volatility.

With demand side factors (hyperscalers' capex upside, our global data center tracking, token consumption trends, etc., see Appendix: CSP comments on AI and investments ) sustaining, across-the-supply-chain price hikes will likely continue, we think. Sustainable upward consensus earnings estimate revisions for Asia semi hardware supply chain companies would still be the biggest catalyst in driving share prices higher - as we predicted to happen through 2026 (report ) - in our view. Risk-wise , we believe AI infrastructure investment momentum is critical (so far, so good based on our tracking), while new technology breakthroughs will be needed from 2028F. We believe lots of cutting -edge technologies need to happen beyond 2027F before the AI chip hardware roadmap can be extended further, including, but not limited to: EMIB-T, CoPoS, GPU-onGPU SoIC, microchannel lid (MCL), co-packaged optics (CPO), 336G/448G SerDes, M9Q/M10Q PCB, PTFE, and new tools/materials for high-density interconnect (HDI) PCB. Owing to surging memory costs, hyperscalers could start facing insufficient FCF in 2027F (Fig. 71 to Fig. 75 ; our latest AI server sales forecast for 2027 suggests eventual upside to hyperscaler capex) - which could cause investor concerns, particularly with the macro risk of yield on an uptrend driven by growing inflation but still decent unemployment rates in the US (report and report ).

Our latest Global new data center build tracking suggests further upside from our March update three months ago. The total number of projects has increased to 280 (from 240), while the gigawatt (GW) level project number has increased to c.50 from 40+. The incremental capacity deployment in 2027F, measured in GW, would grow to 32GW (from 28GW) from 26GW (unchanged) in 2026F. We do not have full-year visibility yet, but the tracking so far suggests 23GW demand in 2028F (up from 21GW). Fig. 2 - Fig. 4 compile our latest findings. Given the surge of AI chip/hardware share prices over the past three months, we hope to see growing 2028 visibility over the next 3-6 months.

We have noticed quite a few interesting points to highlight with respect to TSMC's CoWoS capacity-expansion plan. First, TSMC has turned aggressive in responding to surging AI chip demand and is likely to defend itself from competition from EMIB-T and fanout panel-level packaging (FOPLP), in our view. We thus now expect TSMC to target CoWoS capacity of 2,000kpcs in 2027F, from 1,100kpcs in 2026F. Though we do not have 2028-29F visibility, our back-of-the-envelope calculation suggests that TSMC would need somewhere from 2,500-3,500kpcs of CoWoS output by 2029F, depending on the scale of annual price hikes, to achieve management's goal of a 'high-50% AI revenue CAGR' (Fig. 21 and Fig. 22 ). Another interesting exercise we have done in terms of long-term CoWoS plans is asking, ' How would CoPoS affect the CoWoS capacity plan? '. A year ago, our view on TSMC's CoPoS plan (report ) was that we expected CoPoS to enter mass production only from 2029F (much later than the Street estimate). Despite this, we hope that TSMC could pull forward its schedule to meet nVidia's Feynman GPU timeline (2H28). With our 'napkin math' assuming nVidia Feynman production fully migrates to CoPoS in 2029F, TSMC would need to build 700800kpcs CoPoS capacity by 2029F (How will TSMC's CoWoS capacity shape up

through 2029F? ). We believe 50% of CoWoS capacity in 2029F would need to find new customers in this scenario (however, we note that in reality, product transitions do not happen overnight).

Though TSMC has turned aggressive in its CoWoS plan (precisely, its CoW plan), our tech team's contrarian view is that 'WoS' (not controlled by TSMC) and many small components would very likely become a bigger bottleneck than 'CoW' (controlled by TSMC) into 2027F - which is not a bad reading for long-term cycle sustainability, but would likely drive short-term share price volatility. Taking these new factors into consideration, we only model 1,800kpcs of CoWoS output in 2027F (despite our view of TSMC's target of 2,000kpcs) - which would have profound implications for different GPU/ASIC vendors in 2027F, in our view.

We believe there will be an unprecedented component supply-mismatch period in 2H26F, and we expect it will get worse in 2027F , as in 2H25 many component suppliers still underestimated (more so than TSMC) the order upside potential from AI when they made their capacity expansion plans. In addition to the well-known advanced node/packaging, memory, and CPU shortages, PCB/CCL, IC substrate, higher-end capacitors, power management IC (PMIC), and optical components, are also already in shortage currently, and we forecast demand-supply conditions will further deteriorate when Rubin and Trainium 3 ramp from 2H26. This could further affect the supply for nonAI subsectors such as consumer and auto, in our view. Also, supply chain price hikes could continue or increase with worsening shortages , we think.

In view of our assumptions and observations above, we are raising our 2026-27F server market forecasts on stronger AI and general/CPU server sales (Fig. 69 ). We now forecast global server revenue growth of 74%/65% y-y for 2026F/2027F (vs 43% y-y for 2026F previously), with AI server revenue growth rates at 78%/76% y-y for 2026F/2027F (previously 58% y-y for 2026F) and general/CPU server revenue growth rate at 67%/43% y-y for 2026F/2027F (previously 16% y-y for 2026F). For 2026F, considering rising capex guidance from top US CSPs YTD and increase in neoclouds, we raise our GB/VR rack shipment assumption from 50k units to 54.5k units for 2026F (Fig. 69 ). Of this, we assume VR200 to account for 15-20% in 2026F, with concentration in 4Q26F . We assume a transition from GB300 to VR200 during late-2Q26F to 3Q26F, as top CSPs will likely prefer to wait for VR200, instead of continuing to install more GB300s. In the transitional period, we expect neoclouds to play a bigger role in buying more systems to support the continued token demand growth at AI companies. We also introduce our forecast of 62k racks for 2027F , with a potential transition from Rubin to Rubin Ultra happening in 2Q27F.

In 2H25, we concluded in our AI Semi & Server Anchor Report that nVidia would continue to secure 60% of CoWoS allocation (along with other key materials such as T-glass), as nVidia had booked 'strategic resources' well ahead of its peers to crowd out competitors. This strategy has worked out well, in our view - e.g., Google, despite Geminis' impressive breakthrough from late 2025 (news ), hasn't been able to acquire much more support in 2026. AMD's (AMD US, Not rated) GPU and AWS's (AMZN US, Not rated) ASIC have progressed through 2026 with downside to beginning-of-the-year expectations. Looking into 2027F CoWoS allocation, we expect the following dynamics (many of which are contrarian). First, CoW capacity allocation would be less critical than whether GPU/ASIC vendors can secure support from substrates and other smaller components (e.g., CCL, capacitors); Second , Google's tensor processing unit (TPU) share in CoWoS could rise further to 26% in 2027 from 23% in 2026 (nearly double y-y growth) on its proven Gemini performance, complete Google ecosystem and share gain; Third , despite our view that nVidia would continue to strive for 60% allocation, our models build in our assumption that nVidia's share in CoWoS would slide to c.55% in 2027F given the squeeze by TPU; Fourth , the other GPU/ASIC vendors would be squeezed even more, e.g., we assume AMD's CoWoS capacity share would only marginally improve y-y despite a low base, while AWS's CoWoS capacity share might even fall y-y in 2027F; Fifth , we raise our AI revenue growth estimate for TSMC to 77%/67% for 2026F/27F (from 69%/24% previously), vs the company's target of a 'high-50% revenue CAGR over 2024-29E' (Fig. 26 ); Sixth , despite our c.55% CoWoS allocation assumption for nVidia in 2027F, we see upside to consensus revenue forecast if it can sell out all those booked capacities (Fig. 72 ); Seventh , though we expect TPU to enjoy the fastest growth in 2027F among AI logic semi, the majority of growth would be taken by MediaTek (its share in TPU could more than double to 30%+ in 2027F from c.15% in 2026).

TSMC's more aggressive attitude on expanding CoW capacity would benefit OSATs directly, in our view, given TSMC's current full outsourcing of WoS. Though we believe WoS supply constraints could limit shipment upside for OSATs, the likely ongoing price hikes for substrates could drive OSAT packaging prices higher, too. Separately , we expect the next growth catalyst for OSATs to shift to their own CoWoS-like full processes. Other than technology readiness, we believe another key factor hindering OSATs from engaging in CoW processes is the enormous losses that would be incurred if there were to be immature assembly yield. That, in our view, is the reason why the high-performance computing chips using OSATs' CoW to ramp up volume from 2H26 are mostly CPUs (Fig. 37 ; which do not carry expensive HBM content), such as AMD's Venice CPU by ASE/SPIL or nVidia's Vera CPU by Amkor (AMKR US, Not rated) . Fig. 57 summarizes the skyrocketing TAM outlook for the server CPU market; also see Appendix: other critical developments and key quotes from major server CPU players for more details.

In the meantime, Intel's (INTC US, Not rated) EMIB-T appears to be emerging as potentially the biggest threat to TSMC's advanced packaging given its capability of large-reticle size packaging. The most closely watched EMIB-T project now is Google's v9 TPU in collaboration with MediaTek given its high complexity and large volume (set to ramp-up in 2028, according to our industry survey). The >9x reticle-size chip-level footprint (details in our February 2026 MediaTek report ) is something that could not be addressed by TSMC's CoWoS roadmap by the time when Google's decision was made, we suppose. Also, TSMC probably was not looking to expand CoWoS capacity that much at end-2025 (refer to our December 2025 Anchor Report ). Fig. 44 summarizes our view on EMIB-T supply chain beneficiaries.

Now, it appears to us that TSMC has turned more aggressive on its advanced packaging investments. C.C. Wei, the company's chairman, made it clear during TSMC's April 2026 earnings call that the company 'works very hard to meet all the demand' and 'doesn't leave any business on the table'. During its 2026 North America Symposium in Apr i l , TSMC launched its 14x reticle size CoWoS roadmap (by 2028E; Fig. 46 ) vs a prior roadmap of up to 9.5x reticle size (2027E; Fig. 45 ). However, our view is that SoIC and CoPoS are two equally critical technologies for TSMC to stay ahead of its competition in advanced packaging. We previously wrote that the CoPoS will enter mass production in 2029F, but we hope TSMC could pull this forward and ramp it along with the Feynman timeline (2H28F). What's more, we expect Feynman to target the first-ever GPU-on-GPU SoIC stack -which would lead to higher computational power even with limited growth in interposer reticle stitching size. Our latest study suggests a Feynman interposer reticle size at c.6x (footprint in Fig. 49 ; up from c.5x from Rubin) by using SoIC. We believe there would be multiple implications from this: first, the bigger footprint and high TDP of Feynman would start to drive the adoption of SiC (an upgrade of carrier silicon - concept and location illustrated in Fig. 52 , a cross-sectional view of AMD MI300); second, SoIC capacity demand would skyrocket through 2028-29F. We expect SoIC capacity to double in 2027F (mainly driven by nVidia's CPO) and double again in 2028F (mainly driven by nVidia's Feynman, see Fig. 51 ).

All together, we largely keep our structurally bullish stance and reiterate our Buy ratings on TSMC, ASE, MediaTek, ASPEED, GWC, KYEC, EMC, TUC, and ZDT with higher target prices. We would be mindful about rising volatility from component supply mismatches and the macro yield rate outlook. Structurally, we look forward to full-year 2028F global new data center build visibility over the next 3-6 months. In the upstream semiconductor space, we also like BESI for CPO and GPU-on-GPU SoIC opportunities, Soitec for SOI wafers in CPO, and Samsung Electronics for its memory leadership.

Within the downstream space, we reiterate our Buy rating on Unimicron, as we think its IC substrate business will be a top beneficiary of multiple future trends, such as EMIB-T, CoPoS, and CPO. We like CCL companies, such as EMC and TUC, as we expect them to continue to benefit from supply tightness (with price-hike potential), material upgrades from low-loss requirements for future AI PCBs, and increasing numbers of peripheral boards such as CPUs and switches in addition to AI GPU/ASIC boards.

For the PCB sector, we reiterate our Buy ratings on ZDT and Compeq. We think the strong growth of optical module mSAP boards will be margin-accretive growth drivers for Unimicron, ZDT and Compeq. For AI PCB/HDI, we believe the increasing number of boards for AI GPU/ASIC/networking/CPU and spec upgrades will fuel the growth of the AI PCB market, benefiting ZDT and Unimicron. ZDT is an emerging AI PCB/HDI maker, and is well positioned to penetrate into nVidia, Google, and AWS's PCB/HDI more

meaningfully from 2H26F, in our view.

For the power supply sector, we believe recent concerns about a delay in 800VDC shipments have been overdone and reiterate our Buy rating on Delta, as we believe it will be a leading supplier for the upcoming +/-400VDC project ramp-up from 2H26F and we believe the +/-400VDC volume, if ramped up smoothly, will be substantial enough to beat market expectations on HVDC in 2027F (not much contribution needed from 800VDC). For thermal plays, our top pick is AVC, and we expect the ramp-up of VR200 and Trainium 3 and its new penetration into Google's TPU will be positive catalysts in 4Q26F.

Global new data center build tracking

Steady stream of project rollouts to provide robust latent hardware demand over next 2-3 years, in our view

Projects have been announced in succession with GW-scale

Since our last update at end-March (report ), we have continued to see more projects rolling out, and our datacenter project universe has increased from ~240 to ~280. Notably, we see some GW-scale projects such as Nebius's (NBIS US, Not rated) 1.2GW data center project in Pennsylvania (news ), Softbank's (9984 JP, Buy) 5GW project in France (press ), and SK Telecom's (SKM US, Not rated) gigawatt-scale AI cloud in Korea. By project owner, we see fewer GW-scale projects announced by the top-4 CSPs in this update. However, we still observe these hyperscalers investing globally, such as Microsoft's (MSFT US, Not rated) investment plans in Singapore, Japan, and Australia; Google's investment plans in Austria, Missouri (US) and Sweden; Meta's (Meta US, Not rated) investment plans in Tulsa, Oklahoma (US), and AWS's investment plan in France. That said, less new projects from top-4 CSPs announced with GW-scale, either no disclosure on capacity or with smaller scale.

Our selected GW-scale projects increased to ~50 this time. Similar to our March update , we see more projects supporting stronger hardware deployment in 2027F, and as time goes by, we also see more projects spanning into 2028F. The incremental capacity deployment is 32GW/23GW in 2027F/2028F from these handpicked projects, on our estimates (vs 28GW/21GW last time), indicating demand for 4-6mn AI chips per year (Fig. 3 ).

To better capture potential hardware demand, we further review the rest of the projects within our sample universe. For the rest of the projects, excluding 'shell-only' projects, there are ~40 projects smaller than 1GW in scale, and ~100 projects for which power consumption has not been disclosed. The average power consumption of small projects is 300MW, and we simply assume the rest of the projects to be 100MW each, which could represent an additional 20GW+ in hardware demand. 20GW is equivalent to 3-4mn Rubin chips, or 420k CoWoS demand throughout the deployment period.

Some projects halted

However, we also note some projects have ceased: Crusoe (unlisted) announced on 10 June that it will cease the expansion of Project Jade on a client request, a 1.8GW (up to 10GW) project. We have removed this project from our calculation base. It was also reported on 10 May that Microsoft and G42's (unlisted) USD1bn data center project in Kenya had been halted on payment issues. Our simulation this time reflects these developments.

China ecosystem is also aggressively accelerating datacenter build-outs

We acknowledge the aggressive expansion intention in China, through both national strategies and massive capital expenditures by technology giants. In June 2026, Bloomberg News reported (link ) that China's government has drafted an unprecedented nationwide AI computing network plan, aiming to invest USD295bn (~CNY2tn) over the next five years to achieve a fully interconnected national grid of distributed data centers by 2028 (report ). Besides the announcement, notable datacenter infrastructure activities in China include:

• Eastern Data and Western Computing: announced in May 2021. The plan proposed a new computing network system that integrates data centers, cloud computing, and big data, as well as Eastern Data and Western Computing demonstration projects that will enable high-quality, green data centers. ·
• Chindata Group (unlisted): The company continues to announce datacenter projects. Several years ago, it announced that the Taihang Mountain Energy and Information Technology Industrial Campus in Datong, Shanxi went into operation (ba ck in Oct 2020 ). Recently, the company also announced a partnership with HEC Group (600673 SH, Not rated) for new AI compute projects. ·

However, we do not specifically include these China data center projects in our calculation base, as these projects are likely aiming to adopt domestic compute chips, which are less relevant to our CoWoS capacity estimates. Although companies such as Chindata Group have also announced data centers beyond China (in regions such as Malaysia ), the scale is relatively small, and they are not included in our selected samples.

Fig. 2: Major data center infrastructure buildouts

Source: Company data, Nomura research

Fig. 3: Our back-of-the-envelope calculation on GW deployment trends

We see growing GW deployments into 2026-28F

From GW to Chips

Computing power % as an infra

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VR NVL72

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180

266

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189

Source: Nomura estimates

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Fig. 4: Incremental capacity deployment (GW)

We have seen more project buildouts over the past several months

Note: Adjusted: We removed same infrastructure projects for better comparison.

Source: Nomura research

CSPs are scrambling for compute capacity

Neoclouds continue to play a role

Back in March , we mentioned that nVidia had signed deals with CoreWeave (CRWV US, Not rated) and Nebius in 2026 to deploy 5GW+ AI infrastructure each by 2030. nVidia also invested USD2bn in each of the companies. We also pointed out that in March, IREN (IREN US, Not rated) only announced a purchase agreement with nVidia. Not surprisingly, in May-2026, IREN and nVidia further announced a similar deal, under which two companies will deploy up to 5GW nVidia DSX-aligned AI infrastructure overtime. Furthermore, IREN has issued a five-year right for nVidia to purchase up to 30mn shares of ordinary stock of IREN. Note that for these three deals, we record individual projects for IREN and recorded 5GW as a whole for CoreWeave and Nebius, as IREN's projects are larger and clearer, and the two others are relatively scattered. We note Meta also expanded the deal with CoreWeave in Apr-26, when it signed a long-term agreement for AI cloud capacity that will last until Dec 2032, with a USD21bn deal value (initial deployments will be nVidia Vera Rubin platforms).

We believe neocloud is in an attractive position as a favorable choice for CSPs to access computing capacity, given that CSPs can: 1) shorten lead time (compared to CSPs' own buildouts); 2) gain faster access to the latest technologies (some neoclouds have priority to the latest AI chips); 3) mitigate risks for demand erosion; and 4) in part provides some financial flexibility. Also, during platform transition periods, CSPs may not be willing to expand more capacity for current generation chips, but still need tokens to fill the gap before new generation chips are ready, thus turning to neo clouds.

In the meantime, we see these agreements to turn into real orders. In Nov-25, when IREN announced a multi-year agreement with Microsoft (USD9.7bn), it also entered into an agreement with Dell (DELL US, Not rated; USD5.8bn) to purchase GPUs and ancillary equipment. In Mar-26, IREN announced another USD3.5bn purchase agreement with Dell. In May-26, IREN separately signed a five-year AI infrastructure cloud service contract with nVidia (USD3.4bn), and then announced to purchase USD1.6bn GPUs from Dell to support this USD3.4bn contract. These announcements are encouraging, in our view, as they indicate real hardware demand.

Shell-only projects gradually find their tenants

We removed some shell-only projects in our March update for conservativism, and we keep the same approach this time for our calculation base. However, we note that more shell-only (campus-only) projects have found tenants. For example, Applied Digital (APLD US, Not rated) continued to announced new lease deals for its data center campuses. CoreWeave is one of the lessee named . Lodha Developers (LODHA NS, Not rated) mentioned Amazon when it announced a data center plan in Jan-26, and Meta also announced that it had signed a lease deal with Reliance (RELIANCE NS, Not rated) for

168MW capacity within two years in June-26. These lease agreements boost confidence in potential hardware demand.

Cipher (CIFR US, Not rated) is another name frequently mentioned, and we also classified the company's projects as 'shell-only'. That said, we see more engagements between the company and hyperscalers. Its Barber Lake campus partners with Google and Fluidstack (unlisted), and the company has also signed lease contract with Amazon ( press ). Cipher also further announced that it had signed a new 15-year data center campus lease in Mar-26 with an undisclosed hyperscale tenant. As of June-26, Cipher already contracted 700MW capacity.

Similar to Core Scientific (CORZ US, Not rated) and Hut 8 (HUT US, Not rated), Cipher is pivoting from crypto mining companies to AI/HPC datacenter landlords. Hut 8 also announced AI data center lease deal for its River Bend Campus and Beacon Point Campus . These companies have competitive advantages in securing land, robust grid interconnections, and power capacities. IREN is another similar player that has transformed from Bitcoin miner to AI infra player, but IREN not only acts as colocation landlord, it also purchases GPUs directly.

From our understanding, the supply chain could be:

Power and land developers secure land/water/electricity as well as authority approval, then infrastructure companies build shells and facilities (Level L0/L1). ODMs are L2. Hardware buyers such as CSPs/Neo clouds/LLM players are L3/L4. In a neo-cloud leasing business model, companies such as CoreWeave become L0/L1 companies' tenants, purchase hardware (either through or not through L2), and then sign computing power deals with hyperscalers/LLM players (L3/L4). Note that the distinctions between each layer have been blurring, and some companies such as IREN operate hybrid business models in different projects. The simple classification (L0-L4) is just for better understanding of business model and supply chain.

Some examples of the value chain:

• Applied Digital builds campus, CoreWeave leases campus, purchases GPUs from nVidia, and sells computing power to hyperscalers. We only record CoreWeave's agreement with nVidia's 5GW GPU as a ceiling. ·
• IREN, through Dell, built its own data center, and sold computing power to Microsoft and nVidia. We record individual projects given scale (>1GW) and clarity. ·

In our sample collection for CoWoS demand calculation, we do not include projects without tenants, and do not necessarily include all L0/L1 projects with lease contracts to avoid double count. That said, we view more tenants disclosed a positive sign for future hardware demand.

SpaceX - a new source of computing power?

As discussed in our Global Satellites report , SpaceX (SPCX US, Not rated) has entered into computing capacity supply agreements with third-parties to fully utilize/monetize its datacenter capacity. This kind of business model may become more common, in our view. Companies with more capital/resources on hand may aggressively build own datacenter, while if not fully utilized for internal operations and models, they can in turn rent this capacity out to those who urgently need immediate access of computing power, and enhance the clusters' Model FLOPS Utilization (MFU).

SpaceX entered into Cloud Service Agreements with Anthropic (unlisted) in May 2026. Anthropic is able to access the compute capacity across Colossus and Colossus II, paying USD1.25bn per month through May 2029, with capacity ramping up in May and June 2026 at a reduced fee. SpaceX would retain its ownership and intellectual property rights in its content, AI models, and related data. Through the structure, SpaceX could still reallocate the capacity for its own internal initiatives if needed in the future, according to the prospectus. SpaceX believes that it has sufficient capacity to provide compute for its AI models, and expects to enter into more similar contracts for compute capacity with third parties.

On 5 June 2026, SpaceX announced that it had signed multi-year Cloud Service Agreements with Alphabet, in which Google would pay USD920mn each month starting October 2026 to June 2029 to lock in SpaceX's compute capacity.

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— Other

Anthropic is growing strongly and worth tracking

Following ChatGPT's strong breakthrough and Gemini's emergence, Claude is also gaining traction in the market (Fig. 5 - Fig. 6 ). This is also reflected in Anthropic's revenue the run-rate of which surged from USD9bn at the end of 2025 to >USD47bn in May 2026. We also see increasing engagements with a sizable amount of deals between Anthropic and other key players in the AI world. Just as OpenAI's (unlisted) aggressive Stargate announcement, Anthropic in Nov-25 announced a USD50bn investment in American computing infrastructure, building datacenters with Fludistack in Texas and New York. The investment amount shall cover most below computing power purchase agreements, as well as its collaboration with Hut 8 and Fluidstack, in our view.

AWS and Anthropic's relationship can be traced back to 2023-24, when Amazon made USD4bn investments each in 2023 and 2024. Since then, AWS has continued to be Anthropic's major cloud partner. One of AWS's key data center projects, Project Rainier , was the result of this collaboration. Anthropic actively used Project Rainier (featuring 500k Trainium 2 chips) to build and deploy Claude. In Apr-26, it expanded the deal, and Anthropic signed a new agreement with Amazon to secure up to 5GW capacity for training and deploying Claude. In the same agreement, Anthropic is to commit more than USD100bn over the next ten years to AWS technologies, spanning Graviton and Trainium 2/3/4, with the option to purchase future generations when available. Built on the existing USD8bn investments, Amazon is investing USD5bn in Anthropic along with the announcement in Apr-26, up to an additional USD20bn in the future.

Google was also an early investor of Anthropic from 2023 to early 2025. The relationship extended when Anthropic announced it would expand adoption of Google Cloud technologies, including up to 1mn TPUs (over 1GW capacity online in 2026) in Oct-25. In Apr-26, Anthropic announced that it signed a new agreement with Google and Broadcom (AVGO US, Not rated) for multiple gigawatts of next-generation TPU capacity coming online starting in 2027. While not officially announced, Google reportedly will invest up to USD40bn in Anthropic, and Anthropic is committed to spending USD200bn with Google Cloud over five years.

Note that besides AWS and Google ASICs, Anthropic also bonded relationship with other players on nVidia GPU platforms.

• In Nov-2025, Anthropic, nVidia and Microsoft announced strategic partnerships, when Anthropic committed to up to 1GW nVidia GB/VR systems. nVidia and Microsoft were committed to invest up to USD10bn and USD5bn, respectively, in Anthropic. Although this has not yet been officially confirmed by the companies, news outlets have reported than Microsoft is negotiating with Anthropic to serve its in-house ASICs as well. ·
• Anthropic also utilized compute capacity from SpaceX/xAI's Colossus for Claude (based on nVidia GPUs), as mentioned in above paragraphs. ·
• CoreWeave announced a multi-year agreement with Anthropic in Apr-26. The collaboration between Anthropic and CoreWeave will initially focus on a phased infrastructure rollout, with the potential to expand over time. ·

Fig. 5: Gen AI website traffic share

As of Apr 2026

Source: Similarweb, Nomura research

Fig. 6: Gen AI website traffic share Gemini and Claude continued to grow

Source: Similarweb, Nomura research

— Perplexity - Copilot

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30%

1 month ago

Grok

Copilot

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Fig. 7: Major announcements of data center buildouts - AWS

*AWS announced (Mar-2026) to deploy 1mn+ nVidia GPUs starting in 2026

Source: Company data, Nomura research

Fig. 8: Major announcements of data center buildouts - Google

Source: Company data, Nomura research

Fig. 9: Major announcements of data center buildouts - Meta

Source: Company data, Nomura research

Fig. 10: Major announcements of data center build-outs - Microsoft

*MSFT signed letter of Intent with Nscale for up to 1.35GW VR NVL72, deployment beginning in late 2027.

*Crusoe announced to build 900MW datacenter for MSFT in Abilene, Texas on 27 March 2026. The first building expected to be energized in mid-2027.

Source: Company data, Nomura research

Fig. 11: Major announcements of data center build-outs - HUMAIN

Source: Company data, Nomura research

Fig. 12: Major announcements of data center buildouts - CoreWeave

Source: Company data, Nomura research

Fig. 13: Major announcements of data center buildouts - Oracle

Source: Company data, Nomura research

Fig. 14: Major announcements of data center build-outs - OpenAI

Source: Company data, Nomura research

Fig. 15: Major announcements of data center build-outs - Nscale

Source: Company data, Nomura research

Fig. 16: Major announcements of data center build-outs - Nebius

Source: Company data, Nomura research

Source: Company data, Nomura research

unparlorol

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TSMC turning aggressive on 2027F CoW capacity, but WoS will become bottleneck, in our view

TSMC has turned aggressive in responding to surging demand and to defend against (future) competition

In our last update in December , we flagged TSMC's intention to dial up its CoWoS capacity build-out in 2026F by expediting equipment delivery, in response to nVidia's request (although ~60% of TSMC's CoWoS capacity has already been booked by nVidia) and ASIC customers' (led by Broadcom) eagerness to secure more capacity support. Despite this, we believe TSMC would still keep a disciplined stance on its CoWoS capacity additions and will not overreact to customers' 'potentially inflated' demand forecasts, and likewise for TSMC's fabrication capacity despite a likely 3nm demand surge in 2026F due to a somewhat 'synchronized' large-die AI chip migration cadence (e.g., nVidia's Rubin, Google's TPU v8t/v8i and AWS' Trainium 3).

To date, TSMC's supply is apparently still constrained across the front-end and the back-end given the demand strength from AI, and the company has expressed its commitment to expand its capacity in due course, citing that it 'works very hard to meet all the demand ' and 'doesn't leave any business on the table ' (see remarks from 4Q25 and 1Q26 results ). Interestingly, TSMC's management has decided to step up capex investment to increase its 3nm capacity - in contrast to its old plan, in which TSMC did not add new capacity to a node once it reached the target capacity (about 130-150kwpm, in our view) - with additions in Taiwan, Japan, and the US. TSMC has laid out its plan to drive N5/N3 combined capacity growth (a 25% CAGR over 202227E) with equipment commonality and technology integrations (see our takeaways from the Technology Symposium ).

Our latest supply chain survey suggests TSMC will likely expand its CoWoS capacity to 1,100kpcs in 2026F (or c.130kwpm by the end of 2026F) vs our previous assumption of 1,0501,100kpcs (or c.110kwpm by year-end), increasing this to 2,000kpcs in 2027F vs our previous assumption of 1,300-1,350kpcs. Although TSMC has turned more aggressive in its CoWoS plan (more precisely, its 'CoW' plan), our contrarian view is that 'WoS' (not controlled by TSMC) and many small components would very likely become a bigger bottleneck than 'CoW' (controlled by TSMC) in 2027F. We only model 1,800kpcs of CoWoS output in 2027F (despite our assumption of a TSMC target of 2,000kpcs).

At the front end, we model TSMC to form 160kwpm 3nm capacity by end-2026F (from 130kwpm by end-2025, mostly driven by cross-node conversion) and 175kwpm by end-2027F. We expect 225kwpm of 3nm capacity by end-2028F, with the fabs in Arizona and Kumamoto joining the production lineup. All told, we reason the magnitude of capacity builds remains prudent, judged by not only the 'demand forecasts' of AI chip customers (which occasionally could be misleading against the backdrop of shortage), but more importantly by new data center build trackers (elaborated on in the 'Global new data center build tracking ' section of this report, which we view as a leading indicator beyond Asia supply chain data points). Also see the below section, 'When the elephants fight, the grass gets trampled for our refreshed view on TSMC's AI revenue, CoWoS allocation assumptions and competitive landscape observations in terms of AI chips.

Fig. 18: TSMC turning more aggressive on CoW capacity expansion

Source: Company data, Nomura estimates

Fig. 19: But the output will be constrained by "WoS"

Source: Company data, Nomura estimates

2027F

TSMC's CoWoS output

Fig. 20: TSMC's front-end fab capacity planning

Source: Company data, Nomura estimates

How will TSMC's CoWoS capacity shape up through 2029F?

While we have no clear bottom-up estimates about how TSMC is going to expand its CoWoS capacity beyond 2027F, we try to triangulate a possible trajectory based on TSMC's AI semi growth guidance and our assumptions of manufacturing content added. See Fig. 21 for our simulation.

TSMC guided its AI accelerator revenue would grow to a high-50% CAGR over 2024-29E, implying USD115bn of revenue from AI by 2029E. Additionally, we generalize from our proprietary TSMC AI logic semi model, which analyzes major AI accelerator revenue contributions, that roughly 30-35% of its manufacturing content comes from advanced packaging. For simplicity, we assume all the advanced packaging revenue to TSMC comes from CoWoS (e.g., ignoring SoIC, which is an accretion to back-end content). Altogether, TSMC's guidance might hint to form 2,500-3,500kpcs in annual CoWoS capacity by 2029F, vs 680kpcs in 2025, and this would suggest a 40-50% capacity CAGR over 2025-29F compared to a >80% CAGR planned for 2022-27E (report ).

Fig. 21: A simulation of TSMC's long-term CoWoS capacity planning

Source: Company data, Nomura estimates

A question stemming from the above-mentioned long-run analysis is how TSMC would build its CoWoS capacity in view of an ultimate transition to CoPoS. While, again, we do not have any clear bottom-up estimates since the CoPoS platform remains in the R&D stage at this moment, we have attempted some 'napkin math' about the capacity formation trade-off. TSMC's current AI revenue guidance with our assumed 30-35% content from back-end in 2029E should imply c.USD35bn from AI chip advanced packaging, and nVidia alone could consume ~1,400kpcs of CoWoS capacity if it keeps on securing ~50% of the supply.

• If we tentatively assume the Feynman GPU has an interposer sizing up to 6x reticle (vs Rubin's ~5x reticle) and all the capacity taken by nVidia in 2029E is directed for Feynman production, then the total Feynman output would be 11.4mn units. ·
• The 6x reticle size interposer yields about 8 units on a round 300mm carrier. If the same interposer is produced on a square 300mm panel carrier, each carrier could output about 15 units. We note that AMD believes interposers at >8x reticle size are moving toward panel level packaging for better economics (report ); our 'napkin math' shows that for an 8x reticle size interposer, a round 300mm carrier outputs 5-6 units vs 9-10 units on a square 300mm panel. ·
• If all the 11.4mn Feynman unit outputs move from CoWoS to CoPoS (310x310mm), we believe TSMC would have to prepare 700-800k panels of CoPoS annual capacity instead of c.1,400kpcs of CoWoS for nVidia in 2029E. ·

Although the simulation might be radical, it explains to a certain extent why TSMC has been very prudent with its CoWoS capacity investments that may face a long-run migration to CoPoS, which could result in a huge chunk of spare CoWoS capacity.

Fig. 22: Sensitivity of TSMC's CoWoS capacity planning

Source: Company data, Nomura estimates

When the elephants fight, the grass gets trampled

nVidia and Google are the elephants in AI Semi

AI semi forecast refresh: nVidia and Google will compete for resources at TSMC in 2026-27F, at the cost of other AI chips, in our view

We review our AI logic semi revenue model (from the perspective of TSMC) and key assumptions to assess the demand trajectory for nVidia and ASIC following upward capacity assumption revisions (see TSMC turning aggressive on 2027F CoW capacity, but WoS will become bottleneck, in our view ).

We are raising our 2026F AI semi forecast to 77% y-y growth (from 69% previously) and model 2027F growth of 67% (vs +24% y-y previously), compared to TSMC's AI revenue CAGR guidance of 'toward high-50% CAGR from 2024-29'. See Fig. 35 for a complete summary of our analysis. We estimate AI to make up mid-20% of TSMC's revenue in 2026F (from a high-teens percentage in 2025), further jumping to >30% in 2027F, with nVidia remaining the largest AI revenue contributor at 60%/53% in 2026F/27F (was 56%/51%), followed by Google's 20%/25% (previously 18%/17%). As nVidia and Google together already account for c.80% of TSMC's AI revenue (vs 70-75% a few years ago), the competition between nVidia and Google to secure capacity at TSMC (and possibly elsewhere in the Asia AI supply chain) could come at the cost of other AI chips.

Fig. 23: Hyperscalers' custom silicon roadmap

Source: Company data, Nomura estimates

In our December 2025 projection , we expected TSMC to allocate c.60% of its CoWoS capacity to nVidia in 2026F because of the intention to retain 'strategic resource' to crowd out ASIC supply, and the production mix would shift toward more Blackwell than Rubin. We expected TSMC to allocate more CoWoS capacity to Google TPU (primarily via its design service partner Broadcom) to support the product ramp-up in 1H26F (Ironwood/TPU7x). We then also observed increasing traction in AMD's AI GPUs in the supply chain, after the October 2025 announcement of the strategic partnership between OpenAI and AMD (press release ).

With changes in TSMC's capacity expansion scale and its initial planning for 2027F capacity allocation around the corner, we offer a preview of how TSMC's 2027F AI production mix could shape up, as well as elaborate on our observations about TSMC's major AI customers below nVidia should remain as aggressive, and we suppose Google could be more proactive in securing supply.

• nVidia: We do not expect much change to nVidia's CoWoS capacity bookings at TSMC in 2026F (c.60% of capacity share), but see incrementally lower units of Rubin production, with overall output mix skewing a bit more toward Blackwell. We do not expect Rubin GPU production to ramp up significantly until 4Q26F, which implies that actual rack shipments in mass volume could be even later, and one of the bottlenecks is the HBM4 schedule (report ). Another notable change is the design of Rubin Ultra (slated for production in 2027E, according to nVidia), the floorplan of which could scale down to Rubin-like (2 GPU dies per package) vs prior expectation of two Rubin modules connected on a substrate (CoWoS-L + MCM; four GPU dies per package, see our report about a compromised architecture given unreadiness of CoPoS). Such a change is validated by nVidia's demo of the Kyber compute blade, which accommodates four GPUs (Fig. 62 ) vs the showcase of two GPUs per blade last ·

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year, implying a smaller package footprint. We assume nVidia to take c.55% CoWoS capacity allocation at TSMC in 2027F, and the AI GPU builds will be completely made of Rubin and Rubin Ultra. We therefore estimate TSMC will generate 60%/53% of its AI revenue from nVidia in 2026F/2027F, recording +68%/+47% growth.

• Google TPU: We continue to expect revenue contribution upside for TSMC from TPU and raise our unit build assumption for TSMC in 2026-27F. We expect 2026F revenue/chip volume upside to come from TPU7x (codenamed Hammer) and TPU v8t (codenamed Mad Dog) vs our December projection, despite lower revenue/volume from TPU v8i (codenamed Hell Cat) because of a slower-thanexpected ramp-up. We believe MediaTek (the ASIC design partner of TPU v8t) will benefit from more aggressive TPU capacity bookings by Google in 2026-27F, while the dynamics in 2028F remain a mystery to us, subject to the execution of Google and Intel's EMIB-T. On the back of more aggressive procurement by Google in 2027F, we estimate Google's TPU contribution to TSMC's AI revenue will grow by 200% (we previously forecasted +120% y-y) in 2026F and +116% in 2027F, and the output by TSMC could translate into 4.2mn/8.3mn TPU builds by Google in 2026F/27F. · · Meta

2025

• AMD: We refresh our underlying spec assumptions for MI455X after AMD demonstrated the chip during CES 2026, featuring an even larger footprint (measured at ~5.5x reticle size CoWoS-L by our estimates) than we had previously thought, with compute chiplets built on TSMC 2nm. We have noticed more positive feedback by ODMs' clients on AMD's MI350/375 systems, and increasing ODM/component supplier interest after the partnership between OpenAI and AMD was announced in late 2025, but the CoWoS ordering momentum by AMD in 2026F turns out a bit softer than we had expected in December 2025. As the Asia AI supply chain is already busy preparing for nVidia Rubin and Google TPU, we observe that AMD might appear to be a lower priority and thus, AMD has fine-tuned its upstream demand forecasts in 2026F. That being said, our supply chain checks indicate AMD remains aggressive with 2027F planning, and could seek more CoWoS allocation at TSMC into 2027F. We project AMD's AI GPUs to contribute 9%/10% of TSMC's AI revenue in 2026F/27F. ·
• AWS Trainium: Compared to our AI logic semi model in December, AWS Trainium appears to be another victim in the supply chain suffering from the competition for strategic resources between nVidia and Google. We lower CoWoS capacity allocation assumptions of AWS Trainium in 2026-27F, and estimate AWS's Trainium contribution to TSMC's AI revenue pool to grow 13%/24% in 2026F/2027F (was 56%/14%). ·

Fig. 24: TSMC's CoWoS output breakdown

Source: Company data, Nomura estimates

Fig. 25: TSMC's CoWoS output allocation

Source: Company data, Nomura estimates

Google

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Fig. 26: TSMC's AI revenue breakdown

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— Google TPU contribution to Al revenue (RHS)

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Fig. 27: TSMC AI revenue mix by customer

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Source: Company data, Nomura estimates

Fig. 29: Google TPU's contribution to TSMC's AI revenue

Source: Company data, Nomura estimates

Fig. 31: AWS' contribution to TSMC's AI revenue

Source: Company data, Nomura estimates

Source: Company data, Nomura estimates

Fig. 28: nVidia's contribution to TSMC's AI revenue

Source: Company data, Nomura estimates

Fig. 30: AMD's contribution to TSMC's AI revenue

Source: Company data, Nomura estimates

novellee

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ower requiremen without redundancy

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Fig. 33: HBM base die contribution to TSMC's AI revenue

25 PFLOPS (inference)

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Source: Company data, Nomura estimates

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Fig. 34: Our take on the nVidia AI platform roadmap

Source: Company data, Nomura estimates

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Ph and CPO may kick in from C)

eat disapation a key issue for 1.6 Tbps N

Fig. 35: TSMC - AI revenue summary

Source: Company data, Nomura estimates

OSATs' CoWoS-like full processes could start emerging from 2027F

CPUs are low-hanging fruits to capitalize on

Venice and Vera CPUs are manifestations of OSATs monetizing alternative CoW opportunities

We first wrote about TSMC's prudent approach to CoW capacity expansion in our Asia AI Semi & Server Anchor report in August 2025 , and noted that such planning was critical for OSATs as it had driven most AI chip customers to look for alternative CoW suppliers, thereby benefiting ASE (see our upgrade report ). Amkor is also an alternate CoW partner, and management highlighted over a dozen 2.5D engagements (silicon interposer-based, as per Amkor's definition) and expected high-density fan-out RDL devices (i.e., organic interposer-based) ramping up production in 2026E and bridge-type solution for AMD in 2027E (see Amkor's Investor Day 2026 ). We compare major OSATs' advanced packaging platforms with TSMC's equivalent technologies in Fig. 36 , and observe that many 2.5D/molded interposer based packages in the pipeline of OSATs are for CPUs (Fig. 37 ). In our view, the wider RDL line/space and fewer RDL layers in CPU packages than AI accelerators could possibly relax some technological requirements for OSATs to participate in advanced packaging. Other than technology readiness, we believe another key factor hindering OSATs from engaging in CoW processes is the enormous losses that would be incurred if there were to be immature assembly yield. That, in our view, is the reason why the high-performance computing chips using OSATs' CoW to ramp up volume from 2H26F are mostly CPUs, which do not carry expensive HBM content.

We will discuss CPU architectures in detail in the section 'CPUs: different architectures & surging demand ' and focus on OSATs' advanced packaging capacity planning here. We estimate ASE could form 25kwpm of FOCoS capacity by end-2026F, from 5kwpm installed by end-2025. We believe the major consumption of ASE's FOCoS capacity will go to AMD's Venice CPUs in 2026-27F, which utilize ASE's FOCoS-B platform, and estimate USD350mn/1.4bn of revenue from this project for ASE in 2026F/27F, or 10%/20% of its leading-edge advanced packaging (LEAP) revenue. In our view, another organic interposer based package of significant volumes could be nVidia's Vera CPUs, which are assembled at TSMC (CoWoS-R) and Amkor (S-SWIFT). Our assumption is the TSMC track makes up c.40% of nVidia's Vera backend supply.

Fig. 36: 2.5D advanced packaging solution comparison

Source: Company data, Nomura research

Fig. 37: Major CoW projects at OSATs

Source: Company data, Nomura research

Fig. 38: Vera CPU packaged on TSMC CoWoS-R

Source: Company data, Nomura research

Fig. 39: Vera CPU packaged at Amkor S-SWIFT

Source: Company data, Nomura research

Die 1

Die 2

Intel's EMIB-T: major competitor to TSMC's advanced packaging

EMIB-T appears worth monitoring with increasing adoption

EMIB-T emerges as a 'must-succeed' alternative packaging solution for AI chips

We believe certain AI ASIC customers might have started evaluating Intel's EMIB-T as a logic+HBM integration alternative because of concerns about insufficient capacity support at TSMC. We think Google's potential reliance on Intel's EMIB-T for the next-generation TPU v9 (partnering with MediaTek) could be a critical litmus test for Intel's advanced packaging capabilities. Since 2017, Intel's EMIB has utilized silicon bridges buried in the build-up layers of an IC substrate to connect chiplets on top without any interposer (Fig. 40 ). Previously, in EMIB configuration, the I/O power delivery paths of top dies are cantilevered, and power from the substrate underneath had to traverse on the perimeter of the silicon bridge and across its thin metal layers to reach the microbumps. A longer routing distance, however, could cause intermediate resistance drop (IR drop) or lower actual voltage reaching transistors which adversely affected device functionality and performance. With the most advanced AI chips moving toward HBM4, power integrity becomes a more critical issue since HBM4 doubles the I/O bump density from HBM3E, operates at a higher current and is more sensitive to IR drop.

The new EMIB-T technology aims to incorporate through-silicon vias (TSVs) within the bridge die to create a vertical power delivery network, thereby shortening the routing distance to improve power delivery efficiency and performance (Fig. 41 ). According to Intel, EMIB-T targets HBM4/4E and logic chiplet interconnectivity with the lowest possible cost, and the company's roadmap is to scale to the integration of >8x reticle size total top silicon area on a ~120x120mm substrate by 2026E and >12x reticle size top silicon area on a >120x180mm substrate by 2028E (Fig. 42 ). In addition, the process flow of EMIB-T is not significantly different from the conventional EMIB, except that TSV bridge dies are placed into substrate cavities with a solder joint formation.

In our Greater China Semi Anchor Report , we highlighted Intel's strong commitment to leading substrate partners such as Ibiden (4062 JP, Buy), Unimicron, and Shinko (unlisted) to bring the EMIB-T technology into mass production, and leading substrate companies are expanding their capacities for Intel aggressively through co-investment. Nevertheless, Intel's experience of handling EMIB integration is largely grounded to internal products, with 12-14x silicon bridges in one package at max (Fig. 43 ). Our supply chain feedback indicates that the TPU v9 could have close to 30 silicon bridges buried in the large substrate, with potentially many silicon capacitors embedded as well. We believe the deviation of specs from the current AI/HPC substrate structure could lead to production yield challenges.

Fig. 40: An illustration of EMIB

-4x

Reticle size

EMIB power delivery path

2026

EMIB-T power delivery path

2028 +

Future

Fig. 41: EMIB-T shortens the power delivery routing distance to reduce IR drop

Source: Intel, Nomura research

Fig. 42: Intel's EMIB roadmap

Source: Intel, Nomura research

Fig. 43: Intel's internal products based on EMIB interconnects

Source: Company data, Nomura estimates

2026 NEPCON

15

Fig. 44: EMIB supply chain

Source: Company data, Nomura research

Interposer Size

• CoWos-S has been in production for over 10 years with interposer size up to 3.3-reticle cullergy can poorer

CoWos® Enables Al Compute Scaling

• World's largest 5.5-reticle size CoWoS in production with >98% yield in 2026

TSMC's countering measures: CoPoS and SoIC

A sneak peek into AI semi manufacturing chain in 2028F: it is all about execution 12 HBM3E/4

Admittedly, we do not have a clear picture about how TSMC would allocate its front-end and back-end capacity to AI customers in 2028F since the AI logic semi manufacturing chain dynamics remain fluid into 2028F, and TSMC's 'installed capacity' is not the only bottleneck. Key components and materials supporting TSMC's production turnkey such as IC substrates are also in short supply. Meanwhile, given constrained CoWoS supply at TSMC, Intel Foundry appears to be more aggressive targeting ASIC customers with alternative EMIB-T solutions to address the rather 'low-hanging fruit' compared to frontend wafers. Our view is that SoIC and CoPoS are two equally critical technologies for TSMC to stay ahead of its competition in advanced packaging, and below we provide a few topics worth monitoring. 12xHBM3E/4 2026

Could TSMC bring CoPoS online by 2028F?

TSMC showcased its production roadmap to 14x reticle size CoWoS by 2028E and >14x reticle size CoWoS in 2029E during the Technology Symposium (report ). Our back-ofthe-envelope calculation shows only one or two interposers output per CoWoS wafer when the CoW sizes are up to 14x reticle, making the economics a puzzle to us. Facing the challenge from alternative options like Intel's EMIB-T, we understand TSMC has the incentive to 'work very hard to meet all the demand' and 'not leave any business on the table', but apparently 'CoWoS' is not an economically viable solution at such a large CoW size. As such, we believe TSMC does have the motivation to get CoPoS ready earlier vs our prior projection of mass production in 2029F (report ) if TSMC's AI customers do not compromise their chip design floor plans. The current status of CoPoS is mini-line build-out by mid-2026F, and TSMC's management currently expects a volume ramp-up in two to three years from now. How quick can TSMC complete the development and turn that into high-volume production is noteworthy, in our view.

Fig. 45: TSMC's CoWoS roadmap laid out in 2025 Technology Symposium

Source: TSMC, Nomura research

Fig. 46: TSMC updates its CoWoS roadmap during the 2026 Technology Symposium

Source: TSMC, Nomura research

9.5-reticle

12xHBM4E

2027

14-reticle

2028

>14-reticle

24xHBMSE

2029

Fig. 47: Taiwan-based FOPLP equipment suppliers

Source: Company data, Nomura research

SoIC/3D stacking to be adopted in Feynman?

We believe the development of SoIC at TSMC is worth tracking and the company is committed to further shrinking bond pitches for logic devices, and is currently targeting N2-on-N2 with a 6um bond pitch to be in production in 2028E, and A14-on-A14 with a 4.5um bond pitch to be in production by 2029E (Fig. 50 ). TSMC has been producing N7on-N7 with a 9um bond pitch since 2023, and stacking with a 6um bond pitch has also been in volume production since 2025. The vertical logic stacking of SoIC theoretically could augment transistor counts per package, an outright indicator of computing power, without extra footprints (vs CoWoS/2.5D packaging that expands horizontally to accommodate more chips).

nVidia at GTC unveiled the plan to adopt 3D stacking starting from the Feynman platform (report ). Currently, AMD leads the adoption of SoIC at TSMC (starting from MI300series), and in the latest MI450, we believe AMD stacks four top dies (four XCD) on two reticle-sized active interposers (I/O dies), in which each top die scales to about 1/3 reticle size (Fig. 48 ). However, we are not sure whether nVidia will be more aggressive in chip specs by stacking a reticle-sized GPU die on top of another for the Feynman platform ( Fig. 49 ). Such a practice theoretically exacerbates thermal dissipation challenges and requires very high hybrid bonding yields. If nVidia and TSMC manage to overcome the design and manufacturing challenges, it might cement nVidia's AI computing performance dominance and possibly trigger an unprecedented AI industry scramble for SoIC capacity allocation at TSMC.

Apart from logic-on-logic stacking, TSMC's Compact Universal Photonic Engine (COUPE) could also serve as a key capacity driver, in our view, and the company is exploring DRAM-on-logic for high bandwidth and low latency for future AI inference decoding applications. TSMC has laid out the plan to grow SoIC capacity at a >90% CAGR over 2022-27E (report ). Our current assumption is that TSMC could install >40kwpm of SoIC capacity by end-2028F, from 5kwpm by end-2025.

Dummy

1/0

• Solc with 3D interconnect offers 56X interconnect density and 5X power-

HBM4

HBM4

10X

HBM4

5X

1/0

HBM4

Interconnect 10 Count

HBM4

Source: TSMC, Nomura research

HBM4

Dummy

1/0

HBM4E

HBM4E

IIMIALA

HBM4E

Source: Company data, Nomura research

Source: Company data, Nomura estimates

Fig. 50: TSMC's latest SoIC roadmap

Source: TSMC, Nomura research

HBM4E

HBM4E

HBM4E

10

2026F

2027F

•SoIC capacity (by year end, kwpm)

20+

40+

2028F

Source: Company data, Nomura estimates

larNe

SiC thermal solution is emerging because of SoIC

We observe that silicon carbide (SiC) is emerging as a highly thermal conductive material of interest due to even more stringent heat dissipation requirements for AI/HPC chips whose TDP skyrockets, noting that vertical stacking high-performance computing chips could exacerbate already concerning thermal management. SiC is a very competitive material, due to: 1) >3x higher thermal conductivity than silicon ; and 2) high mechanical strength, chemical stability, and durability in harsh operating environments, which SiC has demonstrated in power electronics applications like MOSFET and IGBT. More importantly, we believe SiC's cost structure has become more favorable than it was 5-6 years ago because of an industry-wide capacity expansion (notably in China).

In our Asia AI Thermal Anchor Report in October 2025 , we noted an application route of SiC in thermal management under study is the use of SiC to replace carrier silicon which are dummy dies bonded onto top logic dies to fill the structural void for better mechanical stability and prevent warpage of the entire complex during the assembly phase (see an example of carrier silicon in AMD MI300 in Fig. 52 ). As the passive die sits in the middle of the heat path from the heat source (processor die), to the thermal interface material (TIM1), and to the heat spreader, the substitution of silicon with SiC - whose thermal conductivity is much higher - could improve the heat dissipation efficiency. We see the SiC mechanical carrier potentially gaining traction on the back of its better thermal performance than current carrier silicon in tandem with broader adoption of TSMC's SoIC in coming years, since 3D stacking increases active silicon area and simultaneously power density in a given module footprint than sheer 2.5D/2D packaging. Manufacturing breakthroughs are nevertheless pending due to: 1) growth of large diameter SiC substrates (12') is more complicated and costly than 6' and 8' ones; and 2) although a dummy die is already simple per se, fabrication on brittle SiC wafers is more difficult than silicon wafers, along with other processing challenges.

We note that GWC has relevant SiC carrier solutions in the commercialization pipeline. Largan's (3008 TT, Buy) subsidiary, Taiwan Applied Crystal (TAC; unlisted), is also actively developing SiC chip-level thermal solution.

Fig. 52: Carrier silicon helps facilitate mechanical stability of the package, and material substitution with SiC might augment thermal performance

Source: AMD, Nomura research

IOD

XCD

CCD

CPUs: different architectures & surging demand Paradigm shift in CPU architectures

We understand that CPUs in AI servers are currently not included in the scope of TSMC's AI revenue, for which TSMC's chairman C.C. Wei shared in the April 2026 earnings call that '…it is not able to differentiate conventional server CPU vs AI server CPU ' yet, admitting that 'CPUs become more and more important in today's AI data center '. nVidia's CEO Jensen Huang at the COMPUTEX keynote speech this year also spent more time on Vera CPUs and mentioned that 'Agent is a new workload. We built CPUs for humans in the past. We need CPUs for agents, agentic systems. The properties are different - why would the old CPUs be the same? ' and '…This is the beginning of a new market, a market that never existed before! It is not going to take away from the old market, but this is a new market CPU for agents. This market will surely be larger than the last. '

We identified some interesting industry dynamics about CPUs in our August 2025 Anchor Report , including an accelerated share gain by ARM-based (ARM US, Not rated) CPUs from x86 CPUs and packaging technology changes in nVidia and AMD's next-generation server CPUs. Below we provide an update on nVidia and AMD's CPU hardware architecture.

• nVidia Vera: We previously believed Vera could utilize CoWoS-R (instead of FCBGA by Grace) to package one compute die, one I/O die and four memory interface chiplets on a 2.2x reticle-sized organic interposer. Our recent field trip to the COMPUTEX indicates the majority of Vera CPUs are packaged at Amkor's Korea facility using S-SWIFT (akin to CoWoS-R) and some at TSMC (CoWoS-R). nVidia's CEO Jensen Huang also discussed the shift in CPU requirements for agentic AI during his keynote speech, explaining that traditional CPUs are designed to maximize 'cores per socket' while Vera is specifically built for agentic AI to deliver 'low latency' (40% lower peak memory latency vs x86 CPU) and 'high memory bandwidth" (3x more bandwidth per core vs x86 CPU with DDR5) so as to direct workloads to GPUs and maximize AI factory outputs. nVidia emphasizes all 88 Olympus cores are in one monolithic compute mesh without 'chiplet tax' in core-tocore communication, and builds separate dies for memory controllers and I/Os to maximize the compute die area utilization for compute purposes. We think the chip design philosophy to offload memory controller blocks from the core compute complex may eventually become a common practice by ARM-based CPU designers and even AI accelerators (e.g., TPU v9 has independent memory fabrics, in our view; MediaTek has publicly illustrated such a concept, see Fig. 55 ) to leave the precious die area to core compute. ·
• AMD Venice: We previously believed AMD's Zen 6 'Venice' server CPUs could also utilize CoWoS-L to connect I/O dies (IODs) and core complex dies (CCDs). Our latest supply chain research suggests Venice will leverage ASE's FOCoS-B (akin to CoWoS-L) to package 2x IODs in the middle and 8x CCDs side by side on a c.2.9x reticle-sized reconstituted interposer. Based on AMD's decision to invest >USD10bn in Taiwan ecosystem (press release ), AMD is dedicated to developing 2.5D bridge interconnect technology 'embedded fan-out bridge (EFB)' in wafer form with ASE and in panel form with Powertech (6239 TT, Not rated). We reason localized high-density silicon bridges could increase die-to-die interconnect bandwidth at favorable economics, presenting a good balance for server-grade CPUs. We learned from SEMICON Taiwan that AMD's strategy is to reuse EFB IP in panel forms to ensure compatible design rules and seamless transition, and more importantly to localize high-bandwidth die-to-die interconnects to silicon bridges and relax line/space (L/S) requirements at panel-level RDL (report ). ·

We wrote in our December 2025 report that we observed that an increasing number of CSPs were developing their own ASIC CPUs for AI assistance purposes, in addition to the typical x86 CPU general servers. The trend does not recess at this moment (and likely will not), and we are witnessing more complicated chip layouts in the pipeline.

• Google Axion: We had flagged demand upside from Axion N4A (on TSMC 3nm; codenamed 'Cypress') to the Asia supply chain in August and December last year, as well as possible elimination of CPU sockets, potential upgrades in PCB/CCL, and potential market share reshuffle between ODMs. As the CPUs in the latest TPU 8t/8i racks shift from x86 to Google Axion, we believe the strength of this project is ·

manifested by those supply chain names including GUC (3443 TT, Neutral) and EMC. The current Google Axion C4A and N4A are still monolithic design, but our industry checks suggest the next generation may be a dual-die configuration, still utilizing FCBGA package, for releases in 2028F.

• AWS Graviton: AWS Graviton is the ASIC CPU of the largest volume, accounting for the majority of AWS' general server demand, based on our supply chain observations. Designed by Annapurna Labs under AWS with production turnkey completely handled internally, Graviton is now in the fifth generation. In the first two models, AWS opted for monolithic die layouts, while starting from Graviton 3, the floor plan has shifted to chiplet designs and the backend integration (of Graviton 3/4) is allegedly facilitated by Intel Foundry amongst the first-wave EMIB offerings to external customers as former CEO Pat Gelsinger's initiative. Specifically in Graviton 3/4, we notice the attempts by AWS to pull memory controller PHY and I/O blocks out from the compute complex and make them independent chiplets, and unsurprisingly such layouts should reserve as many die areas as possible for more intensive compute workloads over time. Nonetheless, in the latest Graviton 5, AWS appears to consolidate those chiplets back into the compute SoC. As such, we suspect the logic density of each individual silicon might be compromised, likely leading to a subpar transistor density vs TSMC's regular N3P for HPC applications, and supposedly this may explain why AWS has to integrate four identical chips on the substrate for Graviton 5 in order to make up for the performance shortfall in one single die. In addition, we observe Graviton 5 could have not considered Intel's EMIB scheme and embrace FCBGA package at Amkor (Korea factory). The modification might be reasonable and more economical particularly against the backdrop of substrate shortage and further embedding yield scrap from EMIB substrate production, in our view. ·
• Microsoft Cobalt: Following the introduction of Cobalt 100 in 2024, Microsoft unveiled its 132-core Cobalt 200 (based on TSMC 3nm) in 2025. We believe GUC is the design service partner for both Cobalt 100 and 200, in charge of supply chain logistics and expect it to stay involved in the next generation ASIC CPU. Cobalt 200 physically differs from its predecessor with a chiplet-based layout, and our survey suggests this could be assembled using Amkor's S-SWIFT. However, we believe Microsoft's Cobalt CPU volume might still be negligible in the supply chain at this moment. ·
• Arm AGI: Arm delivered its first silicon, 136-core AGI CPU (on TSMC 3nm), in March 2026, and we believe Arm is working with its design service partner Socionext (6526 JP, Neutral) on the project. The CPU places 2x half reticle-sized chiplets on a substrate using FCBGA, based on our observation. Arm recently also confirmed its CPU collaboration with Oracle (ORCL US, Not rated) and ByteDance (unlisted) in addition to the lead customer Meta and OpenAI. According to Arm's management, the follow-on AGI CPU 2 is slated for release in 2027E with AGI CPU 3 development already underway. ·

CCD

CCD

CCD

CCD

Axion Next

Olympus core

Fig. 53: An overview of CPU layout

1/0

Graviton 5

Grace

Vera

CCD CCD

CCD

CCD

I/O

CCD

CCD

VO

CCD

CCD

Venice

Turin

N4A

C4A

Graviton 4

Graviton 3

hlt 00

Cobalt 100

AGII

Source: Company data, Nomura estimates

Fig. 54: Select CPU specs overview

Source: TrendForce, Nomura research

Fig. 55: Offloading memory controller interface blocks to chiplets

Memory

I/O

Source: MediaTek, Nomura research

We would also like to temporarily move away the scope of AI/servers to highlight some intriguing changes in client CPUs.

• nVidia DGX/RTX Spark: One new (yet somewhat well anticipated) announcement by nVidia during COMPUTEX was the launch of RTX Spark. We believe RTX Spark and DGX Spark launched last year share the same chip, codenamed GB10. The chip packages 1x Blackwell RTX die and 1x Grace ARM-based CPU die together. MediaTek is responsible for custom CPU design to earn royalty charges, and our observation at the COMPUTEX affirms our view that the chip assembly is carried out by Amkor's Korea factory based on S-SWIFT (akin to CoWoS-R). Our unit build assumption is 1mn/2mn in 2026F/27F. ·
• AMD's next-gen CPU "Medusa": Our supply chain checks indicate AMD's Zen 6 client CPU "Medusa" might embrace chip-last FOPLP package at Powertech, while the predecessor "Strix (Zen 5)" is assembled based on TSMC's chip-first InFO-oS to house 2x CCD and 1x IOD (where GPU and NPU are). Apart from TSMC's capacity constraints, our best guess of the packaging technology change reason is similar to Apple's (AAPL US, Not rated) application processor migration to chip-last WMCM from chip-first InFO-PoP to enable potentially more RDL layers at finer L/S (report ). ·

Boom in Agentic AI leads to unexpected CPU demand

Since 2H25, there have been growing discussions about server CPUs, and we also observe CPU shortage, alongside some crowding out of capacity for PC/SP applications, as reflected in Intel and AMD's business results. In this section, we describe some trends in server CPUs and quote industry-leading players' comments, while providing more details in the Appendix: other critical developments and key quotes from major server CPU players .

Server CPU covers plain CPU for non-AI general servers, head-node CPUs paired with accelerators, and CPUs used for AI workloads (but not with accelerators). We believe the second and third categories are driving substantial demand for server CPUs, especially the last one after Agentic AI boom. Along with the prosperity, major players in the field also provide encouraging TAM forecasts (Fig. 57 ). Notably, AMD in May-26 doubled its server CPU TAM forecast from USD60bn in Nov-24 to USD120bn+ by 2030E; nVidia and Qualcomm (QCOM US, Not rated) both look for USD200bn.

uru demand lo booming.hom sevelal all gies, unvel bout anelly of maneully by ri

AI PHASE

CONVERSATIONAL AI

REASONING AI

CPU cores will also increase

Fig. 56: Agentic AI is driving server CPU demand

AGENTIC AI

• Infrastructure-wide orchestration

Source: Qualcomm, Nomura research

Fig. 57: Server CPU TAM forecast by major players

Company Server CPU TAM forecasts

Arm

When we look at what's going on with agentic AI, the growth of CPUs, the benefit that power-efficient CPUs bring in the data center, we think this represents about a USD100 billion TAM for us in the future. (Rene Haas, Arm Everywhere 2026)

AMD

nVidia

Based on the demand signals we are seeing today and the structural increase in CPU compute requirements driven by agentic AI, we now expect the server CPU TAM to grow at greater than 35% annually, reaching over USD120 billion by 2030. (Lisa Su, 1Q26 Earnings Call)

Vera CPU opens a brand-new USD200 billion TAM for nVidia, a market we have never addressed before, and every major hyperscale and system maker is partnering with us to get it deployed. We have visibility to nearly USD20 billion in total CPU revenue this year, setting us up to become the world's leading CPU supplier. (Jensen Huang, 1Q27 Earnings Call)

Qualcomm USD200bn by FY29 (Tony Pialis, 2026 investor day)

Source: Company data, Nomura research

Fig. 58: The growing importance of server CPU

CPU demand is booming…from several angles, driven both directly or indirectly by AI

Source: Company data, Nomura research

CPU in AI head node to pair with GPU - the CPU:xPU ratio is increasing

The headnode CPU amount paired with accelerators has been widely discussed after Google released its latest TPU v8t/v8i in late April 2026. The company specially mentioned that it has doubled the CPU usage per server, and it has increased adoption of in-house Axion CPUs; previous this was usually paired with x86 CPUs. nVidia has also gradually increased its CPU:GPU ratios from Hopper to the current Blackwell/Rubin architecture.

WATTS

PHYSICAL AI

data hall is increasing

The amount of CPU volumes/racks in the

cavela

UrUs

Blackwell

Ultra GPU

nuull or us ull a compute tay

Jupiter Network

Grace CPU

Grace CPU

ur uo t ta nuvill or us ull a bullpule lay our us vel solvel will - nou ur

ca vola

Up to PCle Gen6 x16

Up to PCle Gen5 x16

Up to PCle Gen5 x4

Blackwell

Distributed

Global WAN

Blackwell

Blackwell

Google unveiled v8 TPUs in Apr-26 with 2x usage of CPUs:

Gen6 x16

M.2

• 'We doubled the physical CPU hosts per server, moving to our custom Axion Armbased CPUs.' (Amin Vahdat, Google) · B3240 DPU (E-W) Supports breakout 2x400Gb/s

(N-S)

• Previous generations: 4 TPUs paired with 1 x86 CPU ·

NVMe

NVMe

NVMe

TPU 8t racks

• From v8i & v8t gen: 4 TPUs paired with 2 Axion CPUs ·

ICI (inter-Chip Interconnect)/ SPOCS

multi-datacenter sites

Expandable to

Data center building

nVidia has also increased its CPU:GPU ratio over time:

• HGX/Hopper: 8 GPUs per server with 2 x86 CPUs ·
• Blackwell & Rubin/Oberon: 2x Grace CPUs + 4x Blackwell GPUs or 2x Vera CPUs + 4x Rubin GPUs on a compute tray ·
• Rubin Ultra/Kyber: 2x Vera CPUs + 4x Rubin Ultra GPUs on a compute blade ·

Fig. 59: TPU 8t rack level connectivity

4 TPUs paired with 2 Axion CPUs

Source: Company data, Nomura research

Fig. 61: Blackwell compute tray logical design

2x Grace CPUs + 4x Blackwell GPUs or 2x Vera CPUs

Fig. 60: H100 data-network configuration

8GPUs per server with 2 x86 CPUs

Source: Company data, Nomura research

Fig. 62: Rubin Ultra compute blade

2x Vera CPUs + 4x Rubin Ultra GPUs on a compute blade

Source: Company data, Nomura research

Fig. 63: Rubin compute tray

2x Vera CPUs + 4x Rubin GPUs on a compute tray

Source: nVidia, Nomura research

Source: Company data, Nomura research

Fig. 64: Rubin compute tray

2x Vera CPUs + 4x Rubin GPUs on a compute tray

Source: nVidia, Nomura research

B3240

DPU

(N-S)

2x400Gb/s DPU for storage network and usericontro

management plane

Storage

NSwitch

NVSwitch

PCle local storage

• Winke

Vera Rubin compute blade

CPU

DGX H100: DATA-NETWORK

CONFIGURATION

Full-BW Intra-Server NVLink

NVIDIA Vera - CPU for the Age of Al

• All 8 GPUs can simultaneously saturate

1e Nyanks to oter Orus wiunin serve

• Limited only by over-subscription from multiple other Crus

Half-BW NVLink Network

• All 8 GPUs can half-subscribe 18 NVLinks o GPus in other serven

• 4 GPUs can saturate 18 NVLinks to GPUs in other servers

• Equivalent of full-BW on AllReduce with SHARP

• Reduction in AlIZAIl BW is a balance with server complexity and costs

Multi-Rail InfiniBand/Ethernet

• All 8 GPUs can independently RDMA data over its own dedicated 400 Gb/s HCA/NIC

800 GBos of aggregate full-duple o non-NVLink Network devic

Vera BlueFie

Storage

Grace

NSwitch

8155 55555

DGX H100

CPU volumes/racks in data halls increasing

From another perspective, CPUs' growth may not necessarily come from increasing the ratio of CPUs to accelerator, as the structure is also limited to overall server design and shall consider physical area within a tray and thermal/power relevant issues. Instead, we may see more CPU racks within a data center campus to operate workloads such as orchestration and management. As mentioned in the above section, this could be partially evidenced in nVidia's grand launch of standalone Vera CPU rack in 2026 GTC in Mar-2026, and the longer time nVidia's CEO Jensen Huang spent on CPUs during its GTC Taipei Keynote in June 2026. The company also disclosed CPU revenue visibility of USD20bn during its earnings call in May 2026.

nVidia announced standalone Vera CPU rack in 2026 GTC

• 'This is the Vera system, twice the performance per watt of any CPUs in the world today. It is also in production. Well, we never thought we would be selling CPU stand-alone. We are selling a lot of CPU stand-alone. This is already, for sure, going to be a multibillion-dollar business for us. So I'm very, very pleased with our CPU architects. ' (Jensen Huang, nVidia) ·
• 'Vera CPU opens a brand-new 200 billion TAM for NVIDIA a market we have never addressed before. And every major hyperscale and system maker is partnering with us to get it deployed. We have visibility to nearly $20 billion in total CPU revenue this year, setting us up to become the world's leading CPU supplier .' (Colette Kress, nVidia) ·
• 'We're going to need a lot more CPUs, and Vera was designed to be an agentic CPU. The CPUs of the past were designed to have many cores so that it could be easily rentable. People rent at cores. Well, agents don't rent cores. They just want the work to be done fast. The economics of the past was dollars per core. That's the economics of cloud computing of the past. The economics of the AI of the future is tokens per dollar or dollars per token. And so what we need to do in the future is to generate tokens, process tokens as fast as possible, and that's what Vera does incredibly well.' (Jensen Huang, nVidia) ·

Arm shared the view of more CPUs inside a data hall and mentioned nVidia's standalone Vera CPU racks in May 2026.

• ' T he ratios are going to change from a CPU core count, maybe not a chip count. Where we'll see the growth, in my opinion, is not so much in the head node to a GPU architecture because that's a little bit fixed given the way the GPU is architected and how it feeds to CPU. But will you see many, many more CPUs inside a data hall, dedicated racks of CPUs that are doing Agentic orchestration and scheduling and management, 100%. You simply just have to look at NVIDIA announcing a dedicated Vera rack, 256 Vera CPU chips, 88 cores per chip and a 200-kilowatt liquid-cooled rack that is designed to sit in a data center adjacent to a Vera Rubin system. And that's simply because of the size of the system, it's liquid cooled. So imagine a world where you had scores of Vera Rubin racks, now you may actually have a Vera rack in between or 2 Vera racks. So that changes the ratios completely. ' (Rene Haas, Arm) ·

Fig. 65: Standalone Vera CPU rack

Source: Company data, Nomura research

Fig. 66: Vera CPUs on compute tray, CPU tray, and storage tray

Source: nVidia, Nomura research

NVIDIA Vera - CPU for the Age of Al

Vera BlueFiel

Storage

70

60

50

40

30

20

10

Growing CPU demand directly enlarges BMC TAM

Following the wave of agentic AI, we see ASPEED as a clear beneficiary of the booming CPU trend. ASPEED saw strong demand from AI-related general server for agentic AI workload and simple inference tasks, and the company separated the category in its latest forecasts in Mar-26. We observe that ASPEED's customers continue to ask for more, reflecting in its growing backlog into 2027F.

Fig. 67: ASPEED's BMC TAM forecast

ASPEED saw strong demand from AI-related general server

• 2026 2027 2028

BMC for General Server

• BMC for Al-related General Server

2029

• BMC for GPU Server

2030

• BMC for AI ASIC Server

Source: Company data, Nomura research

Server forecast updates

We forecast TSMC's CoWoS capacity to grow by over 80% in 2027F, but…

We believe TSMC could expand its CoWoS capacity to c.2mn wafers in 2027F from c.1.1mn in 2026F, which implies 80%+ y-y growth, likely due to rising AI capex commitments from CSPs, neoclouds, sovereign AIs, AI GPUs and ASIC makers, as well as potential competition from Intel's EMIB-T.

... we conservatively factor in 60-65% growth for its 2027F CoWoS output in our server forecasts, given unprecedented mismatch of component supply

However, we are also experiencing unprecedented supply mismatch in various components (including but not limited to the well-known shortage of memory and CPUs), even before the full-scale ramp-up of Rubin and Trainium 3 - which are the most important new AI server platforms in 2026F - from late-3Q26F. We are concerned that the broad-based component shortage situation will deteriorate in 2H26F and 2027F, and such supply chain imbalance will likely cap the growth rate of servers (as well as all the other electronic products) in 2027F and beyond. Hence, we conservatively apply a 10% discount to the CoWoS output (i.e., around 1.8mn wafers, 60-65% y-y growth) for 2027F , and we need to closely monitor the impact of shortage issues.

Deteriorating structural shortages in 2027-28F, with risk of paradigm shifts in 2028F or beyond

In our view, there are several structural challenges to AI server supply chain in 2027-28F.

Unprecedented component shortages

Given the 2-3-year market view of a 60-80% CAGR for AI servers, a 20-30% CAGR for CPU/general servers (a new market view from early-2026), and a 30-50% CAGR for networking switches, the scope and magnitude of component shortage in the tech universe this time is unprecedented, as most of the capacity planned in late-2025 didn't fully consider the additional growth from CPU servers and networking on top of AI GPU/ASICs, and suppliers also tend to discount the growth target from AI customers.

We believe the broad-based component shortage is going to increasingly squeeze non-AI tech products (e.g., consumer products), and even other sectors, including automotive and industrial sectors, from 2H26F to 2027-28F. In addition to the well-known memory and CPU shortage, PCB/CCL, IC substrate, higher-end capacitors, power ICs, optical components, and various other components are already in shortage at this moment, and supply is going to deteriorate further.

The challenges to ease the shortage are: 1) we note the expansion magnitudes of leading component players are usually by a CAGR of 30-50% during 2026-27F. In 2026-1H27F, the most timely capacity expansion will mostly come from brownfield sites left from the prior bull cycle, which already have buildings and infrastructure. After the brownfield sites are used up, to build large-scale greenfield capacity (building everything from scratch) normally take 1.5-2.5 years, depending on industry difference, but the lead times for most equipment tools are lengthened at this moment, prolonging the greenfields' lead time in general to two years or more. This is why we may rarely see component makers easily 'double' their capacity output for AI in 2027F. 2) Materials, materials' materials, and even the key components to make equipment tools are also getting tight or already in shortage . As these upstream material or key component makers are usually serving a wide range of industries, not just the technology sector, they may not fully understand the urgency of capacity expansion of their customers or the AI industry, and their expansion lead time is usually longer than downstream components. 3) Many component suppliers switch/convert capacity from other applications to AI-use to fulfill immediate demand growth from AI. Although we believe this has been the case since 2025 and non-AI demand (e.g., smartphone and PC) indeed looks weak in 2026-27F, the conversion will accelerate in 2H26-27F, squeezing consumer products and even automotive and industrial sectors severely.

Potential breakthroughs in physical walls representing higher risks of technology changes and paradigm shifts for 2028F and beyond

We sense 2028F will be the next technological leap for AI server technologies, after the leap in 2H24-2025 (e.g., nVidia's Oberon architecture for GB200/300, VR200). The

current AI platforms in 2025-26F are mostly based on existing technologies, but by 2028F, based on most AI GPU/TPU players' roadmaps, the new-generation AI platforms by that time will need various breakthroughs in physical limits in technologies and materials to achieve those upgrades.

For example, we believe faster connectivity, e.g., SerDes to 336G or 448G, will be one of the top challenges in next-gen AI beyond 2027F. Even if the chipsets are ready, the peripheral components in the system also need to be upgraded and re-designed thoroughly to accommodate the faster speed, in our view. For PCB/CCL , while M9Q/M10Q, PTFE , or other CCL materials which can support lower signal losses will be required, those materials (e.g., Q glass, and PTFE) are mostly not proven for PCB mass production yet. HDI PCB which has features of shorter circuit routing and lower losses, will likely be increasingly considered vs the current high-layer-count (HLC) PCB, but the manufacturing processes of HDI, which require laser drilling and processes for finer pitch line space/line width, are more expensive and require new investments of equipment for HLC makers to convert to HDI. Not to mention, using HDI to process new materials, e.g., Q glass, PTFE, will likely require new kinds of laser drilling equipment tools (e.g., picosecond green or femtosecond IR lasers ) than current mainstream CO2 lasers.

Copper vs optical transmission : In our view, the necessity of using optical transmission for scale-up is getting higher and higher, because the faster interconnect to 336G and 448G in the future will be close to the limits of copper wiring and the shorter transmission distance of copper wires under such high speed will be against the trends of developing larger scale-up AI clusters. Meanwhile, the upgrades to optical scale-up can somehow improve the performance of AI server platforms, enabling them to serve as a back-up if other required new technologies for new AI architectures fail to break through in time. For example, nVidia is likely developing CPO/near-packaged optics (NPO) to help performance upgrades for its next-gen Rubin Ultra under the current Oberon architecture, if the new Kyber architecture is not ready in time for Rubin Ultra in 2H27F. For Kyber (likely in 2028F for Feynman), CPO/NPO can also serve as a more powerful scale-up technology for larger and higher-density AI server clusters. However, CPO technology still has a lot of challenges in mass-volume, fully automated production and testing processes. We believe before CPO technology gets more mature for mass volume applications, alternative transitional technologies, such as NPO, Extra-dense pluggable optics (XPO), and co-packaged copper (CPC) , will likely be considered in 2027-28F. However, in our view, given the high uncertainties (e.g., various different designs, processes, unclear scale/timing and sustainability) of those new technologies, it is challenging for investors to identify clear winners in this early stage, and it is also difficult for companies to make investment decisions, if the processes are not fixed and scale is undefined. And, we believe there could be higher risks in the medium term (e.g., 3-5 years) to the investments related to transitional technologies, like CPC, XPO, and NPO , given that CPO could be the ultimate solution in the end. In the longer run (e.g., 5-7 years), the PCB-based system architectures will likely need to be scrutinized, if optical I/O (OIO) can be materialized, in our view .

Copper-based connectivity technologies (e.g., direct attach cable [DAC], active electrical cable [AEC], CPC, PCB, and various connectors) also continue to upgrade to cope with faster transmission speed and lower loss requirements, as they are still the more cost-effective, and energy-efficient solutions vs optical solutions, if they can achieve the requirements.

In advanced packaging, we believe in order to achieve higher performance and larger size requirements, various new technologies, such as EMIB-T and GPU-on-GPU SoIC , etc., are required for the next-next gen GPU (e.g., Feynman likely needs SoIC) and TPU (v9 needs EMIB-T) in 2028F. For the longer term, we believe technologies such as CoPoS and glass-core/ceramic-core substrates will also be discussed in 2029-31F. More powerful ICs will likely require more powerful thermal solutions, including MCL, vapor chamber lid (VC lid), SiC, etc. (refer to our Anchor report published in October 25). We have discussed in detail about the challenges for those new technologies in the prior sections.

We believe all these new technological developments show rising risk to investments and execution in 2028F or beyond, given the potential technology shifts. We think it will be a dilemma for companies to invest in some 'transitional' technologies. It will also be a dilemma for investors to invest based on either a 1-2year view (mostly very profitable based on existing or transitional technologies) or

on 3-5-year potential (likely based on unproven technologies with high risk of paradigm shifts), in our view.

In 2027F, nVidia and Google to continue as winners of CoWoS allocations, with Google's share incrementally up the most

As mentioned earlier, we forecast TSMC's CoWoS output to grow to 1.8mn wafers (vs capacity of 2mn units) in 2027F, up from c.1.1mn in 2026F. Within the 1.8mn output in 2027F, we assume that nVidia will get around 54-56% (vs 2026F of 56-58%), Google (Broadcom+Mediatek) c.27% (2026F: c.20%), AMD (including Xilinx) 8-9% (2026F: 78%), and AWS (including Al chip and others) 5-6% (2026F: 6-7%). We expect Google' s share to expand from 20% in 2026F to 27% in 2027F, growing the most y-y.

nVidia upstream: keeping mid-50s share in CoWoS, with mix shifting to Rubin/Rubin Ultra in 2027F

We assume nVidia's CoWoS capacity allocation at TSMC will increase, from 350370kpcs in 2025E and 620-640kpcs in 2026E, to 980-1,030Kpcs in 2027F , and its mix will change from Blackwell (60-62%), Rubin (33-35%), and Vera (4-5%) in 2026F, to c.90% for Rubin and Rubin Ultra and 8% for Vera.

Although there were HBM4 issues and heat spreader design changes for Rubin earlier this year, we believe those bottlenecks have been largely resolved, with certain compromises in performance (e.g., Rubin likely to achieve 1,800W in 2H26F, but not 2,300W, the over-clock performance). We think nVidia will ramp up Rubin rapidly in late-3Q-4Q26F (we assume c.2mn units of Rubin in 2026F , vs our prior assumption of 2.5mn units made in December 2025); at the same time, nVidia will keep doing more optimisations or system design changes in order to drive higher performance, but we think that will only materialize in early 2027F on an upgraded system version of Rubin or by mid-2027F on Rubin Ultra.

We assume Rubin Ultra, the majority of which will be 2-GPU per CoWoS package version, similar to Rubin, will ramp up production from mid-2027F . Given the similarity of package design and system architecture , we expect the transition to Rubin Ultra will likely be smooth and quick, just like GB200 to GB300, except for the uncertain readiness of CPO/NPO scale-up connectivity for Oberon, which could be an optional version if the technology is not mature enough.

nVidia downstream: raising our NVL72 rack shipment estimate to 54.5k (from 50k) for 2026F, and introducing our forecast of 62k for 2027F

For 2026F, considering rising capex guidance from top US CSPs YTD and increase in neoclouds, we raise our GB/VR rack shipment assumption from 50k units to 54.5k units for 2026F (see Fig. 69 ). Of this, we assume VR200 to account for 15-20% in 2026F, with concentration in 4Q26F . We assume a transition from GB300 to VR200 during late-2Q26F to 3Q26F, as top CSPs will likely prefer to wait for VR200, instead of continuing to install more GB300s. In the transitional period, we expect neoclouds to play a bigger role to buy more systems to support the continued token demand growth in AI companies.

We also introduce our forecast of 62k racks for 2027F , with a potential transition from Rubin to Rubin Ultra happening in 2Q27F.

Our HGX vs GB/VR mix assumption for nVidia modules has some swings this time. We change our HGX:GB/VR mix assumption for 2026F to 30%/70% , vs our previous estimate of 18%/82%. Because nVidia needs to produce more Blackwell GPUs against the backdrop of lowered Rubin shipments in 2026F caused by above-mentioned bottlenecks, in order to consume all the promised CoWoS from TSMC, we think HGX type offers better flexibility to consume the excess Blackwell GPUs to smaller customers. However, for 2027F, our HGX/VR mix assumption is now 20%/80%, as we think VR200 demand will outpace supply in the initial stage.

18

16

14

12

10

8

6

4

2

0

16

16

16

Fig. 68: Our quarterly forecasts for GB/VR rack shipments

12

0.7 0.7

Source: Nomura estimates

AMD: rising traction recently in MI455

We currently assume AMD's CoWoS volume (including Xilinx) would grow c.80% y-y in 2027 , with its share in our covered company TSMC's CoWoS slightly up to 8-9% in 2027F, from 7-8% in 2026F. We notice that AMD's top customers for MI455 are OpenAI (through Oracle and Microsoft), Meta, Anthropic, and several neoclouds . MI455 will be the first rack-level system of AMD, similar to nVidia's Oberon. The leading NPI ODM of MI455 is Sanmina (SANM US, Not rated), which bought ZT systems (unlisted; mainly rack and cluster engineering team and manufacturing) from AMD in October 2025. Although we have not heard or seen records of severe bottlenecks of MI455 so far and AMD's public announcements all show optimistic progress on the project, we think whether the severe mismatches of component supply could impact AMD's production ramp-up in 2H26 remains noteworthy, in our view.

Google's TPU: growing the fastest in 2027F

We assume TSMC's CoWoS allocation to Google's TPUs (through Broadcom and MediaTek) would increase over 115% y-y to 480kpcs in 2027F (our assumption factors in Google's internal use as well as external customers) . We estimate the split between Broadcom and MediaTek would be roughly 66-68:32-34 in 2027F.

However, the largest debate in TPU is its roadmap in 2028 and beyond. TPU v9 (code name A5922), led by MediaTek and based on Intel's EMIB-T package, is scheduled to have its first tape-out by end-2026E, which could be the first reality check on the timing of the new EMIB-T technology.

On the other side, Broadcom's TPU v8i (Sunfish) has been pushed out to late-2026E (from originally 3Q26); the next-gen TPU from Broadcom would be a combination of two v8i TPUs in one multi-chip module (MCM) package, likely codenamed Whalefish, and might come onstream in late-2027E, according to management. We think the relative positioning of TPU v9 and Whalefish in Google's TPU roadmap for its internal use or for external demand in 2028F will likely depend on the progress of EMIB-T, which is still unclear at this moment .

We notice that Broadcom has partnered with Apollo Global Management (APO US, Not rated) and Blackstone (BX US, Not rated) to launch the AI XPV platform in June 2026 ( press ), backed by a monumental USD35bn in initial financing. This strategic alliance aims to deliver over 20GW of AI computing capacity through 2028 to support leading AI research labs, including OpenAI and Anthropic. Specifically, the initial funding will directly fuel Anthropic's AI infrastructure expansion, enabling it to deploy over 1GW of computing infrastructure starting in mid-2026. Simply assuming 1,000W TDP for TPUs/ASICs, 20GW could translate to 7mn+ units of TPUs, equivalent to 360-460k CoWoS demand. The vendor-backed financing phenomenon somewhat enhances our confidence, as Broadcom leverages its own robust balance sheet to backstop (offering residual value guarantees) massive infrastructure loans for these LLM makers.

1212

12

Raising 2026-27F server market forecasts, with stronger AI and general/CPU servers

Compared with our forecasts in December , the demand outlook for AI token growth is now more robust, and the development of agentic AI is also accelerating CPU server growth in AI inference. As such, we raise our global AI server revenue estimate by 12% for 2026F, and the new forecast represents 78% revenue growth in 2026F (vs 58% previously) for AI servers, led by stronger demand and higher ASPs from component cost inflation. In this report, we also introduce our 2027F AI server revenue growth forecast of 76%, similar to the 2026F level, in which our AI server unit growth forecast is at 43% (slower than 67% in 2026F), with the rest coming from cost inflation.

We also raise our general/CPU server forecasts substantially, lifting unit/revenue by 14%/48% for 2026F. After the revisions, we now forecast general/CPU servers to grow by 31% in units (vs prior 15%) in 2026F and 26% in units in 2027F , from an estimated 19% growth in 2025F. To reflect rising costs, especially that of memory, we assume the ASPs of general/CPU servers would also increase by 28% in 2026F and 13% in 2027F. All in, our general/CPU server revenue forecasts are growth of 67% in 2026 and 43% in 2027F. We provide a detailed discussion about CPU server market demand for AI inference and comments from top AI and chipset companies in other section of this report (please see Appendix: other critical developments and key quotes from major server CPU players ).

Therefore, we now forecast global server revenue growth of 74%/65% y-y in 2026F/2027F (Fig. 69 ) (vs 53%/43% y-y in 2025F/26F previously), with the AI server revenue growth rate at 78%/76% y-y in 2026F/2027F (previously 76%/58% y-y for 2025F/26F) and general/CPU server revenue growth rate at 27%/67%/43% y-y in 2026F/2027F (previously 23%/16% y-y for 2025F/26F).

Fig. 71 , Fig. 72 , and Fig. 73 suggest that our latest 2027 forecast for AI server sales would eventually translate into upside to current consensus forecast on hyperscaler capex, regardless of hyperscalers' FCF into 2027 (Fig. 75 ).

Fig. 69: Our assumptions of global server market and nVidia's AI GPU supply and demand

Old forecast

(Dec 2025)

2026F

15,600

2,446

18,046

121,720

299,907

421,627

15%

61%

19%

16%

58%

43%

Overall server market

General/CPU server units (k)

AI server units (k)

Total server units (k)

General/CPU server revenue (US$mn)

AI server revenue (US$mn)

Total server revenue (US$mn)

y-y (%)

General/CPU server units (k)

AI server units (k)

Total server units y-y (%)

General/CPU server revenue (US$mn)

AI server revenue (US$mn)

Total server revenue (US$mn)

Source: IDC, company data, Nomura estimates

2024

11,444

877

12,321

85,037

107,476

192,513

9%

130%

13%

11%

182%

68%

Current forecast

2025

13,600

1,475

15,075

107,895

188,206

296,101

19%

68%

22%

27%

75%

54%

2026F

17,820

2,462

20,282

180,680

335,049

515,728

31%

67%

35%

67%

78%

74%

2027F

22,490

3,523

26,013

258,772

590,571

849,343

26%

43%

28%

43%

76%

65%

Change

2026F

14%

1%

12%

48%

12%

22%

(USDbn)

1,000

900

800

700

600

500

400

300

200

100

72%

80%

Fig. 70: Server supply chain

2023

У-у

90%

80%

70%

60%

50%

(USDbn)

600

500

400

у-У

160%

140%

120%

100%

+147bn

180%

160%

140%

120%

Source: Company data, Nomura research

Fig. 71: Top-5 CSP capex consensus

Source: Bloomberg Finance L.P., Nomura research

142%

+168n

+153bn

(USDbn)

700

600

500

400

Fig. 72: nVidia's data center sales consensus

Source: Bloomberg Finance L.P., Nomura research

182%

+256bn

Fig. 73: Our AI server revenue forecasts

Source: Nomura estimates

1,200

1,000

800

600

400

200

0

Fig. 74: US top CSPs' capital spending

Source: Company data, Bloomberg Finance L.P., Nomura research

Fig. 75: Top 5 Hyperscalers' FCF, based on consensus capex from Fig. 71

Source: Bloomberg Finance L.P., Nomura research

(%)

6.5

6

5.5

12,000

4

3.5

10,000

3

2.5

2

8,000

1.5

2024

6,000

4,000

2,000

Nov-20

30yr cash bonds - OIS

More datapoints supporting a stronger 2027

Swaps richen

Our refreshed data center tracking analysis

It's all about Al indicated increasing Al hardware demand

across 2026-2030F, but still a stronger

We would be buyers on

2027F than 2026F with a better mic weakness for the rest of 2024

(vs. most of the time through

2023 our stance being active

60

buyers)

Source: Nomura research

Nomura strategist Naka Matsuzawa recently provided a somewhat contrarian macro view in a 19 June report : regarding interest rates and rate hikes, the market currently expects about 1.5 US rate hikes before year-end followed by cuts, whereas the median FOMC dot plot projects one "insurance" hike in 2026 and one cut each in 2027 and 2028, moving toward a 3.1% neutral rate. However, our strategist expects the Fed to keep rates unchanged in 2026 and warns that AI-driven economic acceleration could force the Fed into a normal tightening cycle, turning precautionary insurance hikes into earnest, consecutive rate increases. In terms of yields, current US two-year real yields are near 2.00%, and if the Fed proceeds with earnest hikes of at least 100bp, 10-year Treasury yields would likely far exceed 5.00% ; as expectations emerge for a global economic recovery, which is a major contender for the next market theme, yields will face upward pressure globally, but differences in fiscal and monetary policy stances across countries should be reflected in the extent of yield increases and the shape of yield curves. Yield curves in the US and Europe would likely bear flatten, while Japan's yield curve would bear steepen. Additionally, the Fed projects the US unemployment rate at 4.3% for both 2026 and 2027, and 4.2% in 2028, indicating that FOMC members are largely unconcerned about economic or inflation overheating.

Source: Bloomberg Finance L.P., Nomura

Al risk partly priced in, but macro risks rising

The new risk is macro, while valuation constraints

aluv

(bp)

250

2022: Likely a strong beginning.

5-30yr spread

A typical downturn framework

Appendix: Reference charts

Valuations may be to April/May earnings season,

Fig. 76: Look back our thoughts over past several years

but soft ending

(bp)

120

(%)|

2.8

2.6

2.4

2.2

2

1.8

1.6

1.4

1.2

0.8

0.6

0.4

(%)|

4.4

Fig. 78: G3 policy rate expectations

-26/212|

(%)

3.2

3

Note: OIS forward rates for each maturity. Source: Bloomberg Finance L.P, Nomura

US

Europe

Appendix: other critical developments and key quotes from major server CPU players

CPU cores within single CPU chip will also increase

Arm believes the increased CPU increased demand could be reflected in more CPU cores within one chip, rather than in chip volume. As well, more cores inside the silicon is driving up CPU ASP. Intel has also witnessed a significant core count increase.

• 'We are seeing literally not only an explosion of CPU demand, but one of the areas that we're seeing growth in terms of CPU is number of cores per CPU.' (Rene Haas, Arm) ·
• 'Maybe a more straightforward way to think about it is each of these agents are running a batch or running a job themselves. There is certainly a level of complexity in terms of the way the branch prediction coding is handled and essentially the way you would code the example. But if you just think about the nature of an asynchronous workload for an agent, it runs a job, it does some scheduling, it stops, it waits, it pauses. It's actually pretty good for a single core design to handle that as opposed to having multi-cores having to run that all together in unison. It's going to be more power efficient if you run it through a single core. And the more cores you have, in theory, the more batches you can run. So our viewpoint is very much one of more cores is better. And that's why I think you're going to see increasingly larger core counts in these CPU chips. So you'll see more CPUs cores being shipped. TAM, whatever the number is, largely, it's going to be driven by the fact that these CPU chips are going to have lots of CPU cores, which will drive ASP up. But I think it' s a per core best job, not multiple instructions across multiple cores.' (Rene Haas, Arm) ·
• 'Obviously, core count is increasing significantly in the data center CPU space.' (David Zinsner, Intel) ·

More players actively joining the field

We have seen more engagement between large names in the CPU world. Meta is aggressively sourcing CPUs from third parties such as AWS and Arm. Qualcomm was once a fabless company specializing in smartphone/mobile chips. It tried to break into datacenter areas through its AI200/AI250 accelerators in Oct-2025. Further, it announced that the company had developed a dedicated agentic CPU in Apr-2026, founded on its expertise in consumer SoCs. Another remarkable move, in our view, is Arm venturing into providing chips, from selling silicon IPs in Mar-2026. Its first product - Arm AGI CPU for datacenters - is anchoring key clients such as Meta and Open-AI, and the company has already announced there will be iterative development of the product in its multigenerational roadmap.

Meta signed an agreement with AWS to power agentic AI on Amazon's Graviton chips (Apr-2026)

• 'The deployment starts with tens of millions of Graviton cores, with the flexibility to expand as Meta's AI capabilities grow. The deal reflects a shift in how AI infrastructure gets built: while GPUs remain essential for training large models, the rise of agentic AI is creating massive demand for CPU-intensive workloads - realtime reasoning, code generation, search, and orchestrating multi-step tasks.' (Amazon) ·

Qualcomm is developing a dedicated CPU for agentic experiences in the data center, and will provide more details in June (Apr-2026)

• 'Agent orchestration is predominantly CPU- bound and Qualcomm has the world's best-performing CPU across smartphones, PCs, auto and soon the data center.' (Cristiano Amon, Qualcomm) ·
• Qualcomm and Meta announced a strategic multi-generation agreement on data center CPUs on June 2026. The C1000 CPU is planned to power Meta's nextgeneration server fleet, underscoring the growing importance of high-performance, power-efficient compute in large-scale scale-out environments. ·

Multi-generation portfolio with hyperscaler wins

Support for air- and liquid-cooled rack offerings

Agentic CPU

Hieh throughput for

Al use cases

INTRODUCING

Qualcomm

Dragonfly

C1000 CPU

Source: Qualcomm, Nomura research

Fig. 80: Qualcomm's C1000 CPU

i oldency

Source: Qualcomm, Nomura research

Arm announced an AGI CPU in its ARM Everywhere event (Mar-2026)

• 'These agentic workloads require CPUs to coordinate tasks, move data, manage memory, enforce security and orchestrate workaround accelerators. As Agentic AI scales, data centers will require more than 4x today's CPU capacity, creating a data center CPU market opportunity of more than $100 billion by 2030 .' (Rene Haas, Arm) ·
• Raised the revenue guidance from USD1bn in Mar-26 to USD2bn in May-26: 'Customer response to the Arm AGI CPU has been very strong. We now have more than USD2bn in customer demand across fiscal 2027 and fiscal 2028. This is more than double what we stated at launch.' (Rene Haas, Arm) ·

Key comments from Intel and AMD

As Intel and AMD are two dominant players in server CPUs, their comments on CPUs are critical for monitoring technical trends and supply/demand status. Both companies emphasized the growing importance of CPUs in a datacenter, commenting on higher CPU to GPU ratios, and AMD particularly raised CPU TAM from USD60bn in Nov-24 to USD120bn+ by 2030 in May-26.

Intel:

• 'In recent months, we have seen clear signs that the CPU is reinserting itself as the indispensable foundation of the AI era. CPU now serves as the orchestration layer and critical control plane for the entire AI stack.' ·
• ' The most important is the reinforced learning, the orchestration of all the different agents and then also the optimizing for some of the workload and CPU is even more important. ' ○
• 'The backbone of AI computing in production remain a CPU anchored architecture. That is good news for the x86 ecosystem.' ·
• CPU to GPU ratio: ·
• 'Customers are deploying server CPUs along accelerators in the ratio that is moving back towards CPU.' ○
• ' If you look at training solutions, they're generally running in the kind of 7 to 8 GPUs to 1 CPU. ' ○
• ' As we look into inference, it's probably getting into like the 3 to 4:1 kind of level. And as you get into agentic and multi-agent, it's one potentially even flip in the other direction a little bit. Inference side, I think in terms of orchestration, control plane and also managing all the different agent with data, CPU is much more efficient. So I think the ratio of CPU to GPU used to be 1 and 8, and now it's 1:4 and I think towards parity or even better. So I think the demand is very strong. ' ○
• ' And now even some of them tell me it's 4:1. So 4 CPU to 1 GPU, so the inference and agent. ' ○
• ' Our outlook for server CPU demand has improved over the last 90 days, and we expect a strong year of double-digit unit growth for the industry and for us with momentum extending into 2027. ' ·
• Unit vs ASP: 'We think the unit volume is going to be the biggest driver. Now that's on an ASP per core basis. Obviously, core count is increasing significantly in the data center CPU space. As core count increases, we get the lift on the ASPs from that, and that obviously is meaningful. ' ○

CPU TAM BY FY29

Gon7: X. connectivit

AMD:

• Raised server CPU TAM forecast from USD60bn in Nov-24 to USD120bn+ by 2030E in May-26 ·

○

• ' W e outlined the server CPU market growing at approximately 18% annually over the next 3 to 5 years. Based on the demand signals we are seeing today and the structural increase in CPU compute requirements driven by Agentic AI, we now expect the server CPU TAM to grow at greater than 35% annually, reaching over $120 billion by 2030. '
• ' O ver the last few months, as we've talked to our customers and we've seen how AI adoption is really unfolding, we're seeing significant more CPU demand from really every major cloud provider as well as enterprise customers. And the way that comes across is as AI adoption scales, you need more inferencing. As inferencing scales and you have more agents and Agentic AI, they all require CPUs for all of the orchestration and the data processing and these other tasks. ' ○
• Three categorizes to drive TAM upward revision: ○
• General purpose compute TAM: increasing at low double digits ○
• Head nodes that really support the AI accelerators: also growing but smalle ○
• CPUs just for all of the Agentic AI work: really stemming from all of the Agentic processes. ○
• ' W hat we see going forward is as core counts increase, obviously, we will see ASP increase. And that's the direction that we're going in as we go forward. But the largest portion of this is the Agentic AI, the CPUs that are serving these Agentic AI workloads in terms of the TAM increase.'

○

• Competition: ' I think you're going to see people actually use x86 and ARM for many of the large hyperscalers. And even for those who are developing their own, they're still buying lots of CPUs in the merchant market for the reason that I just stated, which is unique different CPUs for the different types of workloads, and there's very high demand at the moment. ' ·
• CPU function ·
• ' A s AI adoption scales, demand is increasing, not only for accelerators, but also for the high-performance CPUs that power and orchestrate those workloads. ' ○
• ' Inferencing and Agentic AI are increasing the need for server CPU compute as these workloads require additional CPU processing for orchestration, data movement and parallel execution in addition to serving as the head nodes for GPUs and accelerators. As a result, we are seeing both stronger near-term demand and deeper engagement with customers on long-term capacity planning. ○
• Agentic CPU growth is additive to AI TAM (not at the expense of GPU) ·
• ' I t's largely additive to the TAM. So you should think about we need all of the accelerators to run these foundational models, and then as these agents do work, they spawn more CPU tasks. So I would say largely incremental. The key is to make sure -- what we're seeing is in these deployments, the key is to make sure the ratio of CPUs to GPUs are the right ratio. So if you're installing a gigawatt of compute, there's a percentage of CPU as part of that gigawatt will increase. ' ○
• CPU to GPU ratio: ' W e certainly see the movement towards where in the past, the CPU to GPU ratio was primarily just as a host node in like a 1:4 or 1:8 configuration node, now changing and getting closer to a 1:1 configuration or even -- you can even imagine if you get lots and lots of agents that you could have more CPUs and GPUs. ·
• ' T he key is that everyone is now planning and thinking about CPUs at the same time that they're thinking about their accelerator deployments, which is a good thing. ' ○
• ' T he good thing about this is we're now talking about '27 CPU demand, we're talking about '28 CPU demand. And so that allows us to just plan much better as we go forward. ·

Appendix: CSP comments on AI and investments

Fig. 81: Microsoft's relevant comments on AI business/investments

Source: Company data, Nomura research

Fig. 82: Alphabet's relevant comments on AI business/investments

Fig. 83: Amazon's relevant comments on AI business/investments

Source: Company data, Nomura research

Fig. 84: Meta's relevant comments on AI business/investments

Source: Company data, Nomura research

Fig. 85: Oracle's relevant comments on AI business/investments

Source: Company data, Nomura research

Relative performance chart

2330 TT

EQUITY: FOUNDRY

Price

•115

-110

• 105

Taiwan Semiconductor Manufacturing Corp 2330.TW

2330 TT

EQUITY: FOUNDRY

Courna: | CEC Namiira

Earnings uptrend sustains; Buy with a higher TP

Turning aggressive on CoW plan (despite bottleneck in WoS); price hike scale and scope noteworthy

AI demand surge (unsurprisingly) changes TSMC's mindset about expansion

We keep the AI bellwether TSMC in our core AI semi holding. We expect TSMC to deliver strong revenue growth in 2026F/27F (+37%/+30%, in USD terms), monetizing full fab loadings and another round of price hikes (assume for wafer-outs starting in Jan-27). While we previously expected a severely constrained Asia AI semi and server supply chain throughout 2026F (report ), the scope of supply/demand mismatch has broadened (report ). We believe TSMC will be more aggressive than before in capacity builds, and we believe it targets 2,000kpcs CoWoS in 2027F (more precisely, 'CoW' capacity; vs. our previous estimate of up to 1,350kpcs) by hastening its tooling pace in AP7/AP8. The pace of advanced node (N5/N3) supply addition in 2026-27E, on the other hand, remains broadly steady with the planned N3 builds at Fab 18 and cross-node optimization at Fab 15/18, while the majority of greenfield formations will come online after 2027E (N3 in the US/Japan). Yet we only model in 1,800kpcs of 'CoWoS' output since turnkey volume could be constrained by key components in the WoS stage such as IC substrates, suggesting TSMC cannot be the only one 'working hard' to meet the demand . While keeping 2026F capex unchanged, we raise 2027F/28F capex to USD75bn/85bn (from USD70bn/70bn) but note possible upside (current capex intensity is in the low-30% vs. prior cyclical peak 45-50%) to counter competition (e.g. Intel's EMIB-T) and considering an optically high ROI in this AI-driven cycle. The increased capex in 2027-28F, in our view, is to expedite infrastructure and subsequent tool purchases. We expect 5-10% price hikes for N2/N3/N5 into 2027F, and we do not rule out further upside in scale and scope, i.e. even mature nodes could see price hikes into 2027F. Net, we raise 2026-28F GM to reflect stronger pricing power and a more favorable mix from hectic AI/HPC production and increase 2026-28F EPS by 4-12%. Our new TP of TWD3,425 is based on 25x 2027F EPS of TWD137.0 (previously 25x 2026-27F average EPS TWD112), near the high end of its historical trading band of 10-30x. TSMC trades at 17x 2027F EPS. After SOX's rally in April and May, TSMC local shares (P/E based on Bloomberg consensus EPS) are trading at a 16% discount to SOX's one-year forward P/E (25x; based on consensus). We reiterate Buy as we believe TSMC should trade at a premium to SOX due to its AI-enabler position and strengthened growth outlook.

2Q26F results/3Q26 guidance preview

We model TSMC's 2Q26F revenue growth/GM both at the high end of guidance (+12% q-q in USD terms; GM of 67.4%) and expect another +12% q-q growth in 3Q26F revenue with a 68% GM.

Source: Company data, Nomura estimates

May

(TWD)

2500-

2250-

20001

17501

15001

12501

10001

Global Markets Research 30 June 2026

Relative performance chart

Source: LSEG, Nomura

Research Analysts

Semiconductor

Aaron Jeng, CFA - NITB aaron.jeng@nomura.com +886(2) 21769962

Eric Chen, CFA - NITB

eric.chen@nomura.com +886(2) 21769965

Vivian Yang - NITB

vivian.yang@nomura.com +886(2) 21769970

Key data on Taiwan Semiconductor Manufacturing Corp

Cashflow statement (TWDmn)

Source: Company data, Nomura estimates

Performance

Income statement (TWDmn)

Source: Company data, Nomura estimates

Company profile

Founded in 1987, Taiwan Semiconductor Manufacturing Corp. is a leading foundry player with the most advanced process technology.

Valuation Methodology

Our TP of TWD3,425 is based on 25x 2027F EPS. Our target P/E is at the higher end of historical range. The benchmark index for the stock is Taiwan TAIEX and SOX.

Risks that may impede the achievement of the target price

Major downside risks are: 1) top-down macro issues because of US-China trade tensions; 2) weaker-than-expected sell-through compared with strong demand in the supply chain; 3) slower-than-expected technology migration; and 4) stronger-than-expected competition in advanced 5/3nm nodes.

ESG

TSMC officially sets 'Acting with Integrity', 'Strengthening Environmental Protection', and 'Caring for the Disadvantaged' as its primary ESG mission.

Financial analysis and forecasts

Fig. 86: TSMC - 2026-28F forecast revisions

Source: Nomura estimates

Fig. 87: TSMC's P&L

Source: Company data, Nomura estimates

Fig. 88: Nomura forecasts vs Bloomberg consensus for 2026-28F

Source: Bloomberg Finance L.P. consensus, Nomura estimates

Fig. 89: TSMC's consensus P/E ratio

Fig. 91: TSMC — valuation vs. SOX Index

30

35

25

28

21

20

14

15

7

10

5

Чиід,

0

Jun-21

50%

40%

Fig. 90: TSMC's consensus P/B ratio

Fig. 92: TSMC — valuation vs. TSMC'S ADR

8.0

35

7.0

Valuation methodology and risks

We raise our TP to TWD3,425, which is based on 25x 2027F EPS of TWD137. Our target P/E multiple is at the higher end of TSMC's historical range of 10-30x. The stock is currently trading at 17x 2027F EPS. -20%

Major downside risks: 1) top-down macro issues owing to the ongoing US-China trade tensions; 2) weaker-than-expected sell-through compared with the strong demand in the supply chain; 3) slower-than-expected technology migration; and 4) stronger-thanexpected competition in advanced 5/3nm nodes. - BEst P/Bk Jun-23 +1SD: 6.0x Jun-24 Average: 4.9x - TSMC (2330 TT) BEst P/E (LHS)

-SOX Index BEst P/E (LHS)

Source: Bloomberg Finance LP, Nomura research

Fig. 91: TSMC - valuation vs. SOX Index

Source: Bloomberg Finance LP, Nomura research

TSMC (TSM US) BEst P/E (LHS)

25%

20%

15%

10%

5%

0%

-5%

Jun-25

Jun-26

-1SD: 3.8x

Source: Bloomberg Finance LP, Nomura research

Source: Bloomberg Finance LP, Nomura research

2,400

2,100

1,800

1,500

1,200

900

600

300

0

Jun-21

180

Fig. 93: TSMC's share price vs Bloomberg consensus EPS revisions

Source: Company data, Bloomberg Finance L.P. consensus estimates, Nomura research

Relative performance chart

EQUITY: OSAT

Price

(TWD)

700 1

600-

500

400-

3001

2001

• 200

• 175

• 150

• 125

ASE Technology Holding 3711.TW 3711 TT

EQUITY: OSAT

Courna: | CEC Namiiral

Ongoing earnings upside; Buy and raise TP

TSMC's turning aggressive on CoWoS plan, CPU-driven FOCoS business upside, and further price hikes possible; Buy

Raise TP to TWD730 and maintain Buy, implying 16% upside

Along with our in-depth analysis of ASIC/CPUs and revised CoWoS forecasts in our AI Semi and Server Anchor report, we update our model assumptions for ASE Technology. As we believe TSMC has outsourced most of its oS business to ASE group, ASE should be a direct beneficiary of the revised expansion plan of TSMC. We believe the oS business will still contribute more than half of ASE's LEAP (leading-edge advanced packaging) revenue in FY26F/27F, accounting for 59%/51% of LEAP in these two years. However, we see clear upside potential for its full process platform as well. Also, in our AI Semi and Server Anchor report we provided a detailed analysis on AMD's (AMD US, Not rated) Venice CPU architecture, which we expect to be a major product utilizing ASE's FOCoS-B technology. According to our estimates, full-process could contribute 10%/20% of ASE's LEAP revenue in 2026F/27F. To sum up, we provide a simple simulation for ASE's LEAP revenue in Fig. 94 , where we suggest overall LEAP revenue to contribute USD3.5bn/6.9bn, accounting for 33%/41% of ASE's total IC ATM revenue (in USD terms) in 2026F/27F. Coupled with 0-5% y-y revenue growth for non-LEAP IC ATM revenue and 5-10% y-y growth for the EMS segment, we model ASE's total revenue to grow by 26%/19% in 2026F/27F and tentatively assume 15% y-y revenue growth in 2028F. We also expect margin expansion to continue on optimization of product portfolio and operating leverage, collectively contributing 12% of our 2027F EPS estimate hike. Our new TP of TWD730 is based on 25x 2027-28F average EPS (from 2027F EPS and TWD575 TP) and unchanged target P/E of 25x (at the high-end of its historical range). The stock currently trades at 21.7x 2027-28F average EPS. We maintain Buy rating.

Can the share price uptrend sustain?

In Oct-2025, we upgraded ASE from Neutral to Buy (report ), citing reasons such as share price underperformance (at that time), ASE becoming a prime gainer from TSMC's oS outsourcing, improving product mix and negotiation power. We maintain our positive view, given ASE's revenue, margin and capex growth acceleration (report ), and we also see consensus earnings estimate hikes over the past one year (Fig. 103 ). ASE share price has outperformed major indices and peers since Oct-25 (up 155% vs. TAIEX up 58%, Fig. 100 ), but we expect the stock to extend the rally on potential upside from its full process platform. We believe ASE is also at the forefront to gain from the value of latest technologies such as panel level packaging and CPO, which we believe are currently understated and difficult to quantify, but have significant upside potential.

Source: Company data, Nomura estimates

May

Global Markets Research 30 June 2026

Relative performance chart

Source: LSEG, Nomura

Research Analysts Semiconductor

Aaron Jeng, CFA - NITB aaron.jeng@nomura.com +886(2) 21769962

Donnie Teng - NIHK

donnie.teng@nomura.com +852 2252 1439

Vivian Yang - NITB vivian.yang@nomura.com

+886(2) 21769970

Eric Chen, CFA - NITB eric.chen@nomura.com

+886(2) 21769965

Key data on ASE Technology Holding

Cashflow statement (TWDmn)

Source: Company data, Nomura estimates

Performance

Income statement (TWDmn)

Source: Company data, Nomura estimates

Company profile

ASEH is one of the world's largest OSAT players. Established in 1984, ASE Group specialises in providing semiconductor packaging and testing services. In 2016, ASE Group and SPIL announced a merger and founded ASEH. Currently, ASEH's members include ASE Group, SPIL and USI.

Valuation Methodology

Our TP of TWD730.00 is based on 25x average 2027-28F EPS. Our target P/E of 25x is at the high-end of its historical range. The benchmark index for the stock is TWSE index.

Risks that may impede the achievement of the target price

Downside risks: 1) AI hardware chip demand sustainability; 2) ASE's execution on if they can deliver good-enough yield for CoW process.

ESG

ASEH manages its corporate social responsibility by focusing on six dimensions: stakeholder engagement, sustainability governance, green transformation, inclusive workspace, responsible procurement and corporate citizenship. The company sets water- saving milestones and establishes low-carbon plants in practice.

LEAP to drive revenue upside into 2027F along with a better margin profile

We provide a simple simulation of ASE's LEAP business: we assume the oS business to continue growing along with TSMC's CoWoS expansion plan, accounting for more than half of ASE's LEAP revenue in 2026-27F. Full process revenue will likely record strong growth momentum in conjunction with AMD's Venice CPU ramp-up. On the testing side, ASE is one of the key beneficiaries of TSMC's testing outsourcing activities, mainly on the CP part. We also believe ASE is providing FT services for some key ASICs.

We estimate LEAP revenue to grow from USD3.5 bn in 2026F to USD6.9 in 2027F. Given the LEAP business is margin-accretive, we expect continued margin expansion.

Fig. 94: ASE's LEAP revenue breakdown and forecasts

Note: *incorporates company guidelines

Source: Company data, Nomura estimates

8,000

7,000

6,000

5,000

4,000

3,000

2,000

1,000

-

Fig. 95: ASE's LEAP revenue

USDmn

MOS

Source: Company data, Nomura estimates

Financial analysis and forecasts

Fig. 97: ASE's 2026-27F forecast revisions

Source: Company data, Nomura estimates

Fig. 98: ASEH's P&L

Source: Company data, Nomura estimates

/0

mOS

Source: Company data, Nomura estimates

MUL

200%

34

29

150%

24

100%

19

50%

14

0%

9

4

Jun-21

-50%

Oct-25

7.5

6.5

Fig. 99: Nomura forecasts vs Bloomberg consensus for 2026-2028F

4.5

Source: Company data, Bloomberg consensus, Nomura estimates

Valuation methodology and risks

Our new TP of TWD730.00 is based on 25x average 2027-28F EPS. Our target P/E of 25x (unchanged) is at the high-end of its historical range.

Downside risks: 1) AI hardware chip demand sustainability; and 2) ASE's execution on if they can deliver good-enough yield for CoW process.

Source: Bloomberg Finance L.P., Nomura research

Fig. 101: ASEH's 5-year consensus P/E

Source: Bloomberg Finance L.P. consensus, Nomura research

Fig. 102: ASEH's 5-year consensus P/B

Source: Bloomberg Finance L.P. consensus, Nomura research

35

30

25

20

15

10

5

Jun-21

800

700

600

500

Source: Company data, Bloomberg Finance L.P., Nomura research

Fig. 103: ASEH's share price vs Bloomberg consensus EPS revisions

Relative performance chart

EQUITY: TECHNOLOGY

Price

(TWD)

20000 1

175001

15000-

12500-

10000-

7500-

5000 -

• 200

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-150

-125

ASPEED Technology 5274.TWO 5274 TT

EQUITY: TECHNOLOGY

Churra. I CEC Namura

Customer demand continues to rise; raise TP

Despite overbooking risks, demand continues to rise; we expect further earnings upside

Order outlook momentum continues; reiterate Buy

We raised our 2026F BMC (baseboard management controller) shipment estimate for ASPEED from 22mn in Dec-25 to 25-30mn in Mar-26 owing to the strong demand for both general servers and AI servers, and also our expectation of overbooking. Over the past three months, we continue to see upward revision in customer orders, as reflected in ASPEED's book-to-bill ratio (>2). The advent of agentic AI is driving a significant rise in CPU server demand. Although substrate constraint could potentially cap 3Q26F revenue upside (conservative guidance of TWD4.1-4.3bn vs. Bloomberg consensus at TWD4.3bn, we expect TWD4.7bn), we expect 4Q26F to record significant revenue growth q-q on improved supply with more OSAT vendors joining. We estimate total BMC shipments in 2026F to reach ~33mn. The order momentum should sustain into 2027F, based on our industry checks and ASPEED's comment about a huge backlog. We estimate total BMC shipments to experience another signifiant surge and reach 37mn in 2027F. We maintain our view that the strong booking may carry some underlying risk (i.e. correction). We believe the substantial order momentum could still include stockpiling amid a tight supply/cost inflationary environment, while it doesn't necessarily indicate customers are willing to slow down procurement anytime soon. We tentatively assume BMC shipments to plateau with a soft pullback in 2028F (we model 35mn). We raise 2026F/7F EPS by 22%/40%. Based on 50x 2028F EPS, our new TP is TWD19,100 (up from TWD11,500, based on 50x 2027F EPS). The 50x target multiple is at the midend of ASPEED's historical trading range). We reiterate Buy. The stock trades at 40.9x 2028F EPS. Our current EPS projections are on a pre-dilution basis, as we have not factored in 10% stock dividend (9%+ EPS dilution).

Product portfolio further expands content value per server

ASPEED showcased its latest product roadmap (Fig. 108 ) during 2026 Computex and unveiled AST1840 (Fig. 110 -Fig. 111 ), a brand-new chip combining BIC/SMC functions with embedded FPGA (procured from Lattice [LSCC US, NR]). The multi-function chip reduces design footprint, providing an attractive choice for customers who want to downsize PCB. ASPEED continues to expand its product offshoots in the core server market despite iterating existing product families, all leading to higher value content within one server. Therefore, even if the server market becomes saturated, ASPEED could still enjoy content value increase from mix optimization as well as to expand into adjacencies. We estimate ASPEED's total content value per server could reach 7-8x (if not higher) in AST2800 gen, vs. AST2500 gen (Fig. 112 ).

Source: Company data, Nomura estimates

May

Global Markets Research 30 June 2026

Relative performance chart

Source: LSEG, Nomura

Research Analysts

Semiconductor

Aaron Jeng, CFA - NITB aaron.jeng@nomura.com +886(2) 21769962

Vivian Yang - NITB

vivian.yang@nomura.com +886(2) 21769970

Eric Chen, CFA - NITB

eric.chen@nomura.com +886(2) 21769965

Key data on ASPEED Technology

Performance

Income statement (TWDmn)