報告_OCP2026_Google_Microsoft_Meta_單相冷板極限_20261015

PDF 原檔：報告_OCP2026_Google_Microsoft_Meta_單相冷板極限_20261015_original.pdf

講者公開簡報（OCP 官方 Recorded Content 頁提供下載）。文字以 PyMuPDF 逐頁抽取，### p<n> 為頁碼；圖表內容見原檔。

圖片清單（已驗證 2026-10-19）

原始內容

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Moderator: Joel Chakkalakal Director of Business Development, Shield by Guardian Panelists: Remco van Erp Co-Founder & CEO, Corintis Yin Hang Technical Lead Thermal Engineer, Meta Oscar Farias Moguel Principal Thermal Engineer, Microsoft Weihua Tang Technical Lead Manager, Google Cloud Pushing the Single-Phase Cold Plate Limit: Design Practice, Field Learnings, and the Runway Before Two-Phase Scales AI OPEN DATA CENTER

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Panel Discussion Joel Chakkalakal Director of Business Development Guardian- Moderator Oscar Farias Moguel Principal Thermal Engineer, Microsoft-Panelist Yin Hang Technical Lead Thermal Engineer, Meta Platforms-Panelist WeiHua Tang Technical Lead Manager, Google Cloud Remco van Erp Co-Founder & CEO, Corintis-Panelist

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Moderator Joel Chakkalakal Director of Business Development, Shield by Guardian — Moderator As a Lean Six Sigma Master Black Belt, Joel builds end-to-end solutions that help data center operators take operational risk out of their critical infrastructure. At Shield by Guardian — the data center services division of Guardian — he works with hyperscale and enterprise clients on the testing, maintenance, and fluid management programs behind high-density liquid-cooled deployments. Joel earned his Master’s in Supply Chain Management from the University of Houston after completing his Bachelor’s in Marketing at the University of Texas. His experience spans prestigious brands including AWS, Meta, Formula 1 Racing, and Coca-Cola, where he led cross-functional teams and spearheaded initiatives to overhaul complex operating systems — 180 process optimization projects that saved his clients over $1.8B.

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Panelists Remco van Erp Co-Founder & CEO, Corintis Remco van Erp is co-founder and CEO of Corintis, a provider of liquid cooling solutions for data center applications. Remco received B.S. and M.S. degrees in mechanical engineering from the Eindhoven University of Technology, Eindhoven, The Netherlands, and holds a Ph.D. in microsystems and microelectronics from the École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland.

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Panelists Yin Hang Technical Lead Thermal Engineer, Meta Platforms Yin Hang is a technical lead thermal engineer at Meta Platforms Infrastructure Foundation team, where she develops thermal solutions for IT hardware, specializing in advanced cooling solutions for Meta’s in-house accelerators. Yin earned her PhD from Purdue University.

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Panelists Oscar Farias Moguel Principal Thermal Engineer, Microsoft Oscar Farias Moguel is a Principal Thermal Engineer at Microsoft, where he focuses on technology pathfinding for next-generation cloud and AI infrastructure. As part of the Systems Planning and Architecture (SPARC) organization, he works on evaluating and maturing advanced cooling technologies for future datacenter applications, helping bridge the gap between emerging innovations and hyper- scale deployments. Oscar holds a PhD in Mechanical Engineering from The University of Sheffield, UK.

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Panelists Weihua Tang Technical Lead Manager, Google Cloud Weihua Tang is a Technical Lead Manager at Google Cloud, where she develops thermal solutions for IT hardware, specializing in optimizing cooling technologies for data centers. Prior to Google, she dedicated 14 years to Intel, focusing on processor testing, packaging development, and thermal-mechanical architecture for platform systems. Weihua holds 12 US patents. Weihua earned her PhD in Mechanical Engineering from the University of Minnesota and holds master’s and bachelor’s degrees in Heating, Air Conditioning and Gas Engineering from Tongji University in Shanghai, China.

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Pushing the Single-Phase Cold Plate Limit: A unitary approach COOLING: COLD PLATE Oscar Farias Moguel Principal Thermal Engineer Systems Planning and Architecture (SPARC)

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Single-Phase Cold Plate: Current Challenge Processor architectures complexity is increasing Traditional cold plates rely on a monolithic fin bank, resulting in significant fluid temperature rise and pressure drop. 3D renders created with Microsoft Copilot. Not representative of any product or roadmap.

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Single-Phase Cold Plate: Optimization Opportunities Plot 1. Nusselt number along the axis direction in a rectangular duct (one heated plus 3 adiabatic walls) Upon the entrance region in a fin bank, there is a ~1 mm in length that will have a 150x higher Nu ≈ 6x more HTC. Is this enough to mitigate large hot spots? We think so! Volumetric impingement Developing boundary layers Developed boundary layers Entrance region Fin bank Optimization avenues for a cold plate unitary cell: Entrance region: • No caloric gain • Impingement effect • Boundary layer development Fin bank: • Smaller feature size • Boundary layer disruption 10 mm 10 mm HTC map of an optimized unitary cell Anatomy of a cold plate unitary cell

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Single-Phase Cold Plate: Optimization Tests Cold plate prototypes based on a unitary cell approach, as testing lead by Microsoft SPARC Up to 10C junction temperature reduction was measured Small form factor evaluation Representative form factor evaluation with a partner company (future processor architecture)

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Fluid allocation adjustment Single-Phase Cold Plate: Unitary Cell Methodology Unitary cell distribution optimization DOE A cold plate using a unitary cell design philosophy can cool the hotspots below the desired target. Traditional cold plate cannot provide enough cooling. All hotspots overheat. Hypothetical processor heat flux distribution 10% 10% 20% 20% 60% 60% 140% 140% 130% 130% 120% 120% 140% 140% 130% 130% 120% 120% 140% 140% 130% 130% 120% 120% 140% 140% 130% 130% 120% 120% 140% 140% 130% 130% 120% 120% 10% 10% 20% 20% 60% 60% 140% 140% 130% 130% 120% 120% 100% Monolithic fin bank Monolithic fin bank

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Remco van Erp Co-founder & CEO - Corintis Microfluidic cores: chip-specific liquid cooling to advance cold plate performance Cooling

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Chips are heterogeneous - cooling isn’t Confidential 1 4 Non-uniform power Hotspots concentrate in a fraction of the die area Non-uniform conduction 3D chip stacks move heat at very different rates Non-uniform limits ASIC and memory tolerate different peak temperatures Chips are not a uniform heat source – Cooling needs to match what happens in the package

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Microfluidic core Confid 15 October 15, 2026 CHIP-SPECIFIC THERMAL COMPONENTS TO INCREASE SINGLE-PHASE COLD PLATE PERFORMANCE 10–20% lower temperature Co-designed with the chip Mass-production technology Compatible with existing supply chain Single-phase drop-in solution 01 02 03 04 05 MICRO FLUIDIC CO RE CHIP

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Experimental results on NVIDIA H200 GPU Confidential 16 32.4°C 23.9°C 42.0°C 29.5°C HBM GPU HBM GPU Junction-to-inlet temperature rise °C · NVIDIA H200 at 1 LPM · lower is better SKIVED COLD PLATE MICROFLUIDIC COLD PLATE −19% Same coolant, same 1 LPM flow, same test rig. −23%

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ACTION Fast & accurate simulation tools based on interoperable standards and cooling design optimization algorithms to increase performance within short cycle times. DESIGN/SIMULATION 1 Focus area 1: Design & simulation tools CHALLENGE Product cycles are extremely short, but it can take 12+ hours to simulate cold plates, making manual cooling optimization impractical. OCP workstream: Cold Plate Performance Package model (ECXML) Chip Inputs Temperature targets Power maps Facility inputs Pressure drop/flow rate Filtration What we do: Glacierware

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ACTION Alternative scalable manufacturing methods, such as additive manufacturing, to unlock complex geometries that improve cold plate performance MANUFACTURING 2 Focus area 2: Advanced manufacturing OCP workstream: Cold Plate Performance CHALLENGE Cold plates today rely on skiving, which is mature, but limits design freedom to straight fins. Channel and fin width: <100 µm Large design freedom in 3D Volume: Millions/year What we do: Core Foundry

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ACTION High-resolution silicon thermal test vehicles that enable rapid & representative early-stage performance validation. TEST & VALIDATION 3 Focus area 3: High resolution test vehicles CHALLENGE Chip designers don’t have access to real silicon until late-stage product development, so testing occurs on uniform copper cartridge heaters. OCP workstream: Cold Plate Performance 2 kW 240 channel power supply Silicon TTV 2x2 mm pixels What we do: Therminator

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Weihua Tang Thermal Systems Technical Lead Manager, Google PANEL DISCUSSION | Cooling Environments — Cold Plate Track • OCP Global Summit 2026 Pushing the Single-Phase Cold Plate Limit Design Practice, Field Learnings, and the Runway COOLING: COLD PLATE

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Scaling Single-Phase Cold Plates: Design & Thermal Actions CHALLENGE: SYSTEM INTEGRATION & HYDRAULIC LIMITS • Higher power, dense keep-out zones, and strict height limits drive high rack coolant flow and pressure drop toward connector limits. • Higher coolant flow yields diminishing cooling gains while causing a steep surge in pumping power. ACTION: SILICON & COLD PLATE CO-DESIGN • Co-architect the silicon floorplan, chip package, and cold plate hydraulics together. • Split incoming coolant into short parallel micro-fin sections and tailor local fin geometry, channel depth, and targeted coolant flow to the chip heat map. Ironwood 4-Chip Liquid-Cooled Tray Source: Google Cloud, Hot Chips 2025 Split-Flow Microchannel Cold Plate Cross- Section Source: Google, Hot Chips 2025 Liquid Cooling Tutorial Split-Flow vs. Straight-Through Rca vs. Flow (GPM) Source: Google, Hot Chips 2025 Liquid Cooling Tutorial

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Scaling Single-Phase Cold Plates: Design & Thermal Actions CHALLENGE: THERMAL INTERFACE, WARPAGE & HOTSPOT SPREADING • Refining micro-fins alone yields minimal chip temperature reduction without lower interface resistance. • Extreme localized hotspot heat flux overwhelms the lateral heat-spreading capacity of solid copper. ACTION: THERMAL INTERFACE STACK & COMPOSITE BASES • Prioritize resistance reduction across Thermal Interface Materials — where a large share of the thermal budget is lost. • Integrate high-conductivity composite baseplates with higher thermal conductivity than pure copper. Spring-Loaded Direct-to-Die Parallel Cold Plate Loop Source: Google, Hot Chips 2025 Liquid Cooling Tutorial

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Scaling Single-Phase Cold Plates: Operations & Material Actions CHALLENGE: DEPLOYMENT & OPERATIONAL CHALLENGES • Microchannel debris lodges inside ultra-fine microchannels. • Leak-sensor reliability issues and heterogeneous rack deployment. • Secondary-side cooling system fluid chemistry management. ACTION: GALVANIC CHEMISTRY, FILTRATION & LOOP GOVERNANCE • Standardize durable coatings to raise safe erosion-corrosion velocity limits. • Multi-tenant rack hydraulic impedance matching and field- hardened leak sensor qualification. • Enforce water quality and corrosion inhibitors paired with fine rack filtration. Multi-Rack CDU & Parallel Rack Manifold Loop Source: Google Cloud, Hot Chips 2025 Tutorial Quick-Disconnect Couplings & Flexible Hoses Source: Google, Hot Chips 2025 Liquid Cooling Tutorial Custom 'Feeder Kit' Filtration & Purging Cart Source: Google, Hot Chips 2025 Liquid Cooling Tutorial

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Scaling Single-Phase Cold Plates: Operations & Material Actions CHALLENGE: SUPPLY CHAIN & MANUFACTURING TRADE-OFFS • Pure Copper Supply & Cost Volatility. • Ultra-Fine Fin Skiving & Yield Risk. • Multi-Vendor & Material Qualification. ACTION: ALTERNATIVE MATERIAL SYSTEMS (BEYOND PURE COPPER) • High-temperature engineered polymers that eliminate galvanic corrosion and cut copper mass. • Standardized testing for long-term creep, glycol aging, and seal integrity on alternative materials. Multi-Supplier Cold Plate & CDU Supply Chain Source: Google, Hot Chips 2025 Liquid Cooling Tutorial Google’s contribution to a an open specification for a liquid cooled rack Source: Google, Hot Chips 2025 (datacenters.lbl.gov)

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Pushing the Single-Phase Cold Plate Limit COOLING: COLD PLATE Yin Hang Thermal Engineer, Meta

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Cooling is NOT an one-dimensional problem Confidential 2 6 Z stackup Power components

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Cold Plate is NOT the only bottleneck Confidential 2 7 heat Silicon TIM Cold Plate TIM = thermal interface material 45% Cold plate 20% TIM 35% Silicon R junction → coolant 41% 32% 38% 17% 27% 45% Warpage increased Power density increased Thermal resistance reduction translates to many many watts directly

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Cooling is NOT just a cold plate X kW XX kW XX MW X to XX GW Silicon TIM Cold Plate TIM = thermal interface material tray Rack Data Hall Cluster XXX kW

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• Expand the option set for pushing single-phase cooling limits • Align on simulation and validation guidelines to benchmark thermal performance • Align on test matrix and quality control across cold plate manufacturing methods • Drive the mass production and engagement model to accelerate advanced cold plate adoption • Keep innovation on the full stack to push the single phase cooling limit Call to Action Join us — scan the QR code to get involved.