PDF 原檔：報告_OCP2026_UALink生態系_20261015_original.pdf
講者公開簡報（OCP 官方 Recorded Content 頁提供下載）。文字以 PyMuPDF 逐頁抽取，
### p<n>為頁碼；圖表內容見原檔。
圖片清單（已驗證 2026-10-19）
| 檔名 | 頁 | 分類 | 親眼所見內容 |
|---|---|---|---|
報告_OCP2026_UALink生態系_20261015_p8.png |
p8 | 真資料圖 | UALink 規格 roadmap：200G 1.0 於 2025-04、1.1 與 128G 1.0 於 3Q25、2.0（加 Collectives）／Mgmt 1.0／Chiplet 1.0 於 2026-04、Compliance 1.0 於 4Q26、3.0（提高頻寬）／Mgmt 2.0／Compliance 2.0／Chiplet 2.0 於 2027 |
原始內容
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Powering AI at Scale: Inside the UALink Ecosystem AI CLUSTERS Kurtis Bowman (AMD), Helia Naeimi (Astera Labs), Josh Collier (Intel), Matt Holdrege (Microchip), and Priyank Shukla (Synopsys)
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AI CLUSTERS Powering AI at Scale: Inside the UALink Ecosystem UALink Consortium Mission: To unite the ecosystem in delivering UALink, an open standard, for AI scale-up networking that meets the escalating computing demands of AI applications. UALink Consortium Vision: Unleashing the full potential of open, optimized, high- performance, scale-up connectivity to enable transformative AI solutions.
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Panel Agenda 4 3 2 1 Introduction UALink Ecosystem and Infrastructure Discussion The Future of UALink Technology Audience Q&A
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Introductions Kurtis Bowman Board Chair (UALink Consortium) Director of Architecture and Strategy (AMD) Helia Naeimi Sr. Director of Technology (Astera Labs) Priyank Shukla Board Member (UALink Consortium) Sr. Director of Product Management (Synopsys) Matt Holdrege Associate Fellow (Microchip) Josh Collier Sr. Principal Engineer (Intel Corporation)
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UALink: The Open Protocol for AI Scale-Up Networking Any CPU Any Accelerator Any Switch Any Company
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The UALink Consortium defines a low-latency, high-bandwidth interconnect purpose-built for communication between accelerators and switches within AI compute pods, enabling next-generation disaggregated architectures. UALink Ecosystem and Infrastructure Discussion Kurtis Bowman (AMD) Helia Naeimi (Astera Labs) Priyank Shukla (Synopsys) Matt Holdrege (Microchip) Josh Collier (Intel)
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UALink: Unleashing the full potential of open, optimized, high-performance, scale-up connectivity to enable transformative AI solutions. The Future of UALink Technology Kurtis Bowman (AMD) Helia Naeimi (Astera Labs) Priyank Shukla (Synopsys) Matt Holdrege (Microchip) Josh Collier (Intel)
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2025 2026 UALink Specification Roadmap UALink Common DL/PL Systems & Manageability Compliance & Interoperability Chiplet Protocol/TL/Security/ RAS/Host Int UALink Mgmt 1.0 April 2026 UALink 1.1 3Q25 UALink 200G 1.0 April 2025 UALink Compliance 1.0 4Q26 UALink 2.0 Add Collectives April 2026 UALink 128G 1.0 3Q25 UALink Chiplet 1.0 April 2026 UALink 2.0 ECR/Errata April 2026 2027 UALink Mgmt 2.0 New features 2027 UALink 3.0 New features 2027 UALink 3.0 Increase bandwidth 2027 UALink Compliance 2.0 2027 UALink Chiplet 2.0 2027
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Q&A
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Thank You! UALink Consortium ualink@nereus-worldwide.com ualinkconsortium.org/ Follow us on LinkedIn for our latest updates