報告_MS_上海WAIC_20260721

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M July 21, 2026 02:47 PM GMT

Greater China Semiconductors | Asia Pacific

2026 Shanghai WAIC takeaways: SuperPods enabled by China's scale-up technology

Domestic AI competition is moving up the stack-from accelerator specifications to SuperPods, workload scheduling, and full-system utilization.

From new accelerators to system-level scaling: WAIC 2026 featured fewer major chip launches and a much broader range of SuperPod solutions. Almost every domestic accelerator vendor displayed a 64- or 128-card scale-up system, enabled by Chinese AI GPU vendors' proprietary scale-up technology (vs. global peers - Nvidia's NVLink or AMD's UALink). See Exhibit 4 for the scale-up technology comparison. As we wrote in China's AI Accelerators - Who's Poised to Win?, although Chinese AI GPUs are limited by wafer process at the chip level, they are strong in optical networking and server rack design at the system level ( Exhibit 11 ).

Competition in China's AI computing market is shifting from standalone chip specifications toward interconnects, memory sharing, and system reliability: In WAIC 2025, focus was on: 1) strong inference demand, 2) AI applications expanding beyond chatbots, 3) Huawei's launch of the 384-NPU CloudMatrix 384, and 4) new accelerators from multiple domestic vendors.

Other highlights:

• AI server systems: Huawei scales up beyond 1,000 NPUs: Huawei's Atlas 950 expands the scale-up domain from 384 Ascend 910C processors to 1,024 next-generation Ascend 950DT NPUs, combined with hybrid copper-andoptical interconnects and optical-path protection, Atlas 950 represents an important hardware foundation for domestic large-model training.
• AI GPU chips: Prefill and Decode (P/D) disaggregation emerges as a new inference theme: Separating computing-intensive prefill from bandwidth- and latency-sensitive decoding enables operators to optimize hardware allocation and schedule independently. Details in the following section.
• Along with the WAIC, we also hosted a China Tech Tour on July 16-17. Please see our China Tech Tour: Key Takeaways .

Stock implications: Within domestic AI computing, we prefer Cambricon (OW) , Iluvatar (OW), and Hygon (OW), given strong order visibility and solid supply chain;,we remain EW on MetaX. Among key enablers, we prefer SMIC (OW) for advanced-node capacity expansion; we are EW on Hua Hong, where strong AI PMIC demand should support specialty-wafer pricing. Continued investment in domestic memory and logic manufacturing benefits semiconductor equipment; our preferred plays are NAURA (OW), AMEC (OW), ACM Research (OW), and ASMPTc (OW).

Idea

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For analyst certification and other important disclosures, refer to the Disclosure Section, located at the end of this report.

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Key Takeaways from 2026 WAIC

Huawei Ascend: scaling the SuperPod beyond 1,000 NPUs

Huawei unveiled its next-generation Atlas 950 SuperPod at WAIC, marking another significant step-up in its scale-up architecture: Based on our checks at the event, the new system is primarily designed for Huawei's next-generation Ascend 950DT series, rather than the currently shipping 950PR series. Compared with the CloudMatrix 384 platform introduced in 2025, which connected 384 Ascend 910C processors, the Atlas 950 expands the scale-up domain to 1,024 NPUs. The system comprises 16 computing cabinets, each housing 64 NPUs, together with four dedicated UnifiedBus interconnect cabinets supporting all-to-all communication across the SuperPod.

System-level computing and memory capacity have increased materially: Each 64-NPU computing cabinet delivers up to 64 PFLOPS of FP8 performance and 128 PFLOPS of FP4 performance, implying aggregate SuperPod performance of approximately 1 EFLOPS FP8 and 2 EFLOPS FP4. Each computing cabinet contains around 6TB of HBM, translating into approximately 96TB across the 16 computing cabinets. By combining HBM with external DRAM through memory pooling, Huawei indicated that total addressable memory capacity could reach 256TB. The larger memory pool should be particularly relevant for large-model training, where model parameters, optimizer states, and intermediate data increasingly exceed the capacity of individual accelerator nodes.

UnifiedBus 2.0 is the key architectural upgrade, extending a common communication and memory protocol across physical layers: Within each blade, eight NPUs are connected through a full-mesh topology. At the cabinet level, eight blades-or 64 NPUs -are connected through a Clos fabric using a fully orthogonal, midplane-free design. Across cabinets, four UnifiedBus interconnect cabinets provide the optical scale-up fabric for the full 1,024-NPU system. The resulting architecture therefore remains physically hierarchical, but is logically flatter: rather than treating the rack and interconnect layers as separate communication domains, UnifiedBus provides common addressing, memory semantics and load/store operations across the entire SuperPod.

Overall, Atlas 950 moves Huawei's SuperPod architecture from several hundred to more than 1,000 tightly interconnected NPUs, laying the hardware foundation for large-model training on the next-generation 950DT platform. The use of copper links within computing cabinets and optical links between cabinets balances short-distance bandwidth and power efficiency with longer-distance scalability. Huawei has also incorporated optical-path protection so that a single-link failure does not interrupt system operation. This is important because, as cluster size rises, communication efficiency and fault tolerance become increasingly critical to maintaining effective computing utilization and stable training performance.

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Exhibit 1: Huawei showcased its new Atlas 950 SuperPod at 2026 WAIC

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Source: Company data, Morgan Stanley Research

Source: Company data, Morgan Stanley Research

Exhibit 2: NPU blade (tray) of Atlas 950 SuperPod

Source: Company data, Morgan Stanley Research

Exhibit 3: The reverse side of Atlas 950 mainly showcases the optical interconnects adopted by UBlink

Source: Company data, Morgan Stanley Research

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256TB -

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A flourishing SuperPod landscape

If WAIC 2025 was primarily a showcase for domestic AI accelerators, WAIC 2026 demonstrated that the competitive focus has shifted from individual chips toward system-level scale-up: Nearly every domestic AI GPU and ASIC vendor displayed a SuperPod solution, typically co-developed with server ODMs and networking partners. As a result, we observed several similar or identical system designs appearing across different booths. This reflects the increasingly modular nature of China's AI server ecosystem: accelerator vendors provide the computing platform and software stack, while ODMs integrate servers, interconnects, cooling and power infrastructure into rack- or clusterlevel solutions.

Scale-up configurations of 64-128 accelerators have become increasingly common:

Compared with earlier domestic systems centered on eight-card servers or relatively small clusters, the latest solutions seek to connect multiple computing trays or racks within a higher-bandwidth scale-up domain. The broader adoption of 64- and 128-card architectures suggests that domestic vendors are placing greater emphasis on collective communication efficiency, memory sharing and system-level utilization. However, the repeated appearance of similar ODM-developed platforms also indicates that differentiation will increasingly depend on interconnect performance, software optimization, fault tolerance, and effective application throughput-not simply the number of accelerators connected.

We also observed greater architectural diversity in rack-level interconnects, including orthogonal and conventional cable-tree solutions: In an orthogonal architecture, front and rear boards are arranged perpendicular to each other, allowing high-speed connectors to mate directly across the two planes. Domestic vendors including Huawei and ZTE increasingly favor midplane-free orthogonal designs, which eliminate the large central PCBs used in conventional backplanes. This can reduce the manufacturing and yield challenges associated with a large, high-layer-count midplane and shorten certain electrical paths. The trade-off is greater mechanical and connector-design complexity, while achievable bandwidth still depends on connector density, channel loss and signalintegrity engineering.

Domestic AI server configurations remain centered on GPU-to-CPU ratios of approximately 4:1 or 8:1. We believe this partly reflects the current workload mix. China's agentic AI demand has yet to scale materially, while many deployments remain focused on conventional model inference or selected training workloads. Domestic accelerators also currently deliver lower per-card computing performance than leading overseas products, meaning that accelerator throughput-not host-CPU capacity-is often the primary system bottleneck. As agentic workloads expand and require more data preprocessing, orchestration, retrieval and tool execution, demand for additional CPU resources could rise, potentially changing the optimal CPU-to-accelerator configuration over time.

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Vendor / Partner developed with ZTE

Atlas 950

Yunsui SL64-0

Xijing S6000

Architecture Highlights

16 compute cabinets + 4 UnifiedBus cabinets;

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Enflame + ZTE

MetaX + ZTE|

64 L600 Al accelerators

64 C600 Al accelerators

CPU

Source: Company data, Morgan Stanley Research

Exhibit 4: Comparison of some key SuperPod solutions at 2026 WAIC

networking and cooling

AIDOE AAAA

Similar as Yunsui SL64-0, using midplane-free orthogonal architecture

Source: Company data, Morgan Stanley Research

Exhibit 5: Enflame showed its SuperPod solution, co-

developed with ZTE

Source: Company data, Morgan Stanley Research

Exhibit 6: Midplane-free orthogonal designs at WAIC

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Source: Company data, Morgan Stanley Research

Scale

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P/D disaggregation enables more efficient heterogeneous inference

Reducing token costs while improving utilization of available accelerator resources was another recurring theme at WAIC: Large-model inference consists of two workloads with materially different characteristics. Prefilling processes the input prompt in parallel, generates the initial KV cache, and is primarily compute-intensive. Decoding generates subsequent tokens sequentially, repeatedly accessing model weights and the expanding KV cache, making it more sensitive to memory bandwidth, latency and batch scheduling. Running both phases on the same accelerator pool can create resource contention and utilization imbalances as model sizes, prompt lengths and concurrent requests increase.

P/D disaggregation addresses this mismatch by placing prefilling and decoding on separate accelerator pools: This allows operators to configure and schedule each pool according to its workload characteristics, preventing long prefilling requests from interrupting latency-sensitive decoding jobs. It also enables heterogeneous deployment using different accelerators for each phase. One configuration discussed at WAIC allocated approximately 90% of domestic accelerator capacity to prefilling and 10% of H20 capacity to decoding, reportedly increasing throughput 54% and reducing P90 time-to-first-token 64%. Actual benefits will depend on model architecture, workload patterns, scheduling, and interconnect performance.

Attention/FFN disaggregation could represent the next stage, although we did not observe meaningful demonstrations or benchmark results at WAIC: This approach further divides decoding execution into attention nodes, which repeatedly access a growing KV cache and are highly sensitive to HBM capacity and bandwidth, and FFN nodes, which perform more compute-intensive operations using relatively fixed model weights-or selected experts in an MoE model. In theory, this could enable highbandwidth, high-capacity memory systems for attention and more computing-oriented accelerators for FFN. However, frequent activation transfers between the two pools introduce substantial interconnect and synchronization requirements, making A/F disaggregation an emerging rather than production-ready architecture today.

Iluvatar unveils Tiangai 300 for full-stage AI inference

Iluvatar launched its Tiangai 300 series at WAIC, expanding its product positioning toward both prefilling and decoding inference: The accelerator supports FP4, FP8, and BF16 data formats and increases memory capacity to 144GB. Based on our supply chain checks, Tiangai 300 will adopt HBM3E with approximately 4TB/s of memory bandwidth, which should improve its ability to handle the bandwidth-sensitive decoding phase alongside computing-intensive prefilling workloads. Iluvatar indicated that the architecture can execute matrix and vector operations in parallel, enabling faster long-context processing. Based on the company's testing of domestic LLMs, including DeepSeek V3.2 and GLM 5.2, Tiangai 300 delivered higher prefilling and decoding performance than Nvidia's H100.

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Exhibit 7: Iluvatar's new Tiangai 300 chip shown at WAIC

Source: Company data, Morgan Stanley Research

Oriental Computing: 3D stacking offers an alternative path beyond process scaling

A private company, Oriental Computing, showcased its DF1000, a software-defined nearmemory 3D AI chip built using a domestic 14nm-class process. Conceptually similar to Huawei's T(Tao)-scaling vision, the design uses wafer-level hybrid bonding to vertically stack DRAM and logic dies, shortening data transfer distances and addressing the memory-wall bottleneck without relying solely on leading-edge process migration. The company claims memory bandwidth of 6.4TB/s and BF16 performance of 520TFLOPS, while a 128-card cluster has completed full-function stability validation. We view the product as another example of domestic vendors using architecture and advanced packaging to offset process-node constraints.

71$399

(REle)

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Exhibit 8: Oriental Computing unveiled a 3D stacking AI computing chip

Source: Company data

DF1000

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China Tech Tour: Key Takeaways

We hosted meetings with a number of Chinese semiconductor and AI semiconductor companies on July 16-17. Below, we summarize our key takeaways.

OmniVision: New growth engines beyond smartphone CIS

Emerging-market CIS: Management remains constructive on action cameras, machine vision, AR/VR, and medical imaging, supported by specification upgrades and rising content. Action-camera CIS content can reach approximately US$40 per device, versus US $15-20 for earlier products. Machine vision is migrating from low-resolution sensors toward tens-of-megapixel products for high-precision inspection and humanoid robots, materially increasing system content. Disposable endoscopes support attractive profitability in medical imaging, while professional cameras could become another growth driver from 2027-28.

Automotive and smartphone CIS : Automotive demand should recover after a seasonally weak first quarter, supported by overseas ADAS adoption. Tight supply for select products allows OmniVision to prepare price increases and pass through potential foundry cost inflation, while customer localization requirements should support greater use of domestic manufacturing. By contrast, management remains cautious on smartphones given weak Android shipments, fewer model launches and specification downgrades amid higher memory costs. Higher-resolution products provide some support, but smartphones are unlikely to drive near-term growth.

Analog: Data center optical modules offer the clearest path toward scale and profitability. Customized analog products carry ASPs of approximately US$2-3 per chip, with potential content of around US$30 in a 1.6T NPO system. OmniVision is developing photodetectors, TIAs, SerDes and other optoelectronic-conversion products, supported by recently acquired communications expertise. Initial products have started ramping, with broader adoption expected over the next two years. Domestic substitution and overseas component shortages create further opportunities, although most products remain in development or early qualification.

AMEC: Memory visibility remains strong; advanced logic opportunities broaden

Memory clients' orders: Management sees memory foundries as the segment with the strongest three-year demand visibility, driven more by localization and technology migration than global memory pricing. The DRAM client continues to add capacity and purchase R&D tools, while the NAND client is focused on technology upgrades and equipment replacement. Near-term NAND demand depends partly on replacing highaspect-ratio etching and PECVD equipment, with larger expansion linked to nextgeneration 3D NAND. Several preliminary awards are converting into purchase orders and shipments, although a meaningful portion of potential 2027 demand has yet to be formally placed.

Advanced logic and localization: Management expects domestic advanced-logic investment to remain strong over the next five years. Equipment localization is already

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above 10%, while select production lines could reach 25-30%. AMEC is developing platforms for FinFET, GAA and 3D architectures and indicated that certain product launches are only around six months behind the global leader.

Product expansion and execution: Beyond etching, AMEC highlighted progress in ALD, CMP, inspection, and metrology. Overseas component lead times are lengthening, but management expects year-end deliveries to remain on schedule. Price negotiations from major clients have become less aggressive, operating expenses remain controlled, and R&D intensity should decline as new platforms are commercialized.

Hua Hong: Pricing recovery and new capacity support growth

Utilization and pricing: Hua Hong's three 8-inch fabs are operating at approximately 110% utilization, while the first 12-inch fab also maintains high loading. Foundry prices have increased~10-15% across both platforms since late last year, with further increases possible into 2027. Demand remains broad-based and is currently led by server-related applications, while power semiconductors are relatively weaker. Management will reduce loading for weaker power products rather than repurpose dedicated capacity.

Capacity ramp: The 9A fab currently has around 60kwpm of capacity, with the full 83kwpm expected to be ready by 3Q26 and fully loaded by 1H27. Focused mainly on 4055nm products, it is targeted to become profitable by end-2027. Construction of 9B has begun, with 10-20kwpm expected by year-end and volume production starting in 2027. The fab will ultimately provide 55kwpm focused on 40-28nm. Depreciation will rise next year, but management expects revenue growth to outpace depreciation.

Acquisition and localization: The Rmb8.4bn HLMC Fab 5 acquisition is expected to close in August-September. The fab has 40kwpm of capacity, with profitability improving after Hua Hong assumed operational control. Hua Hong views 28nm as the practical limit for specialty processes, with potential applications including logic, NOR flash, MCUs and CIS.

Iluvatar: Tiangai 300 Broadens Inference Coverage

Product roadmap: In addition to launching new products at WAIC, Iluvatar joined our meeting. Management is awaiting core customer feedback on Tiangai 300 and indicated that certain performance metrics exceed H100, although the product remains behind Blackwell. Tiangai 150 primarily targets prefilling, while Tiangai 300 extends into decoding and post-training. Iluvatar is also developing a SuperPod with fewer than 200 accelerators. Tiangai 400 is scheduled to tape out in 2027 and will benchmark against the Blackwell generation.

Shipments and customers: Iluvatar expects to ship approximately 100,000 cards this year, with next year's volume expected to be no lower. The company is initially prioritizing scalable inference deployments rather than aggressively pursuing large training clusters. Some Internet customers are already using its products, while recent fundraising by domestic LLM developers could support stronger accelerator spending next year. Management prefers large customers capable of meaningful deployments, given the engineering resources required to support smaller installations.

Supply chain and costs: Iluvatar targets an approximately 50:50 split between overseas and domestic production capacity next year, subject to US policy and domestic

Idea

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Idea manufacturing progress. Localization should increase longer term, supported by dual-die architectures and inter-die connectivity developed since 2023. The July placement was mainly intended to secure supply-chain resources and support 2027 growth. Iluvatar has around Rmb10bn in cash and is negotiating additional credit facilities. Memory already represents more than half of card cost, while foundry prices are also rising; Tiangai 300 pricing may therefore include HBM cost pass-through mechanisms.

JCET: Accelerating advanced packaging expansion

JCET Group is accelerating its AI chip packaging expansion: This includes a CNY7.8 billion (US$1.1 billion) investment in a new advanced packaging and testing plant in Shanghai Lingang, strengthening capacity for AI computing, high-performance chips. Besides this newly announced fab, JME based in Jiangyin is also for 2.5D packaging; that fab achieved Rmb200mn revenue last year. Management believes we are Chinese AI GPU ramp-up is in early innings amid a multi-year structural trend.

JCET follows the market regarding OSAT pricing: Despite tight supply of substrate, there is limited impact on production, while could affect newly added capacity.

The company maintained its Rmb10bn capex target for this year and sees 2027 capex as likely to be higher: 1Q26 utilization was around 80% and 2Q26 utilization improved sequentially.

800

700

600

500

400

300

200

100

0

(US$ bn)

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Key Charts for Chinese AI Semis

Exhibit 9: We expect China's AI GPU TAM to grow to US$91bn

China cloud capex m Global Cloud Capex

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Source: Company data, Morgan Stanley Research estimates

Exhibit 11: Relative strengths of AI industries in the US and China

Source: Morgan Stanley Research

Exhibit 13: Surge in ByteDance (Volcano Engine/Doubao) tokens indicates high AI demand

Source: Company data, Morgan Stanley Research. ByteDance numbers represent monthly run-rate based on daily numbers.

Exhibit 10: We expect China's AI chip self-sufficiency to reach 70% in 2030e

Source: Company data, Morgan Stanley Research estimates

Exhibit 12: Average token price for China's mainstream AI LLMs

Source: Company data, Morgan Stanley Research

Exhibit 14: Chinese CSPs' capex will be a key demand driver for Chinese AI GPUs

Source: Company data, Morgan Stanley Research (E) estimates

734

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Exhibit 15:

Domestic chips have lower TCO and comparable per token cost (AI LLM inference) vs. NVIDIA's processors for China

TCO of 10MW capacity (US$ mn)

Per token cost (US$ cent) (Right-axis) (Lower is better)

Source: Company data, Morgan Stanley Research estimates

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