報告_UBS_漢測7856_首次覆蓋_20261008

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原始內容

Initiation of Coverage

Hermes Testing Solutions

Shifting-left, scaling-up: dual catalysts in chip probing and CPO

Jack-of-all-trades for bespoke testing solutions in the se iconductor industry

We initiate coverage of Hermes Testing HTSI) with a Buy rating and NT$8,880 PT. HTSI is uniquely positioned to benefit from two key semiconductor testing trends: shift-left testing and the emerging CPO testing market. Leveraging its long-standing relationship with TSMC, HTSI has established capabilities across electrical test engineering, customised test equipment, thermal control modules, probe cards, and CPO testing solutions. We forecast revenue growth of 127%/152%/78% in 2026E/27E/28E, driven by increasing adoption of thermal control modules for wafer-level test and initial deployment of CPO insertion 2 and insertion 3 test equipment through ficonTEC. Additional 2028E growth drivers include reflow tools, laser clean solutions, and MEMS probe cards. The stock trades at 27/15x 2027/28E PE, versus ~35x NTM PE for handlerequipment peers, offering re-rating potential as sales scale, new products are qualified, and its CPO presence expands. See our companion testing deep dive sector note.

Shift-left beneficiary with exceptional ther al control odules

Thermal control modules should be HTSI's largest growth driver over the next several years. We expect increasing chip power consumption, rising package complexity, and tighter probe pitches to drive adoption of advanced thermal control solutions used alongside leading-edge probers, in additional to more wafer level insertions and longer test time. We estimate HTSI will ship approximately 3,000 thermal-control modules in 2027E, up from around 1,200 units in 2026E, sales contribution rise from ~30% in Q226 to >50% of sales by 2027E. The launch of its second-generation platform in 2027E, which carries 25-50% higher ASPs, should further improve profitability. We forecast GM expansion from 55.5% in 2026E to 58.3%/60.0% in 2027E/28E.

Unique position to capture CPO upside

Through its partnership with German optical-automation leader ficonTEC, HTSI is positioned to participate in the initial ramp of CPO testing equipment. HTSI supports local manufacturing, installation, automation and after-sales service, making it a key enabler of volume production. We estimate HTSI captures approximately 30% of equipment value across the 40 insertion 2 and 70 insertion 3 systems we forecast for delivery in 2027E, with further potential upside in 2028E as adoption expands.

Valuation: initiate coverage with a Buy rating and price target NT$8,880

We forecast EPS of NT$29.1 in 2026E including a one-off employee share purchase programme impact), rising to NT$153.3/286.5 in 2027E/28E. Our NT$8,880 price target is based on 31x average 2028E PE, versus handler-equipment peers forward PE at roughly 35x, reflecting HTSI's unique exposure to both shift-left testing, CPO, and our estimate of 32% LT earnings CAGR. We initiate with a Buy rating.

Source: Company accounts, LSEG Eikon, UBS estimates. Metrics marked as UBS) have had analyst adjustments applied. Valuations: based on an average share price that year, E): based on a share price of NT$ 4,190.00 on 06-Oct-2026

Equities

Taiwan

Semiconductors

RIC: 7856.TWOBBG: 7856 TT

Trading data and key etrics

52-wk range

Market cap.

NT$5,295.00-516.55

NT$114b/US$3.58b

Shares o/s

27.2m ORD)

Free float

94%

Avg. daily volu e ('000)

240

Avg. daily value ( )

NT$1,068.4

Co on s/h equity (12/26E)

NT$15.2b

P/BV (12/26E)

9.1x

Net debt to EBITDA (12/26E)

NM

Ryan Sun

Analyst

ryan-za.sun@ubs.com

+886-2-8722 7267

Sunny Lin

Analyst sunny.lin@ubs.com +886-2-8722 7346

Thesis Map UBS Research THESIS MAP a guide to our thinking and what´s where in this report

Pivotal Questions

UBS VIEW

EVIDENCE

WHAT´S PRICED IN?

Upside/Downside Spectrum

Company Description

Q: Will HTSI be able to keep its oat within chip probing ther al control odules?

Yes. We expect HTSI's competitive position to strengthen as chip power consumption, package complexity, and probe density continue to increase. The company is developing next-generation thermal control solutions, including liquid cooling technologies, while also expanding into specialized chuck solutions designed to address wafer warpage. In addition, HTSI's close collaboration with TSMC, TEL, Advantest, and other OSATs should reinforce its position within advanced wafer-level testing.

Q: Will insertion 2 of CPO testing process be skipped?

No. We believe concerns surrounding insertion 2 adoption are overdone. While some industry participants favor bypassing insertion 2 due to throughput and ROI considerations, doing so increases the risk of defective optical engines being identified only after the components are delivered to OSATs, creating yield accountability challenges and higher packaging losses. Based on our industry studies, we expect insertion 2 testing to remain an important part of the CPO workflow over at least the next two years as the industry focuses on improving PIC yields and overall testing efficiency.

We initiate coverage of Hermes Testing HTSI) with a Buy rating and NT$8,880 price target. HTSI offers unique exposure to two of the semiconductor testing industry's most attractive growth drivers: 1) shift-left testing and 2) CPO testing. The industry's shift-left testing strategy will have more test insertions move to the wafer level before packaging, in addition to longer CP time. Leveraging its longstanding relationship with TSMC, HTSI has established capabilities across thermal control modules, electrical-test engineering services, customized equipment, and emerging CPO testing solutions. We believe there could be re-rating potential as sales scale, new products are qualified, and its CPO presence expands.

TSMC and OSATs have been expanding their CoWoS capacities aggressively, from 40kwpm in 2024 to around 90 kwpm in 2025, and is tracking to expand CoWoS capacity toward 160kwpm in 2026E. TSMC also ramped up expanding N3/N2 capacity, with multiple product launches from customers' pipelines-Nvidia's Rubin, AMD's MI400 series/Venice CPU and other cloud ASICs-translating into foreseeable, strong testing demand.

Despite a 264% YTD share-price increase, HTSI currently trades at just 15x of our 2028E EPS versus handler-equipment peers forward PE at roughly 35x. We believe market expectations for 2027 CPO testing equipment shipments remain conservative, particularly for insertion 2 equipment. Based on our industry analysis, we estimate HTSI will deliver 40 insertion 2 and 70 insertion 3 systems in 2027E, this should be higher than the market's expectation of no insertion 2 and limited insertion 3 shipment due to engineering bottleneck. We also see further upside in 2028E as CPO adoption expands. Our reverse DCF analysis indicates that the current market price implies only a 17% long-term sales CAGR vs our estimate of 27% and long-term GM level of 33% vs our estimate of 61%. We see scope for re-rating.

Value drivers (2027/28E) Thermal control module shipmentsCPO insertion 2 & 3 shipments GM

Source: UBS estimates

Hermes Testing Solutions HTSI) was founded in 2004 in Hsinchu, Taiwan. It focuses on providing semiconductor testing and inspecting solutions, equipment installation, technical support, and maintenance services. Its main business segments are customized semiconductor equipment, engineering services, and probe cards and other materials.

Testing TAM expanding with IC co plexity: leaders likely to outperfor industry growth

Our central view is that testing content per AI accelerator is growing faster than semiconductor unit volumes, creating a multi-year expansion in testing TAM. We believe semiconductor testing is entering a period of structural growth as AI-driven chip complexity increases testing intensity across wafer, package and system levels. The industry's shift-left strategy, which moves more testing upstream in the semiconductor manufacturing process, is resulting in longer and more frequent test insertions. As cloud AI GPUs and ASICs become increasingly complex, additional testing is required to ensure functionality, performance and yield, while reducing defective parts per million DPPM). More robust testing should improve deployment efficiency and lower the cost of operating AI infrastructure.

Semiconductor testing generally comprises four stages: wafer/chip probing CP), final test FT), system-level test SLT), and burn-in. CP is conducted at the wafer-level before packaging, while FT, SLT, and burn-in occur after packaging. The below Figure 3Semicondutr sgp:fwalvk illustrates the semiconductor manufacturing flow.

Figure 1: Se iconductor testing process: fro wafer level to package level

Source: UBS

We estimate semiconductor testing historically accounts for ~1% of total semiconductor revenue. Within testing, consumables such as probe cards, sockets and interface boards represent ~10-15% of industry revenue. According to Yole, the probe card, socket and interface board markets should grow from US$3.8bn, US$2.3bn and US$1.7bn in 2026 to US$5.5bn, US$3.1bn and US$2.0bn by 2031, respectively.

Figure 2: Yole esti ating testing consu ables TAM to cli b in the next 5 years

Source: Yole, UBS

Nonetheless, leaders within the testing sector will standout among competition, with greater sales CAGR comparing to the industry.

We see HTSI's sales for the next few years to mainly be driven by 1) thermal control module shipment and 2) CPO equipment shipment. In the past, thermal control modules weren't necessary for chip probing, due to less TDP for the chips. However, as new iterations of AI accelerators now got substantial power draw, this unlocks a brand new TAM for HTSI to enter with their thermal control modules to pair with probers, in order to prevent probe card damages.

• ˜ Robust ther al control odule ship ents. We estimate HTSI to ship 3,000/4,100 thermal control modules in 2027E/28E, with continuous demand in future years, bringing their 2026-31E semiconductor equipment sales CAGR to 48%.

• ˜ Ther al control odule ASP expansion. Gen 2 thermal control modules will start to ship in 2027E which will drive tool ASP up around 25-50%.

• ˜ De and supported by Advantest expansions. We believe the 3,000 thermal control modules shipment forecast for 2027E is not far-fetched, as we read-across from Advantest's announced capacity expansion plan testers will be paired with probers with a 1:1 ratio) with increasing capacity up to 5,000 testers within FY2027/3 and they also announced a 10,000-unit target within CY2028. Although the testers capacity expansion plan includes testers for final test, we do see a good portion to be allocated to chip probing given shift-left testing trend increasing both testing insertions and testing time before chip packaging.
• ˜ CPO is another brand new TAM for se iconductor testing. As insertion 2 and 3 testing equipment demand starts to rise in 2027 with scale-out CPO adoption, we see HTSI to ship 40/70 insertion 2 and 3 equipment in 2027E, with this number growing in 2028E to 80/160 and higher in future years as CPO proliferates, and driving 52% 2026-31E test equipment & engineering services sales CAGR.
• ˜ CPO to see content increase. Gen 2 insertion 3 equipment may start to ship in 2027E, with higher throughput and tool ASP.
• ˜ Insertion 2 ight scale down, but not happening anyti e soon. Insertion 2 equipment shipment might come down in 2029E and beyond, as foundries scaleup yield for photonic IC PIC) in order to lessen the time consuming insertion 2 testing burden.

Figure 3: Her es Testing is set to benefit with a 46% 2026-31E sales CAGR

Source: UBS estimates

Robust growth drivers across se iconductor testing

We believe HTSI is set to benefit from several semiconductor testing growth drivers and capture the AI induced, expanding testing TAM. We see HTSI is uniquely positioned as the main beneficiary of two of the strongest growth drivers within semiconductor testing: testing shift-left and CPO.

Shift-left igniting secular growth for chip probing

The industry's adoption of shift-left testing should drive a multi-year structural growth opportunity for chip probing CP) and its supply chain. As advanced packaging costs rise and AI accelerators become increasingly complex, semiconductor manufacturers are placing greater emphasis on identifying known-good dies KGD) before packaging.

Figure 4: CP is set to grow substantially with shift-left, each packaging step set to be MORE costly than the prior step

Source: UBS

The economics of advanced packaging reinforce this trend. Heterogeneous integration, chiplet architectures and 2.5D/3D packaging significantly increase package value, while defects identified late in the manufacturing process can lead to substantial scrap costs. To mitigate this risk, foundries and OSATs such as TSMC and ASE employ distributed testing flows incorporating KGD, known-good-stack KGS) and assembly test screening, to catch defects before the components enter a multi-week packaging cycle >2 weeks for CoW and 2 weeks for oS). The importance of these tests rises as AI clusters become increasingly dependent on component reliability and low defective-parts-per-million DPPM) rates. Given the multiplicative yield degradation, a 300bps yield decline at just one manufacturing stage e.g. dropping from 99.5% to 96.5%) reduces overall integrated four-stage yield from 98.0% to 95.0%; on a 500,000 unit ramp at US $10,000 per unit, this 3% scrap delta translates into around US$150m in unrecoverable losses given >6-month manufacturing lead times.

At the same time, rising chip power consumption is increasing the technical difficulty of wafer-level testing. As chip thermal design power scales beyond 1,000W and power density is expected by the industry to surge another 8x by 2030, traditional wafer-level chip probe WLCP) encounters severe physical bottlenecks. Finer probe pitches and higher power densities increase the risk of overheating, probe needle burnout and yield degradation, creating demand for more advanced probing and thermal-control solutions.

Figure 5: CP power delivery trend rises with process tech evolution

Source: UBS

Figure 6: Ther al control odule inside probers are essential to control wafer te perature

From pin count of ~20k Migrating now to ~40k In 2-3 years pin count >100k

Source: UBS

Her es Testing (HTSI) is a key beneficiary of this trend. Leveraging its long-standing relationship with TSMC and expertise in semiconductor test solutions, HTSI supplies advanced thermal control modules used alongside leading-edge probers made by Tokyo Electron), particularly for AI applications. These thermal control modules are required for high TDP semiconductor wafer probe in order to maintain the temperature of the chuck to avoid needle burns or probe card damages. We estimate HTSI will ship approximately 3,000 thermal-management modules in 2027E, up from 1,200 in 2026E, supporting sales growth of 127%/152% in 2026E/27E. HTSI is also the partner for prober installation, prober maintenance and services. In addition, HTSI provides highend chuck processing services, an area that should benefit from increasing package sizes and higher wafer warpage associated with advanced packaging.

Beyond thermal control modules, HTSI also supplies consumables and customised solutions for wafer-level testing, including probe card cleaning sheets and laser-based probe head cleaning systems. As probing intensity increases under the shift-left testing model, demand for cleaning and maintenance solutions should rise alongside probe card utilisation. Currently, cleaning sheets is around 5% of sales, but we believe it could gain traction in 2027/28E and beyond. We see additional upside from future modular laser cleaning systems that could be integrated directly with probers, further expanding HTSI's content opportunity within advanced wafer-level testing.

CPO testing fuelling future growth for se iconductor testing

As interconnect bottlenecks increasingly shift from the memory wall to the copper wall, we believe co-packaged optics CPO) adoption is inevitable over the longer term. Testing remains one of the key bottlenecks to CPO deployment, as optical validation differs fundamentally from the electrical testing processes that have dominated semiconductor manufacturing for decades. As a result, CPO is creating a new testing opportunity across the semiconductor equipment and consumables ecosystem. We have written extensively on CPO and opportunities that it brings to the semiconductor supply chain, see our CPO deep dive, our thoughts on CPO timing, 2026 SiPhIA conference takeaways, and SEMICON 2026 takeaways.

Various test equipment suppliers are scrambling to come up with ideal testing equipment across the four insertions of CPO testing, with solutions to ensure both optical and electrical signal integrity of the CPO solutions. The four insertions are:

• ˜ Insertion 1: Electronic IC (EIC)/Photonic IC (PIC) test. Single-side wafer test that has dedicated probe cards to test the fabricated EIC/PIC wafers.
• ˜ Insertion 2: Optical/Electrical test. Double sided wafer test, testing the hybrid bonded e.g. via TSMC's COUPE) EIC and PIC wafers by an opto-electrical test that verifies the electrical signals on the top and optical signal on the bottom of the hybrid bonded wafers.
• ˜ Insertion 3: Optical engine (OE) test. The OE tests are done to ensure the quality of the OEs and with FAU Fiber Array Unit) attached, to ensure the signal integrity of the OEs. The testing equipment needs to be able to handle 224G per channel data rates, requiring high unit per hour UPH) throughput, meticulous dirt mitigation, and maintaining a near 100% contact rating on high-speed sockets.
• ˜ Insertion 4: ASIC final test. This final test step is established post the OEs are packaged together with the ASIC. The complete ASIC package now with CPO) is now tested for opto-electrical functionalities.

As it stands, insertion 2 and insertion 3 are the two areas where there are the most debates in the industry. Insertion 3 suppliers such as Chroma has noted the trend of 'shift-to-middle' paradigm centered on insertion 3. In high-density scale-out switches deploying up to 32 optical engines e.g. Nvidia's Spectrum-X architectures), any OE defect results in package scrap at the CoWoS level, making 100% known good die KGD) validation at the singulated OE stage an absolute commercial requirement.

Figure 7: An illustration for insertion 2 test ethod

Figure 8: An illustration for insertion 3 test ethod

Source: UBS

Source: UBS

As shown in the below figure, as there are no set standards for the testing equipment, throughput and stability are now the main target and area of competition for the major players in the field. Notable ones for each insertions are listed.

Figure 9: CPO testing flow chart with key suppliers

Source: UBS

With its 25 years of precision test equipment expertise, ficonTEC is an early mover for CPO test equipment and has key know-how for optical alignment, which is quintessential for optical test. HTSI, through its partnership with ficonTEC, is set to be a major beneficiary once CPO proliferates in 2027E-28E. As the partner of ficonTEC, Hermes Testing is the key enabler that can help ficonTEC achieve HVM for its CPO testing equipment. As of now, our view is that both insertion 2 and insertion 3 should be required within the next two years, despite the difficulties surrounding double-sided wafer probing insertion 2), as the yield for OEs are still not high enough to avoid defective dies. Finding out known-good OEs will be crucial before the FAU coupling process during the latter stages of CPO packaging, to prevent impeding the final package with multiple OEs attached to the switch ASIC e.g. 32 OEs on Nvidia's Spectrum-X). We estimate Hermes Testing will ship 40/70 units of insertion 2/3 testing equipment in 2027E, with potential upside to the numbers as we view Hermes Testing will likely assist with the ramp up for Gen 2 insertion 3 equipment in 2027E. Gen 2 insertion equipment will come with better throughput and ASP.

Figure 10: We believe HTSI CPO equip ent sales will pick up in 2027/28E with 541%/135% YoY growth

Source: UBS estimates

Beyond insertions 2 and 3, HTSI is also positioned to participate in insertion 1 testing through customised prober solutions for photonic integrated circuit PIC) testing. We believe these solutions could eventually be packaged as licensable intellectual property, creating an additional long-term growth opportunity as CPO adoption broadens. While near-term testing growth is driven by AI accelerators, CPO represents the next major expansion cycle for semiconductor testing. We believe HTSI is uniquely positioned to participate across multiple test insertions, providing exposure to a potentially significant source of incremental revenue beginning in 2027E.

Figure 11: A switch chip with 32 OEs and the CPO packaging supply chain

Source: UBS

HTSI's unique position for new TAM of ther al control odules and CPO test equip ent

Hermes Testing Solutions HTSI) was founded in 2004 in Hsinchu, Taiwan, as a spin-off from Hermes-Epitek. The company provides semiconductor testing and inspection solutions, engineering services, customized equipment, and test consumables. HTSI maintains a global service footprint across Taiwan Hsinchu, Tainan), Mainland China Suzhou), Japan Tokyo, Kumamoto), Singapore, Malaysia, and the United States Arizona), enabling close support for leading semiconductor customers.

Its main business segments are structured around three pillars:

• ˜ Se iconductor equip ent and custo ized products: HTSI utilises a dualtrack strategy of independent R&D and also equipment agency sales. They offers

highly customized solutions designed to address specific client pain points and bottlenecks. Key products include: thermal control modules that pair with a 1:1 ratio with wafer-level test probers, electron beam inspection equipment, white light interference optical inspection systems, laser probe cleaning machines, and the SYMPHONY fluxless reflow system.

• ˜ Testing equip ent engineering services: The company operates the largest engineering service team in Taiwan, consisting of over 340 technical professionals. The engineering service team provides extensive equipment life-cycle support, including installation, relocations, modification, testing, routine maintenance, and repair services. CPO related equipment sales/services will be recognized within this segment, as CPO are not direct HTSI products, but rather sales recognition via its partnership with ficonTEC.
• ˜ Probe card design, anufacturing, and cleaning aterials: HTSI delivers a comprehensive product portfolio that supports the entire probe card life-cycle. For probe cards, they supply membrane, cantilever, and vertical probe cards. As they are small in scale, HTSI targets niche probe card applications such as RF, 5G/6G, millimeter wave, LCD driver, low end logics, TIA Transimpedance Amplifier), etc. In addition to the three existing probe technologies, HTSI also collaborates with MJC in Japan for MEMS probe development, targeting sales in 2028E for high-end, AI/ HPC related applications. Cleaning materials is another important business within this segment, as HTSI source and process sand paper or other materials to offer cleaning sheets to clean the probe cards, removing oxidations, unwanted particles and substances that accumulated on the probe cards during the testing process.

The sales resiliency in the coming years mainly stems from its robust relationship with key industry players, especially as an engineering and service provider with TSMC for testing solutions. This sets up a solid foundation for its customized equipment business, as they know the specific testing bottleneck to tackle. For instance, as Hermes-Epitek manufacturers the probers for Tokyo Electron TEL) and HTSI helps with installation, services, and maintenance of the probers, they understand the thermal bottlenecks that the wafer-level test industry has been facing and can effectively come up with module solutions to solve this.

Margins set to expand with value-added products and services

The company has demonstrated strong execution in advanced wafer-level testing, with H126 revenue of NT$2.2bn already exceeding 90% of FY25 revenue NT$2.4bn). Profitability has also improved significantly, with GM increasing from 42.1% in 2025 to 54.9% in H126.

With share of value-added products and services set to rise in 2027E in sales mix, HTSI is set to see GM and operating leverage expansion. As a niche engineering service provider that has robust ties to leading foundries and OSATs, we believe HTSI has substantial pricing power and estimate HTSI' GM for thermal control modules to be around 65%, with GM for CPO equipment of around 60% as HTSI provides an engineering-servicelike business for it. We believe these factors will help the company to reach a 60% longterm GM range.

OPM is also set to expand with customized equipment sales rise in total sales mix. If we exclude the one-time expense to be recognized during Q326 for employee stock benefits we estimate around NT$1bn), YoY opex growth will be around 99% for 2027E, with downside risk if the company conducts tight cost control measures. We forecast the company's OPM will expand from 19.5% in 2026E, to 44.3%/47.0% in 2027/28E.

Figure 12: HTSI sales set to continue to cli b with 152% growth and GM at 58.3% in 2027E

Source: UBS estimates

Figure 14: We see custo ized equip ent to continue to drive co pany growth

Source: Company data, UBS estimates

Figure 16: UBS earnings forecast

Source: UBS estimates

Figure 13: OPM set to grow to 44.3%/47.0% in 2027/28E

Source: UBS estimates. Note 2026E opex includes a one-time NT$1bn employee stock benefit.

Figure 15: HTSI H126 sales ix breakdown

Source: Company data, UBS

Figure 17: Testing supply chain valuation table

Source: LSEG, UBS estimates. Priced as of October 6 HKT).

What´s Priced In?

WHAT´S PRICED IN?

Source: LSEG, UBS

Despite a 264% YTD share-price increase, HTSI still trades at just 15x 2028E P/E. We believe market expectations for 2027E CPO testing equipment shipments remain conservative, particularly for insertion 2 equipment. Based on our industry analysis, we estimate HTSI will deliver 40 insertion 2 and 70 insertion 3 systems in 2027E, this should be higher than the market's expectation of no insertion 2 and limited insertion 3 shipment due to engineering bottleneck. We also see further upside in 2028E as CPO adoption expands. Our reverse DCF analysis indicates that the current market price implies only a 17% long-term sales CAGR vs our estimate of 27% and long-term GM level of 33% vs our estimate of 61%. We see scope for re-rating.

We believe the market is not fully reflecting three key growth drivers:

1) Shift-left testing is still underappreciated.

As advanced packaging costs rise and AI accelerators become increasingly complex, more thorough testing is done at the wafer-level. This should drive sustained demand for HTSI's thermal control modules, probe card consumables, and other wafer-level testing solutions.

2) CPO revenue potential re ains underesti ated.

Investor expectations for 2027 CPO equipment shipments, particularly insertion 2 testing systems, remain conservative. Based on our industry studies, we forecast HTSI will deliver 40 insertion 2 and 70 insertion 3 systems in 2027E, with further potential upside in 2028E as CPO adoption broadens.

3) New products provide additional optionality.

Beyond its core businesses, HTSI is expanding into higher-value solutions including massreflow tools, MEMS probe cards and laser cleaning systems, creating incremental growth opportunities that we believe are largely absent from current expectations.

We value HTSI using 31x average 2028E PE, underpinned by a 32% 2027-31E earnings CAGR. We use 2028E PE as our view is that 2028 is the year for thermal control modules and CPO adoption grow from the initial ramping up stage to mass adoption stage. We believe using handlers as a peer group is justifiable for a unique company like HTSI, with thermal control modules for chip probing sharing similar characteristics as active thermal control used for final test, in addition to Hon Precision and Chroma having exposure to CPO test equipment. For equipment vendors, the peer group's average NTM PE post 2022 is around 35x, and the group is currently trading at around 41x NTM PE see What's Priced In chart).

HTSI is trading at NT$4,190 as of 6 Oct 2026

Upside/Downside Spectrum

Upside/Downside Spectrum

Source: UBS estimates

Risk to the current share price is heavily skewed (2.2:1) to the upside.

UPSIDE (NT$10,000): Our upside scenario reflects stronger than expected thermal module and CPO equipment shipment in 2027-28E, with additional upside from better traction of probe cards and mass reflow tools, forming 157%/91% YoY sales growth in 2027/28E and even higher operating leverage with OPM of 46.3%/50.0% in 2027/28E. This scenario implies a 34x 2028E PE, a upside driving by more equipment demand stemming for robust shift-left test induced equipment bottleneck, alongside CPO proliferation with scale-up CPO equipment pull-in in 2028E.

BASE (NT$8,880): Our price target of NT$8,880 is based on 31x 2028E PE. We expect an earnings CAGR of 32% in 2027-31E. With shift-left trend for more thermal module requirement during testing, alongside 40/70 CPO insertion 2/3 shipment. We see these growth drivers driving YoY sales growth from a high base of 127% in 2026E to 152%/78% YoY in 2027/2028E, with OPM of 44.3%/47.0% in 2027/28E.

DOWNSIDE (NT$1,500): Our downside scenario reflects lower shipment of thermal control modules due to less advanced prober demand with less insertion 2 and 3 equipment shipment due to bottlenecks with CPO production, alongside limited additional growth drivers to be picked up in 2028 such as MEMS probe card and mass reflow tools. This leads to weaker YoY sales growth of 67%/50% in 2027/28E and operating margin of 29.3%/32.0% in 2027/28E as equipment shipment fails to scale. This scenario implies a 14x 2028E PE, as valuation de-rate with dimmed outlook without CPO and limited upside from thermal control module shipments.

HTSI is trading at NT $4,190 as of 6 Oct 2026

Company Description

Company Description

Hermes Testing Solutions HTSI) was founded in 2004 in Hsinchu, Taiwan. It focuses on providing semiconductor testing and inspecting solutions, equipment installation, technical support, and maintenance services. Its main business segments are customized semiconductor equipment, engineering services, and probe cards and other materials.

Industry Outlook

New iterations of semiconductors, especially for AI / HPC applications, are set to increase in both front-end wafer fabrication advancements and back-end packaging complexities with each iterations. With the industry now moves to utilize "shift left", chip probing and its relevant supply chain will be key beneficiaries of this trend which we believe will unlock multiyear, secular growth trends.

HTSI sales and GM trend

Source: Company data, UBS estimates

HTSI H126 sales ix breakdown

Source: Company data, UBS

Her es Testing Solutions (7856.TWO)

Source: Company accounts, UBS estimates. UBS) metrics use reported figures which have been adjusted by UBS analysts. 1 Cash EPS UBS, diluted) is calculated using UBS net income adding back depreciation and amortization.

Her es Testing Solutions (7856.TWO)

Source: Company accounts, UBS estimates. UBS) metrics use reported figures which have been adjusted by UBS analysts.

Forecast returns

Co pany Description

Hermes Testing Solutions HTSI) was founded in 2004 in Hsinchu, Taiwan. It focuses on providing semiconductor testing and inspecting solutions, equipment installation, technical support, and maintenance services. Its main business segments are customized semiconductor equipment, engineering services, and probe cards and other materials.

Valuation Method and Risk State ent

We value Hermes Testing based on PE methodology. Risks for the semis industry:

• Geopolitical uncertainties: Geopolitical uncertainties including tariffs and more export control could negatively impact semis cycle, and a downturn would lead to slower demand in the overall market and moderating capacity expansion.
• Meaningful deceleration of new technology development: Slower demand and less investment are expected If there is meaningful deceleration of new technology development such as Cloud AI, autonomous driving, etc.
• Rising utility cost: Larger-than-expected utility cost increases would further pressure profitability. Rising utility costs in Taiwan have negatively impacted margins for Taiwan tech companies.

Company risks:

• Faster- or slower-than-expected front-end/CoWoS capacity expansion: This could result in Hermes Testing gaining/losing equipment orders from major foundries and OSATs.
• Competitors achieving technological advancement: Potential risk of competition from either local or foreign companies) achieving technological advancements could result in Hermes Testing losing market share from major foundries and OSATs.
• Better- or worse-than-expected AI growth: Better- or worse-than-expected AI growth could lead to a ramp-up or a slowdown of equipment orders from major foundries and OSATs to Hermes Testing, affecting long-term revenue growth potential.
• Slowdown or delay of new technological advancement: A potential slowdown or delay of the rollout for technological advancements for technologies such as SoIC, CoPoS, and CPO, would limit future equipment orders.
• Increase of raw material costs: Rising raw material costs may directly impact Hermes Testing's margins for equipment shipments.

Quantitative Research Review

UBS Global Research publishes a quantitative assessment of its analysts' responses to certain questions about the likelihood of an occurrence of a number of short term factors in a product known as the 'Quantitative Research Review'. The views for this month can be found below. Views contained in this assessment on a particular stock reflect only the views on those short term factors which are a different timeframe to the 12-month timeframe reflected in any equity rating set out in this note. For previous responses please make reference to i) previous UBS Global Research reports; and ii) where no applicable research report was published that month, the Quantitative Research Review which can be found at https://neo.ubs.com/quantitative, or contact your UBS sales representative for access to the report or the Quantitative Research Team on ubs-quant-answers@ubs.com. A consolidated report which contains all responses is also available and again you should contact your UBS sales representative for details and pricing or the Quantitative Research Team on the email above.

Her es Testing Solutions