PDF 原檔：報告_OCP2026_Marvell_客製HBM系統_20261015_original.pdf
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圖片清單（已驗證 2026-10-19）
| 檔名 | 頁 | 分類 | 親眼所見內容 |
|---|---|---|---|
報告_OCP2026_Marvell_客製HBM系統_20261015_p3.png |
p3 | 真資料圖 | HBM 占晶片面積與成本：示意圖為中央運算邏輯（約 70% die）兩側各一排 HBM PHY＋controller，外側各三顆 HBM；標題寫 HBM 約 30% die 面積、>50% XPU 成本；文字稱 HBM4 介面翻倍為 2048 bit（32×64-bit 通道）、記憶體 BOM 在許多 GPGPU/ASIC 占 >60-80% |
報告_OCP2026_Marvell_客製HBM系統_20261015_p4.png |
p4 | 文字卡 | cHBM 四欄檢核表：Base die 與面積（PHY 約占運算 die 30%、可回收至多 25% 面積、多至 30% 更多運算）、D2D/TSV/HCB（UCIe 非為 HBM 頻寬密度設計、降 D2D 功耗、2.5D 到 3D 混合鍵合同一架構）、封裝熱（HBM 堆疊占熱阻 57%、>2.0 W/mm²、>100 W/stack）、生態系 |
報告_OCP2026_Marvell_客製HBM系統_20261015_p5.png |
p5 | 真資料圖 | 每堆疊頻寬長條圖：HBM2E 2020 0.5 TB/s、HBM3 2022 0.8、HBM3E 2024 1.0、HBM4 2026E 2.0（8 Gbps）至 3.3（13 Gbps）、HBM4E 2027-28E 3.6（14 Gbps）至 4.1（16 Gbps）、HBM next-gen 2028E+ 5.3（HBM4E+30%）至 7.2 TB/s（28 Gbps）；標示最多 8.9 倍 |
報告_OCP2026_Marvell_客製HBM系統_20261015_p6.png |
p6 | 真資料圖 | AI 晶片 TDP 折線（GPGPU 與 ASIC，2021 400W 至 2027E 3,000W）與功率密度表：2021 0.48、2022 0.86、2023 0.86、2024 0.75、2025 0.88、2026E 1.25 W/mm²，>28 Gbps I/O 時 >2.0 W/mm²；文字稱 HBM 熱通量超過 JEDEC 約 1.7 W/mm² 參考值 |
報告_OCP2026_Marvell_客製HBM系統_20261015_p9.png |
p9 | 真資料圖 | HBM5 熱路徑：左為 SK hynix iHBM 剖面（SoC 旁 HBM 堆疊，D2D PHY 上方藍色 ICE 矽塊連到 Cold Plate，標示熱阻約降 30%）；右為 HBM5＋Heat Path Block 構想（核心 die 堆疊旁加矽塊）；文字稱 HBM5 約 100 W/stack、D2D PHY 為最熱點 |
報告_OCP2026_Marvell_客製HBM系統_20261015_p11.png |
p11 | 文字卡 | SBD（同時雙向）D2D 四項規格卡：64 Gbps/wire（含 15% 以上頻寬保護）、PHY 面積 15%、功耗最多降 75%（尖峰流量降 42%）、>7 TB/s UCIe 密度 |
原始內容
p1
© 2026 Marvell. All rights reserved. Mark Hsin-wei Tseng | Director, Marvell Technology Custom HBM as a System: Co-designing the Base Die, Die-to-Die Power, and Package Thermals for AI Accelerators SERVER: OPEN CHIPLET ECONOMY
p2
© 2026 Marvell. All rights reserved. Except for statements of historical fact, this presentation contains forward-looking statements (within the meaning of the federal securities laws) including statements related to future revenue, future earnings, and the success of our product releases that involve risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “plans,” “projects,” “believes,” “seeks,” “estimates,” “can,” “may,” “will,” “would” and similar expressions identify such forward-looking statements. These statements are not guarantees of results and should not be considered as an indication of future activity or future performance. Actual events or results may differ materially from those described in this presentation due to a number of risks and uncertainties. Forward-looking statements are only predictions and are subject to risks, uncertainties and assumptions that are difficult to predict, including those described in the “Risk Factors” section of our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q and other documents filed by us from time to time with the SEC. Forward-looking statements speak only as of the date they are made. You are cautioned not to put undue reliance on forward-looking statements, and no person assumes any obligation to update or revise any such forward-looking statements, whether as a result of new information, future events or otherwise. Forward-looking statements
p3
© 2026 Marvell. All rights reserved. HBM: ~30 % of die area, > 50% of XPU cost HBM HBM HBM HBM HBM HBM Compute logic ~70% of die HBM PHY + controller HBM PHY + controller Why HBM crowds the die • HBM4 doubles the interface to 2048 bits (32 × 64-bit channels)3, growing PHY area, power and edge “beachfront.” • More HBM stacks compete with compute logic for the same die edge. • Memory I/O, not the cores, increasingly limits accelerator scaling. • At today’s memory price, memory BOM cost
60-80% in many GPGPU/ASICs. Not to scale. 1. Marvell Industry Analyst Day, Dec 2024, as reported by Futurum, “Marvell Debuts Custom HBM Compute Architecture,” Dec 18, 2024. 2. Silicon Analysts, “HBM Memory Pricing and Specifications (2026),” Sep 2026, compiling Epoch AI, Raymond James, TrendForce and SemiAnalysis estimates. 3. JEDEC JESD270-4 HBM4 standard, Apr 2025.
p4
© 2026 Marvell. All rights reserved. Checklist make high-performance cHBM work Base die and area HBM4’s 2,048-bit PHY takes ~30% of compute-die area Move PHY and controller into a custom base die Reclaim up to 25% of die area for compute Use the space for up to 30% more compute Speed up customized the base-die interface across memory vendors D2D / TSV / HCB UCIe was not built for HBM Next- gen class bandwidth density Cut D2D power Keep one D2D architecture from 2.5D to 3D hybrid bonding Prove 3D hybrid-bonding yield at volume Package thermals The HBM stack holds 57% of thermal resistance; HBM Next- gen reach > 2.0 W/mm². Reserve a silicon heat path at the D2D PHY Plan TIM, lid and cold plate with the base die Model heat flux above 2.0 W/mm² for HBM5 Validate cooling beyond 100 W/stack and > 2.0 W/mm². Ecosystem No single company can build custom HBM alone Align memory makers, foundries, OSATs and XPU designers Share thermal models and test data across the chain Define cHBM with more re- usable modules between different AI applications. Sources: Marvell newsroom (Dec 2024; Aug 2025); JEDEC JESD270-4 and HBM thermal-density reference; IEEE ECTC 2026; SK hynix iHBM release (May 2026); Hot Chips 2026. Details on earlier slides. Addressed today ¨ Additional effort needed
p5
© 2026 Marvell. All rights reserved. • Per-stack bandwidth grows ~1.7× every 2 years: 0.5 TB/s (2020) to 3.6–4.1 TB/s (2028E) • Two ways to get there: more data I/Os (1,024 → 2,048 in HBM4) and faster I/O speed • HBM4 moves the base die to a logic process, the opening for a custom base die in HBM next-gen HBM bandwidth per stack grows ~9× by 2028 E = projection. Dark segment = low end, light = high end: HBM4 8 Gbps (JEDEC) to 13 Gbps (Hot Chips 2026); HBM4E 14–16 Gbps; HBM next-gen = 16 Gbps HBM4E +30% (industry disclosure, Aug 2026). Industry roadmap cites up to 28 Gbps × 2,048 I/Os (Hot Chips 2026). Source: JEDEC JESD270-4; SK hynix, Aug 2026; Hot Chips 2026; NVIDIA Technical Blog, “NVIDIA NVLink Fusion Brings NVHBM to Next- Generation AI Infrastructure,” Aug 2026. 0.5 TB/s 0.8 TB/s 1.0 TB/s 3.3 TB/s 13 Gbps 4.1 TB/s 16 Gbps 7.2 TB/s 28 Gbps 2.0 TB/s 8 Gbps 3.6 TB/s 14 Gbps 5.3 TB/s HBM4E +30% HBM2E HBM3 HBM3E HBM4 HBM4E HBM next-gen HBM bandwidth per stack up to 8.9× 2020 2022 2024 2026E 2027-28E 2028E+
p6
© 2026 Marvell. All rights reserved. Base-die logic under the DRAM stack is solvable only through package-level co-design. • HBM heat flux passes the JEDEC ~1.7 W/mm² reference: HBM5 reaches >2.0 W/mm² at >28 Gbps • TIM, lid, and integrated cooling must be planned with the compute die, base die, and package — not bolted on Base-die logic / memory reach heat limit 400 W 3,000 W 0 1,000 2,000 3,000 2021 2022 2023 2024 2025 2026E 2027E GPGPU ASIC W/mm² = chart TDP ÷ GPGPU logic-die area (excl. HBM and I/O dies); 2024–26 dual-die parts assume ~800 mm² per reticle-size die; 2026–27 are estimates (E). Source: JEDEC HBM thermal-density reference; SK hynix, “iHBM” Integrated Cooling Elements announcement, May 26, 2026; GPGPU vendor product specifications. / Marvell Internal. / JEDEC 2026 consortium. / S. Han, “HBM Base Die,” Hot Chips 2026, Aug 23, 2026. Power density: GPGPU logic die vs. HBM Year TDP Logic die W/mm² 2021 400 W ~800 mm² 0.48 2022 700 W ~800 mm² 0.86 2023 700 W ~800 mm² 0.86 2024 1,200 W ~1,600 mm² 0.75 2025 1,400 W ~1,600 mm² 0.88 2026E 2,000 W ~1,600 mm² 1.25 —
28 Gbps I/O (2×) 2.0 AI chip TDP by type, W
p7
© 2026 Marvell. All rights reserved. • In 2.5D packages, HBM internal resistance is 57% of the stackup vs 13% for the ASIC — the stack, not the logic, is the limiter • Taller stacks push internal temperature past the acceptable range: 8- → 16-high HBM crosses the thermal budget by 2028 The HBM stack holds 57% of thermal resistance 13 57 14 27 12 56 17 0 20 40 60 80 100 ASIC HBM Thermal Resistance Contribution in 2.5D (%) Internal Crosstalk TIM1+Lid TIM2+Cooling Source: “Package Thermal Design,” 2026 IEEE 76th Electronic Components and Technology Conference (ECTC), Orlando, FL, May 26–29, 2026. 2.5D package cross-section (heat flows up) TIM2 + cold plate TIM1 + lid Interposer + substrate ASIC 1 die · 13% HBM stack 8–16 dies · 57%
p8
© 2026 Marvell. All rights reserved. Hybrid bonds cut HBM thermal resistance 23–47% • No underfill gap: Cu–Cu bond removes the ~30 µm µ-bump gap 23–47% lower die-to-die thermal resistance than microbump HBM stacks up to 3× higher vertical thermal conductivity through the bond layer
15% shorter HBM stack height, so less heat builds up in the stack Range depends on Cu pad density (≥20% coverage) and bond-interface quality HBM die-to-die joint, cross-section Today: µ-bump + underfill (TC-NCF / MR-MUF) Cu–Cu hybrid bond (3D) Near-zero gap; heat flows through Cu and oxide Caveat: 3D logic-on-memory raises power per footprint; the heat path still needs package co-design Images: Samsung (ECTC 2024) via The Elec, Jun 2024 Sources: Electronics 14(13):2682 (2025); Onto Innovation (2025) • Shorter heat path: less material between base die and cold plate
p9
© 2026 Marvell. All rights reserved. • HBM5 is projected at ~100 W per stack; the D2D PHY in the base die is its hottest spot • HBM suppliers add a dedicated silicon heat path. HBM5 adds a silicon thermal path at the D2D PHY Images: SK hynix (left), industry mockup (right). Sources: SK hynix iHBM press release (May 26, 2026); HBM5 HPB mockup, Hot Chips 2026. SK hynix iHBM HBM5 + Heat Path Block (HPB) Silicon ICE in the D2D PHY: ~30% lower thermal resistance Silicon block beside the core-die stack pulls PHY heat to the cold plate
p10
© 2026 Marvell. All rights reserved. For HBM, energy per bit sets the budget, not bandwidth density: every pJ/bit saved goes back to compute. SBD cuts D2D power by up to 75% 75% power reduction applies to normal workloads (42% at peak traffic). Source: Marvell, “Marvell Unveils Industry’s First 64 Gbps/wire Bi-Directional Die-to-Die Interface IP in 2nm,” press release, Aug 2025. D2D power, % of an interface without adaptive power management Density is already enough HBM5 needs ~6.4 Tbps/mm (7.2 TB/s over 9 mm beachfront) −42% even at peak traffic Power falls at full HBM bandwidth, not just when idle Power tracks traffic Savings are largest under bursty AI-inference traffic 100% 58% 25% Without adaptive power mgmt SBD, peak traffic SBD, normal workloads −75%
p11
© 2026 Marvell. All rights reserved. SBD D2D enables a custom, low-power base die What simultaneous-bidirectional (SBD) D2D brings to a customized base die High performance 64 Gbps/wire Simultaneous- bidirectional signaling on every D2D wire With bandwidth guard with 15% or higher. High capacity 15% PHY area Smaller D2D PHY frees base-die area for custom logic and memory Lower power Up to 75% less D2D power in normal workloads; up to 42% less at peak traffic High connectivity
7 TB/s UCIe density for main- die-to-main-die and main-die-to-I/O-die links Source: Marvell — 64 Gbps/wire Bi-Directional D2D Interface IP in 2nm (Aug 2025); Hot Chips 2025
p12
© 2026 Marvell. All rights reserved. Checklist make high-performance cHBM work Base die and area HBM4’s 2,048-bit PHY takes ~30% of compute-die area Move PHY and controller into a custom base die Reclaim up to 25% of die area for compute Use the space for up to 30% more compute Speed up customized the base-die interface across memory vendors D2D / TSV / HCB UCIe was not built for HBM Next- gen class bandwidth density Cut D2D power Keep one D2D architecture from 2.5D to 3D hybrid bonding Prove 3D hybrid-bonding yield at volume Package thermals The HBM stack holds 57% of thermal resistance; HBM Next- gen reach > 2.0 W/mm². Reserve a silicon heat path at the D2D PHY Plan TIM, lid and cold plate with the base die Model heat flux above 2.0 W/mm² for HBM5 Validate cooling beyond 100 W/stack and > 2.0 W/mm². Ecosystem No single company can build custom HBM alone Align memory makers, foundries, OSATs and XPU designers Share thermal models and test data across the chain Define cHBM with more re- usable modules between different AI applications. Sources: Marvell newsroom (Dec 2024; Aug 2025); JEDEC JESD270-4 and HBM thermal-density reference; IEEE ECTC 2026; SK hynix iHBM release (May 2026); Hot Chips 2026. Details on earlier slides. Addressed today ¨ Additional effort needed
p13
© 2026 Marvell. All rights reserved. Checklist make high-performance cHBM work Base die and area HBM4’s 2,048-bit PHY takes ~30% of compute-die area Move PHY and controller into a custom base die Reclaim up to 25% of die area for compute Use the space for up to 30% more compute Speed up customized the base-die interface across memory vendors D2D / TSV / HCB UCIe was not built for HBM Next- gen class bandwidth density Cut D2D power Keep one D2D architecture from 2.5D to 3D hybrid bonding Prove 3D hybrid-bonding yield at volume Package thermals The HBM stack holds 57% of thermal resistance; HBM Next- gen reach > 2.0 W/mm². Reserve a silicon heat path at the D2D PHY Plan TIM, lid and cold plate with the base die Model heat flux above 2.0 W/mm² for HBM5 Validate cooling beyond 100 W/stack and > 2.0 W/mm². Ecosystem No single company can build custom HBM alone Align memory makers, foundries, OSATs and XPU designers Share thermal models and test data across the chain Define cHBM with more re- usable modules between different AI applications. Sources: Marvell newsroom (Dec 2024; Aug 2025); JEDEC JESD270-4 and HBM thermal-density reference; IEEE ECTC 2026; SK hynix iHBM release (May 2026); Hot Chips 2026. Details on earlier slides. Addressed today ¨ Additional effort needed
p14
© 2026 Marvell. All rights reserved. Call to action Custom HBM scales only as a co-designed: The base-die interface Close collaboration on custom base-die interface that works across memory vendors. Converge on one low-power D2D A D2D spec customized built for HBM, from 2.5D to 3D hybrid bonding. Co-design package thermals Memory makers, foundries, OSATs, and XPU designers plan TIM, lid, and cooling together Publish models and data Thermal models, stackup data, and interop results every vendor can build on