PDF 原檔：報告_OCP2026_聯發科_資料中心晶片效率_20261015_original.pdf
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| 檔名 | 頁 | 分類 | 親眼所見內容 |
|---|---|---|---|
報告_OCP2026_聯發科_資料中心晶片效率_20261015_p5.png |
p5 | 真資料圖 | 聯發科資料中心 roadmap 時間軸：2011 企業／資料中心投資、2016 企業交換器、2020 InFO 91x91mm² 量產、2022 Hybrid CoWoS 85x85mm² 量產、2024 長距客製 224G SerDes、2025 NVLink Fusion／Intel EMIB、2026 首個量產設計 Q4 出貨；下列 tape-out 節點 Intel I16、TSMC N3P、N2P、A14；底部封裝規模 MCP／1x／2x（量產）、3x+／5x+（設計中）、9x+（架構階段） |
報告_OCP2026_聯發科_資料中心晶片效率_20261015_p6.png |
p6 | 真資料圖 | 資料中心營收與 TAM：2026 由 $1 Billion 劃掉改為 $2 Billion；TAM $70B-$80B（年度標示 2028 被劃掉、改為 2027），聯發科市占 15%-20%；底部為晶圓、封裝、XPU、運算板、托盤與機櫃產品示意 |
報告_OCP2026_聯發科_資料中心晶片效率_20261015_p10.png |
p10 | 真資料圖 | 記憶體方案：SRAM、LPDDR/GDDR、Compute Near/In Memory、HBM/custom HBM、3D Memory stacking 五類；文字列延伸 LPDDR 資料中心能力、客製 SRAM、標準與客製 HBM 開發、3D 堆疊記憶體 |
報告_OCP2026_聯發科_資料中心晶片效率_20261015_p11.png |
p11 | 真資料圖 | 互連分三層：封裝內 die-to-die（UCIe、Mlink）、板上 chip-to-chip（高速 SerDes PCIe、uLED）、板外 board-to-board（高速 SerDes Ethernet、NPC/CPC 連接器、Co-Package Optics） |
報告_OCP2026_聯發科_資料中心晶片效率_20261015_p15.png |
p15 | 文字卡 | 策略夥伴：TSMC 列早期技術合作（先進節點、DTCO、CPO、SOW、早期 DTCO/STCO 與 3DBlock 夥伴、「worldclass D0 與產能配置」）；NVIDIA 列產品共同開發（車用、IoT、AI 超級電腦、資料中心、運算） |
報告_OCP2026_聯發科_資料中心晶片效率_20261015_p16.png |
p16 | 真資料圖 | 聯發科機櫃方案：上方兩種 ASIC shell 封裝圖——含客戶 IP 的 NVLink C2C Chiplet 版（綠色 NVLink Fusion Chiplet、NVHBM、Compute Die 四顆）與含客戶 IP 的 PCIe/Ethernet 版；中間為 MediaTek ASIC 運算托盤加 NVSwitch 托盤的機櫃，及 OCP 運算托盤搭乙太網路互連與交換器夥伴的三櫃排列 |
原始內容
p1
Copyright © MediaTek Inc. All rights reserved. Bhushan Chitlur The Silicon Heartbeat of the AI Economy The Efficiency Paradox in Next-Gen Data Center Silicon C H I E F A R C H I T E C T D A TA C E N T E R & A I
p2
Copyright © MediaTek Inc. All rights reserved. A I T R A I N I N G C O M P U T E C U M U L A T I V E D E M A N D ( R E L A T I V E , L O G S C A L E ) Conventional Scaling Cadence – Moore’s Law Era (2X every 18-24 months) AI Compute Demand Scaling (2X every 4-5 months) 101 103 105 107 109 1011 1013 1960 1970 1980 1990 2000 2010 2020 2030 2026-2030 values illustrative / extrapolated AI Compute Demand Is Accelerating Faster Than System Scaling A new strategy is required Needed to close the computing demand gap: • Investments in infrastructure • Innovations in architecture (Rack, Systems, XPUs, Memory, Interconnect)
p3
Copyright © MediaTek Inc. All rights reserved. Source: International Energy Agency and Goldman Sachs research The energy wall is a global, unavoidable constraint We need to make energy a first- class metric and design priority This constraint is our greatest catalyst for innovation Compute Energy Consumption World’s Energy Production 2010 2020 2030 2040 2050 10 16 10 18 10 20 10 22 J O U L E S / Y E A R 2X / 3-4 years +2% / years 2x / year Data Center electrical energy demand with current AI trends ➙ Hit Energy Wall before 2030 Data Center electrical energy demand with conventional compute ➙ Hit Energy Wall in 2040s Energy Is Our Most Significant Constraint … and Our Greatest Opportunity
p4
Copyright © MediaTek Inc. All rights reserved. Energy Efficiency Trends and Enablers Wave 1 : General Purpose CPU (<1x Reticle) • Single core/thread →multi-core/thread/virtualization • Moore’s Law scaling Wave 2 : GPU (<10x Reticle) • Embarrassingly parallel SW • Device/Node/Rack level parallelism (scale up/out) Wave 3 : Domain Specific Architectures (<40x Reticle) • Custom Compute pipelines • Heterogenous 2.5D/3.5D, Wafer scale integration • Optics and bidirectional interconnects E N E R G Y E F F I C I E N C Y A P P L I C A T I O N D I V E R S I T Y Trend : Compute cycles moving to custom silicon for better efficiency General Purpose CPU <0.5 KW GPU Upto 2+ KW Domain Specific Upto 5+ KW E N E R G Y E F F I C I E N C Y E N A B L E R S
p5
Copyright © MediaTek Inc. All rights reserved. V O L U M E P R O D U C T I O N A R C H I T E C T U R E P H A S E D E S I G N P H A S E Heritage of Innovation MCP 1x 2x 3x+ 5x+ 9x+ 2011 Enterprise & Data Center Investments 2016 Enterprise Switch Launched 2024 Long Reach Customizable 224G SerDes 2026 First production design ships in Q4 I P A N D P R O D U C T I N V E S T M E N T S 2020 World largest InFO PKG (91x91mm^2) volume production 2022 World 1st Hybrid CoWoS (85x85mm^2) volume production 2025 NVLink Fusion Intel EMIB D A T A C E N T E R F I R S T S I P A N D T E C H N O L O G Y E X P A N S I O N TSMC N3 I N T E L I 1 6 T S M C N 3 P T S M C N 2 P T A P E - O U T S - > T S M C A 1 4 Data Center Update
p6
Copyright © MediaTek Inc. All rights reserved. MediaTek Data Centered Solutions Overview Strong Data Center Growth – A Breakout Year $1 Billion (USD) $2 Billion (USD) 2 0 2 6 $70B-$80B 2 0 2 8 2 0 2 7 T A M 15%-20% M E D I A T E K S H A R E
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Copyright © MediaTek Inc. All rights reserved. W O R K L O A D S A R C H I T E C T U R E & S I L I C O N R A C K / C L U S T E R I N T E G R A T I O N MediaTek: One Partner from Workload to Rack F ro m Wo r k l o a d a n a l y s is to S i li co n to Ra c k d e s ig n , M e d ia Te k d e li v er s a f u l l y c o- o p t im i ze d , e n d - t o - en d d es i g n j o u r n e y to a c h ie v e th e b e st P er f / T CO Algorithmic analysis and innovations • Heterogenous silicon integration • 2.5D/3.5D/Wafer Scale • Memory, Optics • Custom Rack/Cluster design
p8
Copyright © MediaTek Inc. All rights reserved. 8 xPU MediaTek is investing in technologies and IPs to enable industry leading 10x+reticle designs solutions BETTER Perf/Watt and Perf/TCO with LARGER and more COMPLEX integrations
p9
Copyright © MediaTek Inc. All rights reserved. MediaTek Capabilities for Improving Compute Perf/W
p10
Copyright © MediaTek Inc. All rights reserved. 10 Memory: A Critical Enabler For xPU Training and inference specific memory innovations are critical for step jumps in performance HBM/custom HBM SRAM LPDDR/GDDR Compute Near Memory (CNM) Compute In Memory (CIM) 3D Memory stacking • Extending world’s best performing LPDDR solutions with DC capabilities • Leading edge best in class custom SRAM solutions • Standard and Custom HBM development • 3D stacked memory for large capacity and BW MediaTek memory solutions for xPU Perf/W and Perf/TCO
p11
Copyright © MediaTek Inc. All rights reserved. 11 MediaTek Interconnect Technologies and IP Interconnect solutions that span from die to rack for best in class perf, power and reach • UCIe • Mlink ON PAC KAGE Die-to-die interconnect xPU TECHNOLOGY • High-Speed SerDes (PCIe) • uLED ON BOARD Chip-to-chip interconnect xPU xPU System TECHNOLOGY • High-Speed SerDes (Ethernet) • NPC/CPC Connectors • Co-Package Optics OFF BOARD Board-to-board interconnect xPU xPU System xPU xPU System TECHNOLOGY
p12
Copyright © MediaTek Inc. All rights reserved. • MediaTek's investments drive advanced packaging solutions to enable large complex heterogeneous integration. • Advanced power delivery technologies (IVR, IPD) deliver higher power density and efficiency. • System technology co-optimization (STCO) capabilities across Power Delivery, Thermals, Performance, and Packaging. Advanced Packaging Technology Innovations Critical for achieving larger integration 2.5D < 1 0 , 0 0 0 S q . m m S i 3.5D 1 0 , 0 0 0 - 2 0 , 0 0 0 S q . m m S i
p13
Copyright © MediaTek Inc. All rights reserved. MediaTek Solutions to Scale Cloud Compute Co-optimization across three pillars: Compute, Scale-up, and Scale-out Interconnect Supports industry standard (E.g. UALink, ESUN, UEC) and proprietary interconnect (E.g. NVLink) solution Heterogeneous integration to enable new system use-cases with improved performance/TCO
p14
Copyright © MediaTek Inc. All rights reserved. The de facto unit of compute consumption Greater value through hardware/software vertical integration for Cloud AI and enterprise customer Power, thermals and reliability dictate the performance Effective monetization requires optimization of rack across different usages Perf/TCO and Reliability at scale are critical metrics to achieve best-in-class data center efficiency The Rack Building blocks of data centers
p15
Copyright © MediaTek Inc. All rights reserved. 15 Strategic Partnerships with Industry Leaders P R O D U C T C O - D E V E L O P M E N T • Automotive • IoT • AI Supercomputer • Data Center • Compute E A R LY T E C H N O L O G Y E N A B L E M E N T • Advanced Nodes | DTCO CPO | SOW • Early DTCO/STCO and 3DBlock partner • Our collaboration has yielded worldclass D0 and capacity allocations
p16
Copyright © MediaTek Inc. All rights reserved. MediaTek Rack Solutions MediaTek ASIC Compute Tray and NVSwitch Tray in rack. MediaTek ASIC OCP compute tray with Ethernet Interconnect and Ethernet Switch partners ASIC Shell w/ Customer IP PCIe/Ethernet in MediaTek ASIC ASIC Shell w/ Customer IP NVLink C2C Chiplet in MediaTek ASIC Leadership Compute Tray & Scale-Up Co-engineer custom rack solutions for leadership performance and power
p17
Copyright © MediaTek Inc. All rights reserved. T E C H N O L O G Y L E A D E R S H I P Process, Packaging, Power, Connectivity S T R O N G I P P O R T F O L I O SerDes, Optical, High Speed I/O, Die to Die Interconnect, Memory C O L L A B O R A T I V E E C O S Y S T E M Partnerships & Global Supply Chain TSMC, NVIDIA, Intel, SK Hynix, Micron, Samsung S T R A T E G I C E N G A G E M E N T M O D E L Fast Time to Market Flexibility Across the Technology Lifecycle The Value of MediaTek Global Scale Technology Optimization Relentless Execution
p18
Copyright © MediaTek Inc. All rights reserved. 1 Co-Optimize across the stack Compute, memory, interconnect, and packaging - one roadmap. 2 Support Open & Standards-based ecosystems E.g. ESUN, UAL, UEC, NVLink Fusion , and OCP 3 Efficiency at scale as the scoreboard Perf/Watt and Perf/TCO — not peak FLOPs Sustaining the Next Decade of AI Infrastructure Growth
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