PDF 原檔：報告_OCP2026_緯穎_AyarLabs_CPO光學ScaleUp機櫃_20261015_original.pdf
講者公開簡報（OCP 官方 Recorded Content 頁提供下載）。文字以 PyMuPDF 逐頁抽取，
### p<n>為頁碼；圖表內容見原檔。
圖片清單（已驗證 2026-10-19）
| 檔名 | 頁 | 分類 | 親眼所見內容 |
|---|---|---|---|
報告_OCP2026_緯穎_AyarLabs_CPO光學ScaleUp機櫃_20261015_p3.png |
p3 | 文字卡 | 1024 ASIC scale-up pod 到封裝的整合層級與五項設計考量：兩個熱域、ELSFP 前面板可熱插拔、光纖結構、分散電源樹（48V／±400V／800V 對 3.3V）、跨供應商測試邊界 |
報告_OCP2026_緯穎_AyarLabs_CPO光學ScaleUp機櫃_20261015_p5.png |
p5 | 真資料圖 | 光纖佈線架構：每個運算機櫃 32 個 1OU 運算托盤經櫃內 shuffle box，連到每個 scale-up 交換機櫃（32 個 1OU 交換托盤） |
報告_OCP2026_緯穎_AyarLabs_CPO光學ScaleUp機櫃_20261015_p6.png |
p6 | 真資料圖 | L10 運算托盤拆解圖：805 × 537 × 46.5 mm，含 2 塊 CPO ASIC 板、16 個 ELSFP、ELSFP 板、CPU 板、OCP 3.0 NIC、12V→3.3V PDB、DC-SCM、冷板與歧管 |
報告_OCP2026_緯穎_AyarLabs_CPO光學ScaleUp機櫃_20261015_p7.png |
p7 | 真資料圖 | 加速器多晶片封裝：8 顆光引擎、8 組 HBM、UCIe-A 轉 UCIe-S 的 I/O 轉換小晶片；標示每顆加速器 200+ Tbps scale-up 頻寬、微環架構、OCI-MSA Optical PHY |
報告_OCP2026_緯穎_AyarLabs_CPO光學ScaleUp機櫃_20261015_p8.png |
p8 | 真資料圖 | 封裝熱模擬：衝擊式冷板、流量 4.5 LPM，Tj-max 為 SoC 112°C（規格 125）、HBM4 75.4°C（95）、IO 59.9°C（125）、OE 69.8°C（100） |
原始內容
p1
Open Rack-Scale Optical Infrastructure for AI Scale-Up with Co-Packaged Optics Kinny Chen Sr. Manager of Pioneering Center, Wiwynn Vishal Chandrasekar Director of Product Management, Ayar Labs
p2
Bigger models demand better efficiency, not just more ASICs (xPUs) The scale-up domain size directly shapes tokens/sec/cluster Why this matters Larger models need larger scale-up domains to stay efficient Tokens/sec/cluster is the metric that actually matters at fleet scale 1024-ASIC Scale-Up Pod projects ~10x higher system performance vs. the smallest evaluated config Communication-bound workloads benefit most from expanding scale-up reach across multi-racks This is why we design top-down: start from the 1024-ASIC target, then work down through rack, tray, fiber, and multi-chip package.
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Integration Levels and Design Considerations We drill top-down: from the 1024-ASIC scale-up pod to the ASIC + OE package 1024-ASIC SCALE-UP POD RACK / L11 L10 TRAY ASIC + OE PACKAGE Compute Tray (ELSFP + CPU + ASIC + OE) In-chassis Fiber Harness Patch Panel (MPO/MMC/EBO) CPO Switch Rack Network Rack /DC Structured Cabling 1 Two thermal domains ASIC/OE heat vs. ELSFP temperature window 2 Front-panel consumable ELSFP must remain hot-pluggable and reachable, reserved space for NIC, SSD, and BMC 3 Fiber as structure Bend radius, PM Fiber orientation, service loops 4 Fragmented power tree 48 V/±400V/800V rear input versus 3.3 V at the front 5 Cross-supplier test boundary Loss can originate across multiple ownership points
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Level 1 — The 1024 Scale-Up Pod Translate high-density CPO I/O into structured rack-to-rack infrastructure 1024-ASIC SCALE-UP POD RACK / L11 L10 TRAY ASIC + OE PACKAGE AI Rack Scaling Across Racks AI Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute AI Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute AI Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute AI Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Scale-up s/w Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch … … Scale-up s/w Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch • Single-stage scale-up topology (ASIC-Switch-ASIC) • Scale-up Switch Requirement 1024 bi-direction signal within same optical I/O spec as Compute Switch Switch Switch Switch Switch Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Switch Switch Switch Switch Compute Compute In-rack Scaling
p5
Level 2 — Fiber Routing Architecture Organize optical endpoints through a hierarchical physical structure 1024-ASIC SCALE-UP POD RACK / L11 L10 TRAY ASIC + OE PACKAGE • 32 × 1OU scale-up switch trays and a shuffle bus per switch rack AI Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Compute Shuffle box Shuffle box Shuffle box Each compute rack connects to every switch rack Scale-up s/w Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Shuffle box Shuffle box Scale-up s/w Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Shuffle box Shuffle box • Every ASIC connects to every scale-up switch • At least one fiber pair provides a bidirectional link to each switch rack • All ASIC scale-up fibers connect to the in-rack shuffle box • Each compute rack houses 32 × 1OU compute trays Scale-up s/w Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Shuffle box Shuffle box
p6
Level 3 — The L10 Layout & Design Cold Plate & Inner Manifold DC-SCM DC-SCM Interposer 2x CPO ASIC Board 16x ELSFP ELSFP Board 12V → 3.3V PDB OCP 3.0 NIC SFF CPU Board 805mm 46.5mm 537mm Fiber Cables & Guiding Parts 1024-ASIC SCALE-UP POD RACK / L11 L10 TRAY ASIC + OE PACKAGE Tray design integrates optics, power, electrical signals, cooling, and control
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Level 4 — Inside the Accelerator Multi-Chip Package Optical conversion moves into the package, along with thermal and repair consequences 1024-ASIC SCALE-UP POD RACK / L11 L10 TRAY ASIC + OE PACKAGE 8 Optical Engines on-package ➔High bandwidth, high radix ➔Low latency ➔Low end-to-end energy I/O protocol converter chiplets ➔UCIe-A to UCIe-S ➔Scale-up protocol endpoint 8 HBM Stacks ➔Memory bandwidth expansion ➔Multi-rack scale-up connectivity ➔200+ Tbps scale-up bandwidth per accelerator ➔Hundreds of scale-up links per accelerator ➔Microring architecture, OCI-MSA Optical PHY ➔UCIe-S die-to-die interface
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Level 4 — Package Thermal Simulation Thermal cross-talk onto the optical engines is negligible 1024-ASIC SCALE-UP POD RACK / L11 L10 TRAY ASIC + OE PACKAGE Use Impingement type Cold plate thermal solution Active Surface Temperature (Flow rate = 4.5 LPM) SoC IO IO HBM4 HBM4 IPD IPD IO IO OE OE OE OE OE OE OE OE HBM4 HBM4 HBM4 HBM4 IPD IPD HBM4 HBM4 SoC Ta = 25 (oC) , R-TIM=5.2 (W/mK) Item Spec Tj (oC) Flow rate 4.5 LPM Tj-max (oC) SoC 125 112 HBM4 95 75.4 IO 125 59.9 OE 100 69.8 ASIC Cold plate Flow rate: 4.5 LPM Pressure drop: 11.2 kPa OE Cold plate Flow rate: 4.5 LPM Pressure drop: 18.8 kPa The impingement cold plate can meet the spec
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Call to Action How do we deploy Short Reach Optical Interconnects for scale-up? 1. Common Physical Interface 2. Deployment and validation practices 3. System telemetry 4. Reference rack design
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LIVE CPO TRAY at #C74 x
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