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圖片清單（已驗證 2026-10-19）

原始內容

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Toward quantum supercomputing with IQM quantum processors Khadijeh Sona Najafi, Ph.D. Quantum Solution Manager, IQM

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→ Algorithm and Application Development → Software & Workflow → Scalable Hardware + Error Correction + HPC Integration IQM: Full stack quantum computers integrated with HPC

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2022 2025 2024 2023 Crystal-5 2Q fidelity Crystal-20 Median 99.76% Best 99.85 ± 0.02% 2Q fidelity Star-6 Crystal-54 2Q fidelity Star-24 CZ median 99.26% Best 99.45% MOVE median 99.66% Best 99.75% Q-R fidelity Crystal-150 IQM Constellation 2026 Median 99.47% Best 99.85% Retired Coming soon Coming in 2026 IQM Star High connectivity IQM Crystal Parallel gates Note: The timeline shows when the first-version of the QPU was developed, and the fidelities are based on the latest available data Median 99.65% Best 99.74 ± 0.02% Q-Q fidelities 97-98% Constellation Q-Q fidelities now well beyond 99% CZ median 99.37% Best 99.52% Hero 99.67% Ref 1 CZ 2 CZ 3 CZ 4 CZ

of Cliffords

Avg. GG probability

of interleaved CZs

Sequence fidelity Hero 99.67% build on IQM Constellation Theory: arXiv:2603.10699 Deployments drive learning and architectural progress

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Timeline corresponds to first demonstration systems. First on-premise delivery is 12-18 month available from first demonstration. Processor layouts are for illustrative purposes only and do not represent the actual design. Two-qubit-gate error refers to demonstration devices consisiting of two qubits and a coupler only. The fidelities get transferred system-level with a delay. Fault-tolerant quantum computing requires massive scaling Development Roadmap

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now projected → 1947 transistor 1958 integrated circuit 1965 Moore's law 1971 Intel 4004 1976 Cray-1 vector 1980 8087 coprocessor 1989 FPU on die 1994 clusters, MPI 1997 teraflop c. 2005 Dennard scaling ends 2008 petaflop 2022 exascale 2025 JUPITER 1999 first “GPU” 2001 programmable shaders 2004 GPGPU 2007 CUDA 2010 ECC; GPU tops TOP500 2012 AlexNet 2016 NVLink 2017 tensor cores 2023 coherent CPU + GPU 2024 APU tops list 2025 AI factories 2027+ AI gigafactories 1982 Feynman 1994 Shor's algorithm 1995 QEC 1999 SC qubit 2007 transmon 2012 surface code 2016 cloud access 2019 supremacy 2021 Helmi (VTT) 2022 Helmi + LUMI 2023 utility claim 2024 Q-Exa, Willow 2025 real-time QEC 2026 ORNL, CINECA NISQ, ≲150 qubits Early FTQC, 1k–100k NISQ utility, 150–1k FTQC Utility, ≥10⁵ 1950 1960 1970 1980 1990 2000 2010 2015 2020 2025 2030 2035 Sona. Najafi et al, in preparation From quantum processors to quantum supercomputer

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Why integrating quantum & HPC?

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 Exact solutions of many particle physical systems is computationally is challenging  Different classical and quantum approximations such as MD,DFT, DMFT, DMRG, Quantum Monte Carlo require HPC resource  In some regime such as strong correlation or nonlinear regimes, the approximation methods fail or do not have required accuracy Sona. Najafi et al, in preparation Demand of computing has reached beyond classical resources

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T I E R 1 · T O P O F S T AC K Applications Every target workload is a hybrid workflow, not a circuit. The classical stages set the time to solution. Materials science Quantum chemistry High-energy physics QML Differential equations The first three make up over 50% of NERSC’s production workload today. The same analysis proposes execution time of large-scale quantum workflows, rather than qubit count, as the parameter to optimise. CL AS S ICA L D EM AN D Bulk Large partitions, hours to days. Batch scheduling is adequate. Tier 1: Camps et al., arXiv:2509.09882 (NERSC/LBNL, 2025) · Tiers 2–3: Seelam et al., arXiv:2603.10970 (2026) Demand of computing has reached beyond classical resources DFT Lattice QCD Climate Fusion - PIC Scalable Solvers N-Body (MD) Fusion - Multiphysics Quantum Chemistry 30.9% 18.6% 12.8% 9.1% 8.6% 8.1% 4.8% 2.6%

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Three tiers of the stack, three independent reasons. Each generates classical work on its own, and the character of that work changes as you descend. T I E R 1 · T O P O F S T AC K Applications Every target workload is a hybrid workflow, not a circuit. The classical stages set the time to solution. Materials science Quantum chemistry High-energy physics QML Differential equations The first three make up over 50% of NERSC’s production workload today. The same analysis proposes execution time of large-scale quantum workflows, rather than qubit count, as the parameter to optimise. CL AS S ICA L D EM AN D Bulk Large partitions, hours to days. Batch scheduling is adequate. T I E R 2 · M ID D L E Mitigation and compilation The layer that turns an unreliable device into a usable one, and the layer whose cost scales worst. Zero-noise extrapolation Probabilistic error cancellation Noise-aware transpilation Sampling overhead grows exponentially in the circuit error rate, so the classical burden rises faster than the qubit count. Compilation consults live calibration data, which makes it a runtime service rather than a build step. CL AS S ICA L D EM AN D Burst Many circuits per observable, seconds to minutes. Needs co-allocation and sessions. T I E R 3 · B A S E Error correction Not a post-processing step. A classical computation running continuously, under a deadline set by physics. Syndrome decoding Feed-forward Logical scheduling Decoder throughput must at least match the syndrome rate or backlog grows without bound, forcing the processor to idle while further errors accumulate. Worst-case latency, not average, is the figure of merit. CL AS S ICA L D EM AN D Real-time Microseconds, inside the coherence window. Deterministic interconnect required. Tier 1: Camps et al., arXiv:2509.09882 (NERSC/LBNL, 2025) · Tiers 2–3: Seelam et al., arXiv:2603.10970 (2026) Why integrate Quantum with HPC?

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NISQ ≲150 NISQ Scaling 150–1k Early FTQC 1k–100k FTQC Utility ≥ 10⁵ Applications and Algorithms hybrid algorithms compensate for few qubits hybrid workflows at larger scale early fault-tolerant algorithms algorithms expressed in logical qubits Compilation, Error Mitigation and Pulse Control vendor stack, local control AI-assisted compilation; mitigation overhead compilation to logical operations compilation to a quantum ISA Quantum Error Correction demonstrators only demonstrators only real-time decoding on HPC and AI decoding at scale; may migrate in-device Physical Layer CPU, GPU, QPU, cryogenics, wiring and control electronics: internal to the quantum + HPC system in every era Stand-alone Deeply integrated HPC + Quantum Sona. Najafi et al, in preparation Integration is inevitable

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How can we integrate quantum & HPC?

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VTT’s quantum computer HELMI (“Pearl”) has been connected with the pan-European supercomputer LUMI (“Snow”), hosted by CSC - IT Center for Science. The connection to Europe’s most powerful classical supercomputer enables the best possible use of the quantum computer’s computing power. This is the first time in Europe that this kind of hybrid service connecting a supercomputer and a general-purpose quantum computer is opened for researchers. Demonstration in Slush 18.11.2022 HPC-QC integration since 2022

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Our HPC Guidebook Detailed learnings from one of the first HPC+QC systems  Superconducting qubits have stricter facility requirements than HPC, but these can be managed by careful site selection  IQM Radiance 20 operated for >150 days without any human touch except for the weekly 5-minute liquid nitrogen refill. Download the article to learn more! https://arxiv.org/abs/2509.12949

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IQM leads quantum–HPC integration on-prem QPUs European-built 2021 VTT Q5 “Helmi” 5-qubit star · Espoo 2022 Helmi ⇄ LUMI first EU hybrid service 2023 VTT floor upgrade 20-qubit processor floor 2024 Q-Exa · LRZ 20-qubit + SuperMUC-NG 2025 VTT Q50 53-qubit coupled to LUMI 2025 VLQ · IT4I 24-qubit star + Karolina 2025 CESGA · Galicia 54-qubit Radiance · Spain 2026 Euro-Q-Exa · LRZ 54-qubit Radiance · Slurm 2026 NOX · CINECA 54-qubit + Leonardo 2026 Pathfinder · Oakridge 20-qubit · first US install 2026 Real-time QEC GPU decode over NVQLink 2027 LUMI-IQ · CSC 150-qubit · Halocene H4 2026 Aalto University · LUMI 20-qubit · Espoo Contracted, not yet delivered Integrated Deployment status: Sona. Najafi et al, in preparation Already integrated with 11 quantum supercomputer

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T I E R T Tight real-time, ≲ 100 µs The decoder sits inside the coherence budget. No scheduler, no shared network and no general-purpose operating system may appear on this path. ON E TI MING DO MAI N T I E R M Intermediate co-scheduled, 0.1 ms – 1 s Quantum and classical resources are held in a single job. The scheduler must see device availability and calibration state as first-class attributes. ON E AL LO CAT ION, O NE SCH E DUL ER T I E R L Loose federated, ≳ 1 s Access is a service across an institutional boundary. What remains hard is identity, accounting, data movement and the reconciliation of two queues. SE PAR AT E S ITE S, H OS TE D AC CES S hosted access off the real-time path dedicated link QPU + control HPC AI hosted on site QPU HPC AI hosted service quantum site HPC site AI site QPU HPC AI Sona. Najafi et al, in preparation Three regime of integration

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Tier T — tight real-time Tier M — intermediate co-scheduled Tier L — loose federated qubit coherence wall QEC syndrome decoding (surface / qLDPC) mid-circuit measurement → feed-forward real-time calibration and drift tracking circuit knitting, sample-based diagonalisation adaptive / dynamic circuits VQE, QAOA parameter update loop batch sampling, error-mitigation post-processing ensemble sweeps, benchmarking campaigns NVQLink-class interconnect, ≈ 4 µs round trip co-located QPU, shared batch scheduler hosted service access, separate queues 10 ns 1 µs 100 µs 10 ms 1 s 100 s 100 h TB/s GB/s MB/s kB/s classical quantum round-trip latency budget τ [s] Each regime is a different engineering problem: Tier T an interconnect problem, Tier M a scheduler problem, Tier L a federation and identity problem. Solving one does not solve the others. Sona. Najafi et al, in preparation The coupling regime space

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1 Applications I1 workflow definition 2 Algorithms & kernels quantum and classical methods I2 job submission 3 Orchestration I3 resource allocation 4 Hybrid compilation & runtime what each device executes I4 device interface (QDMI) 5 Device interface & control firmware on the control path I5 control, readout & deterministic link 6 Hardware resources connected in signal order Quantum simulation Quantum AI Optimisation PDEs QUANTUM CLASSICAL NISQ: VQE, QAOA, QNN FTQC: QPE, Grover, Shor Qrisp . Qiskit · Cirq · PennyLane · CUDA-Q DFT · DMFT · DMRG · QMC BLAS · ITensor · Quantum ESPRESSO Scheduler Workflow manager Gateway / API Accounting & identity NISQ toolchain transpilation · mitigation · post-processing FTQC toolchain FT compiler · emulator · assembler Classical toolchain LLVM · CUDA / HIP · MPI shared IR (MLIR) · hybrid runtime: CUDA-Q, Catalyst + Backline Quantum device interface Pulse sequencing Primary decoder NVQLink · Backline link HPC NODES CPU GPU Low-latency NIC RoCE / RDMA NVQLink · ERNIC ROOM-TEMPERATURE CONTROL FPGA controller · sequencer AWG / DAC drive pulses Digitiser / DAQ ADC · demodulation clock & timing distribution CRYOSTAT · 4 K → 10 mK Drive lines attenuated Amplifiers TWPA · HEMT QPU CROSS-CUTTING Calibration, telemetry & feedback calibration state device telemetry monitoring & logging AI-assisted tuning and decoding provenance for results state flows up, corrections flow down Sona. Najafi et al, in preparation A reference architect for quantum supercomputer

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Applications of quantum supercomputer

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In every one of these flows the QC is accelerator and the HPC/AI cluster carries the load Quantum + HPC + AI 01 · QUANT UM CHEMIST RY Next-generation batteries Volkswagen Group × IQM • Hybrid AFQMC models Li-ion electrolyte breakdown • Chemical accuracy using 13 of 32 qubits 02 · BIOLOGY & HE ALTH CARE Cancer drug research Algorithmiq × IQM • Energy gaps of BODIPY photosensitizers on IQM Emerald (54 qubits) • ~100× better precision than another superconducting QPU 03 · AI FOR QUANTUM Error-correction decoders AI cluster beside the QPU • GPU-trained neural decoders turn syndromes into corrections • Low-latency inference beside the cryostat 04 · QUANT UM FOR AI Quantum machine learning Global insurance company • Quantum kernels flag anomalous behaviour for fraud detection • Quantum transformers: comparable accuracy, fewer parameters 05 · PDE Physical simulation • Navier–Stokes, plasma, heat and ion transport • Black–Scholes pricing and seismic waves Sona. Najafi et al, in preparation Applications of quantum supercomputer

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Towards simulation of next generation batteries arXiv:2606.19239 • Battery materials are strongly-correlated • Computational cost too high for practical use • Improved SOTA runtime estimates by 248x using LUMI supercomputer • Largest demonstration of this hybrid method Approximations cannot capture the behavior of strongly-correlated systems, such as battery materials Need to understand the reaction pathways QC-AFQMC is a hybrid method that is a quantization of a promising classical method. While efficient, it is still too slow for any practical chemical system Combining algorithmic and implementation improvements, we bring the projected runtime for a 100-orbital system down to a couple years from half a millennium Contextualize the work with a reaction pathway for lithium-air batteries that fitted to 40 qubits

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BA TTE RY C HEMIST RY · V W × IQ M Towards simulating next- generation batteries T H E PR O B L E M Battery materials are strongly correlated, so approximations miss their reaction pathways. Hybrid QC-AFQMC captures them, but its classical post-processing was too slow for practical systems. T H E R E SU L T Algorithmic and implementation gains cut projected runtime up to 248×: a 100-orbital system drops from ~500 years to ~1.8 years on 10M CPU cores. Largest run: a lithium-air (Li₂O₄) pathway on 40 qubits (simulated data, LUMI). Nappi et al., arXiv:2606.19239 IN DUSTRI AL CHEMI STRY Compact wavefunctions from quantum-selected CI T H E PR O B L E M Selected CI needs a configuration subspace that is both small and well chosen. Sampling it is classically hard exactly where static correlation matters, at bond dissociation. T H E R E SU L T Potential energy curve of silane, SiH₄, on 42 qubits. At large separation the subspace is over 200× smaller than conventional SCI with comparable energies. Final energies are solved on HPC, so hardware noise never enters. Weaving et al., arXiv:2509.02525 SO LUTI ON CHEMI STRY Subspace, embedding and classical MD combined T H E PR O B L E M A reaction in solution can span ~10⁵ atoms. Almost none need quantum treatment, but deciding which do, and handing them over cleanly, is the hard part. T H E R E SU L T Proton transfer (solvated Zundel cation) through a multiscale workflow: classical MD, projection-based embedding and qubit- subspace reduction feeding QSCI on a QPU. Run on IQM’s 20-qubit Q-Exa with LRZ compute. Bickley et al., arXiv:2505.16796 MA TERI A LS SCI ENC E Quantum-assisted ghost Gutzwiller ansatz T H E PR O B L E M Ghost Gutzwiller matches dynamical mean- field theory at lower cost, but is bottlenecked by the embedding density matrix, which must converge in a self- consistent loop. T H E R E SU L T The metal-to-insulator transition of the Fermi-Hubbard model on a Bethe lattice, captured with 24 qubits and 11 ghost orbitals on IQM Garnet, using an SCI basis of as little as 1% of the CI states. Sriluckshmy et al., arXiv:2506.21431 Examples of hybrid workflows on IQM machines

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The path toward FTQC

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The first institutions to demonstrate lattice surgery at scale, publish decoder benchmarks and build production-grade QEC tooling will define the standards the field builds on. Memory experiment Logical qubit survives longer than a physical qubit 1 Stability experiment Syndrome processing and decoding stay reliable over long periods 2 Lattice surgery Entangling operations between logical qubits 3 T-state injection Inject a non-Clifford resource state into the code 4 T-state distillation Turn noisy magic states into high-fidelity ones 5 Arbitrary gates Fault-tolerant execution of quantum circuits 6 The path toward fault-tolerance

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WEL L-KNOWN OPTION Square grid + surface code • 4 neighbours per qubit: ideal for the surface code, inefficient for colour codes or qLDPC • Needs a vast number of physical qubits to protect a few logical qubits NEW HARDWA RE COMPONE NTS Connectivity beyond the square grid • IQM Star: high connectivity through a central resonator, but limited parallelism slows QEC cycles at scale • Tunable couplers + resonators give each qubit many native partners Beyond the surface code

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HARDWARE · CONSTELL ATION TOPOLOGY • 12 native neighbours per qubit, instead of 4 on a square grid • High parallelism with high-fidelity two-qubit gates • A platform to research new QEC codes such as quantum LDPC (qLDPC) CODE · BARBEL L qLDPC A “barbell” Few near-local long couplers (one per every other qubit) join planar Constellation sites • Limited number of near local couplers • Hardware complexity stays constant as code distance grows • 8x lower cost in resources, high efficiency compared to rotated surface code • 30 physical qubit to 1 logical qubit Choe et al., Barbell Codes: qLDPC Codes for Superconducting Quantum Hardware, arXiv:2606.06062 (2026). Circuit-level noise simulations; surface-code comparisons per IQM announcement, 9 June 2026. IQM constellation and barbell code

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The next-generation product line for quantum error correction research QEC RESEA RCH: UNT IL NOW A CLOSED FIE LD • Meaningful QEC experiments have run only on proprietary systems, out of reach of the HPC community • Halocene puts this research in the hands of HPC centres: learn, educate, research and create IP on the path to fault tolerance 150 qubits in the first system; installs from end of 2026 5 logical qubits for research, with Clifford gates Open QEC stack, modular decoders Introducing IQM Halocene QEC code implementations Compilers Error decoders (AI) Quantum algorithms HPC integration software Calibration tools Build commercial applications across key domains

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NISQ early fault tolerance long-term fault tolerance 0 – 50 50 – 200 200 – 1000

1000 20 50 200 1000 10⁻¹ 10⁻² 10⁻³ 10⁻⁴ 10⁻⁵ 10⁻⁶ physical qubits ② HPC + QPU + AI integration 2026 ① utility scale 2025–26 ③ scaling to 1000 2026+ ④ logical qubits 2026+ four transitions, one window T IE R 1 · AP PL I CA T IO N S New algorithms, not ported ones The algorithms that will use a 1000-qubit machine coupled to an HPC centre have not been written. Existing ones were designed for a device in isolation, and must be rediscovered for the hybrid setting. algorithm discovery workflow adoption T IE R 2 · MI T IG AT I O N AN D CO M PIL AT I O N Tools that survive the next decade of scale Mitigation overhead grows faster than the device. Above 100 qubits, compilation and characterisation need AI-assisted methods to stay tractable, plus workflow integration that makes the QPU a scheduled resource. AI-assisted compilation workflow integration T IE R 3 · H AR DW A RE A N D F AC IL I T Y QPU scaling and the AI factory Scaling 150 to 1000 physical qubits needs new technology, not more of the same. In parallel, the QPU has to be integrated into facilities being built around quantum, HPC and AI together. QPU scaling HPC + AI factory integration What is next for quantum supercomputer?

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Spain US Italy Germany Finland Poland South Korea Taiwan Czech Republic Japan Join the Future Of Supercomputing Sona Najafi, Quantum Solution Manager sona.najafi@iqm.tech

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Superconducting qubits as building blocks for quantum information processing Superconducting quantum processor structure • Superconducting QPUs are high-end microwave ICs (4 – 8 GHz) • Superconducting ultra-low-loss thin-film structures (CD ≥ 1 µm) as on-chip microwave building blocks • Josephson junctions as core qubit elements • Infrastructure for high-performance microwave connectivity Couple r qubit Qubit 1 Qubit 2 Coupled structure with two qubit; schematics and microphotographs. Quantum processing unit (QPU) as “artificial atom” lattice. Example topology of IQM Crystal-54 with 54 qubits and 90 couplers. nm F. Marxer et al., PRX 4, 010314, 2023 Superconducting qubits and processors

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(a) Backline Xanadu · AMD TIER T · HETEROGENEOUS COPROCESSING PennyLane (Python) Triton / Gluon decoder kernels Catalyst (MLIR · LLVM) Backline runtime · tier routing FPGA (Versal) · primary decoder ERNIC · RDMA NIC CPU (Threadripper) · backup decoder GPU (Instinct) · backup decoder distributed > 100 µs real-time 1 ns – 1 µs synchronous 1 – 100 µs LATENCY TIER RESOURCES controller + coprocessors FPGA RDMA CPU GPU QPU hosted API, off the real- time path controller mean round trip, FPGA → coprocessor → FPGA: 2.3 µs (CPU) · 4.4 µs (GPU) (b) NVQLink NVIDIA · Quantinuum · IQM with Zurich Instruments TIER T · LOGICAL QPU CUDA-Q (C++ / Python) device_call real-time callbacks CUDA-Q compiler (MLIR) CUDA-Q QEC library System controller (FPGA / RFSoC) RoCE FPGA core Real-time host (GH200) nv-qldpc-decoder (GPU) host program pulse processing sub-µs real-time callbacks ≈ 4 µs LATENCY TIER RESOURCES logical QPU QSC RoCE GH200 QPU hosted API, off the real- time path controller mean round trip over RoCE: 3.84 µs (σ = 0.035 µs, n = 1000) Both place classical decoding inside the timing domain of the processor; they differ in the coprocessor and in the programming path from the host language to the controller. Sona. Najafi et al, in preparation Real time couplings

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(a) Gateway access TIER L · SEPARATE SITES HPC site quantum site User · SDK HPC scheduler Hosted API / gateway QDI Classical process Control system RESOURCES hosted API (gateway) quantum site HPC site (b) Scheduler-integrated TIER M · 1:1 User · SDK Hosted API Scheduler Classical process QDI Control system 1 direct 2 hybrid RESOURCES hosted API on site direct hybrid HPC QPU (c) Shared QPU TIER M · MANY:1 User · SDK Hosted API Scheduler Classical × N GW middleware: bookkeeping QDI Control system RESOURCES hosted API + bookkeeping HPC × N QPU (d) Multi-QPU TIER M/L · MANY:MANY User · SDK Hosted API Scheduler Classical × N QDI QDI QDI Control Control cloud QPU RESOURCES hosted API cloud QPU HPC QPUs Component paths follow the IQM deployment diagrams: (1) direct offload from the scheduler, (2) hybrid offload from a running classical process. Dashed boxes mark site boundaries. Sona. Najafi et al, in preparation Deployment variant of quantum supercomputer

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Towards simulation of next generation batteries Lithium-air batteries have 5.0x theoretical energy density of Li-ion batteries Battery materials are strongly-correlated Approximations cannot capture the behavior of strongly-correlated systems, such as battery materials Need to understand the reaction pathways Computational cost too high for practical use QC-AFQMC is a hybrid method that is a quantization of a promising classical method. While efficient, it is still too slow for any practical chemical system Improved SOTA runtime estimates by 248x using LUMI supercomputer Combining algorithmic and implementation improvements, we bring the projected runtime for a 100-orbital system down to a couple years from half a millennium Largest demonstration of this hybrid method Contextualize the work with a reaction pathway for lithium-air batteries that fitted to 40 qubits arXiv:2606.19239

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Noise sets a hard ceiling on what a quantum computer can do without error correction. • Noise makes deep circuits effectively shallow: only the last O(log n) layers still influence the output. • Adding qubits and depth without QEC stops adding computational power. • QEC encodes each logical qubit in many physical qubits and corrects errors faster than they accumulate. • How efficient QEC is depends on the hardware connectivity and on fast classical decoding on HPC/AI. Effective depth of noisy circuits. For most circuits with (possibly non-unital) noise, only the last O(log n) layers significantly influence expectation values; n is the number of qubits. Mele, A.A., Angrisani, A., Ghosh, S. et al. Noise-induced shallow circuits and absence of barren plateaus. Nature Physics (2026). doi:10.1038/s41567-026-03245-z Why we need error corrections?

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2 4 6 Quantum error correction (QEC) is crucial in reaching fault- tolerant quantum computing, and its efficiency depends on hardware connectivity. Previous approaches fall short: • Most processors use square lattice connectivity, ideal for surface code QEC but inefficient for newer codes like color codes or qLDPC. • Surface code needs a vast number of physical qubits to protect few logical qubits. • IQM Star provides high connectivity but limited parallelism, slowing QEC cycles at scale. Beyond surface code

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• Effective 12-to-1 connectivity instead of 4-to-1 • High parallelism, high connectivity, high fidelity 2 qubit gate • Ability to research NEW QEC codes such as quantum low density parity check (qLDPC) codes A “barbell” • Limited number of near local couplers • Utilize IQM new quantum error correction code, the Barbell Code • 8x lower cost in resources, high efficiency compared to rotated surface code • 30 physical qubit to 1 logical qubit IQM Constellation & Barbell code

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Introducing IQM Halocene The next gen product line for quantum error correction research Learn, educate, research, and create IP on the critical path to quantum error correction. Join cutting-edge researchers to reach fault-tolerant quantum computing Build commercial applications across key domains From IP creation to commercialization QEC code implementations Compilers Error decoders (AI) Quantum algorithms HPC integration software Calibration tools