報告_JPM_半導體測試介面_Initiation_20261026

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原始內容

J PMORGAN

Taiwan Semiconductor Test Interface

Beneficiaries of rising AI testing intensity and supply chain localization: Initiate on WinWay (OW) and PI (N)

We initiate on WinWay (6515 TT) at OW and MPI (6223 TT) at N, adding to our existing coverage of CHPT (6510 TT, OW). We are constructive on the sector's multi year outlook as AI drives longer test times, higher pin counts, and broader SLT coverage, with Taiwan interface suppliers key beneficiaries of localization. We favor WinWay on its stronger earnings outlook (JPM FY26 28E socket EPS CAGR 108% vs 73% for MPI) plus more favorable competition landscape vs probe card (MPI).

• Testing intensity increases the m lti-year trend.We expect chiplet design to lift aggregate CP time by 10-15% per generation and FT/SLT to see a similar trend as chip complexity rises. We estimate HPC probe card TAM at US $1.6/5.9bn (2026/28E) (90%+ CAGR), and HPC socket (FT/SLT) TAM at US$0.9/3.7bn (100%+ CAGR), with SLT a major socket TAM driver.
• Favor socket over probe card - o r non-consens s view. Probe cards carry higher technical barriers/margins, and MPI is well positioned for increasing localization. However, 1) competition remains robust (m/s lacks continuity), 2) PCB is becoming a binding constraint for MPI, especially where competitors have built in house capability. High end sockets have a narrower qualified supplier pool and better m/s visibility. We are on par/-9% vs Street on WinWay/MPI 2028E EPS. Earnings upgrades are the key share price driver (still room for WinWay).
• WinWay: global socket leader; LT beneficiary of rising SLT adoption. WinWay has 70%+ m/s in Nvidia's FT socket (45 50% m/s in HPC FT socket). WinWay entered Nvidia's SLT socket in 2026 (7 8x content vs FT on longer test time). WinWay brings excellent onsite support and strong supply chain relationships, positioning it as a LT SLT beneficiary (Smiths [not listed] is a competitor in SLT). We estimate Nvidia SLT socket rev CAGR of ~200% to 23%/35%/44% of WinWay's 2026/27/28E rev. Our 2028E EPS are on par with the street, assuming 7% higher rev but lower GM on expansion cost (scale benefit to arise in the LT).
• MPI: Taiwan probe card leader entering MEMS. MPI is Taiwan's probe card leader expanding into MEMS technology (>4x capacity in 2027E vs 2025); we expect MEMs to reach 20%/35%/48% of 2026/27/28E total rev. While we are positive on MEMS demand and MPI's positioning, peers such as Technoprobe and FormFactor are also aggressively expanding, lowering m/s visibility vs expectations (sellside all OWs with TP 35 40x 2028E). Our below street EPS growth reflects competition and a modest CPO rev outlook.
• OW WinWay, N MPI. WinWay/MPI shares have fallen 50%/30% from April/July peaks vs TWSE +16% from April on de risking plus company specific factors (GM and m/s concern for WinWay, CPO testing uncertainty for MPI). As growth outlook remains robust and valuation is now more reasonable (30's vs +50x 2027E P/E at peaks), we see better risk/reward in WinWay. Our WinWay Dec 27 PT is based on 26x 2028E socket EPS. Our N for MPI view reflects probe card competition; PT is based on 28x2028E EPS (global peers trading at mid 20's; Taiwan hist. premium vs RoW 15 20%). Key risks are AI capex deceleration, test time cut, and escalating competition.

Technology

erry Tsai AC

(886-2) 2725-9867 jerry.tsai@jpmorgan.com J.P. organ Securities (Taiwan) Limited

osie Yu

(886-2) 2725-9877

josie.yu@jpmorgan.com

J.P. organ Securities (Taiwan) Limited

Gokul Hariharan

(852) 2800-8564

gokul.hariharan@jpmorgan.com

J.P. organ Securities (Asia Pacific) Limited/ J.P. organ Broking (Hong Kong) Limited

Glossary:

HPC: High-Performance Computing

CP: Chip Probing

CPC: Cantilever Probe Card

MEMS: Micro-Electro-Mechanical System

FT: Final Test

S T: System-level Test

CPO: Co-packaged Optics

DUT: Device Under Test

DFT: Design For Test

Figure 1: Key drivers for test interface market

See page 67 for analyst certification and important disclosures, including non-US analyst disclosures

Equity Ratings and Price Targets

Source: Company data, Bloomberg Finance .P., J.P. Morgan estimates. n/c = no change.All prices as of 22 Oct 26.

Investment Thesis

Figure 2: Key drivers for test interface market

Source: J.P. Morgan.

We are constructive on the test interface demand outlook through 2028 and potentially beyond, driven by: 1) rising testing intensity as AI chips require longer test time, higher pin counts and broader system level test (SLT) coverage; and 2) Taiwan suppliers remaining the enablers and key beneficiaries of the increasing number and complexity of projects, which leads to greater localization. These trends support strong growth in both high performance computing (HPC) final test (FT) and SLT sockets (100+% CAGR 2026-28E) and probe cards (90%+ CAGR). Considering the relative clarity of the demand growth outlook given sockets' better competitive dynamics compared with probe cards, we favor WinWay and highlight the key points to watch for MPI. We initiate coverage of WinWay at Overweight with a Dec-27 price target of NT$7,500 (26x 2028E EPS ex-probe card) and MPI at Ne tral with Dec-27 price target of NT $5,350 (28x 2028E EPS), while forecasting FY2026-28E EPS CAGRs of 108% (socket-related) and 73%, respectively.

O r stock preference reflects the better clarity of ind stry demand translating into company earnings. Our non consensus call is to prefer high end sockets over probe cards in the current AI cycle. Probe cards retain higher technical barriers, ASPs and margins, but high end sockets currently offer narrower qualified competition, better allocation visibility after qualification, and a slower qualified capacity response. We also believe the likelihood of new entrants disrupting the current socket dynamics is limited, given the close collaboration required between vendors and customers. In our view, these factors provide a clearer path from AI demand to allocation, utilization and incremental EPS gains for Winway. While we acknowledge that MPI stands to benefit from localization, we note that the dynamic shifts in probe card industry market share could persist as global players continue to expand their presence in Taiwan. Our 2028E EPS forecast for WinWay/MPI is in-line / -12% vs consensus, which reflects our view on the m/s allocation in socket and probe card industry.

WinWay (OW): Unlocking SLT TAM

We expect rising SLT exposure, higher pin content and next generation socket adoption to increase revenue per AI platform. We project WinWay's SLT socket revenue mix to rise from approximately 56% in 2026E to 70% in 2028E. Demand backed capacity expansion and stronger utilization should also support operating leverage. One key concern is whether WinWay can retain allocation across successive Nvidia and other AI platforms - we think this is likely. Platform share appears sustainable so long as the socket vendors like WinWay sustain service levels and product quality. Other concerns for WinWay are more related to probe cards: 1) share competition with MPI over the Nvidia Vera probe card; and 2) margin drag from MEMS probe card (WinWay sources the key component, MEMS pin, from Technoprobe and margin for WinWay is capped at 30 35%. This is 5 15ppt lower vs company average). However, we find these concerns overdone, believing they are largely in the price, and because socket margins exceed probe card margins for WinWay given its higher production internalization in sockets. While our valuation for WinWay excludes the contribution from probe cards, it still offers decent potential upside in support of our Overweight rating.

MPI (N): Entering the competitive MEMS market

Broadcom has been MPI's largest customer and is a key anchor of its TPU (Tensor Processing Unit) exposure, but final allocation remains sensitive to customer sourcing decisions and to the VPC to MEMS transition, where competition could be even more fierce vs the current Cobra probe card technology. MPI is dominant in cobra pin probe card - a more mature technology - whereas the MEMS field is crowded. MPI is expanding MEMS pin capacity by more than 4x from 2025 to 2027E, which could raise utilization and margin risk if production awards lag. In recent quarters, the company's CPO Insertion 2 prober has been a key driver of share price volatility amid talk of reduction or removal of the process. We believe investors remain divided on the outcome, implying potential upside for MPI's revenue if the process survives. This could contribute ~6% of 2028E reven e (assuming meaningful pull in starting in 2027E). We currently apply a 50% discount to the rev contribution to factor in the possibility of insertion 2 to be cancelled and therefore insertion 2 equipment rev contribution is 3% in 2028E in our model.

CHPT (OW): Beneficiary of testing PCB supply bottlenecks

The PCB, which houses the pins and sockets, is also a critical component of the test interface. The lead time for probe card PCB is rising rapidly, driven by: 1) a growing number of chip designs, which translates directly into more customized probe PCB designs; and (2) value add from advanced packaging proliferation. This leads to our positive view on CHPT, which we believe to be the leading testing PCB producer globally and is leveraging this position to capture more total solution probe card opportunities, which offer 3 5x higher content value vs its typical PCB only sales. We assign a 30x 2028E target P/E to CHPT, the highest in our coverage, reflecting our view that CHPT has the best prospects for upward earnings revisions, as complex PCBs are becoming the key binding constraint for probe card supplies.

Valuation gap between socket and probe card could narrow

We assign a higher multiple to probe card vendor MPI than to socket supplier WinWay, reflecting the belief that higher technical requirements warrant a premium. Nevertheless, we expect the valuation gap to narrow over the coming years. The challenging competitive environment should not be overlooked, and we believe incumbent socket vendors such as WinWay can defend their leadership positions well. Our target multiples, based on 2028E EPS, are 28x for MPI vs 26x for WinWay - a narrower gap than the Bloomberg consensus premium of 6 8x between probe card and socket vendor valuation.

Coverage company comparison - in charts

Table 1: Comparing WinWay, MPI and CHPT

Note: Market cap data is as of 22 Oct 2026. Forward financials are all based on J.P. Morgan estimates. Source: Bloomberg Finance .P., J.P. Morgan estimates.

Figure 3: WinWay - revenue and growth

2019

Source: Company data and J.P. Morgan estimates.

Figure 5: MPI - revenue and growth

Source: Company data and J.P. Morgan estimates.

Figure 7: WinWay - revenue mix by client, 2026E

Source: J.P. Morgan estimates.

Figure 4: WinWay - socket-related EPS and growth

Source: Company data and J.P. Morgan estimates.

Figure 6: MPI - EPS and growth

Source: Company data and J.P. Morgan estimates.

Figure 8: MPI - revenue mix by client, 2026E

70%

Source: J.P. Morgan estimates.

80%

Figure 9: WinWay - revenue by segment

Source: Company data and J.P. Morgan estimates.

Figure 11: MPI - revenue by segment

Source: Company data and J.P. Morgan estimates.

Figure 10: WinWay - revenue by segment

Source: Company data and J.P. Morgan estimates.

Figure 12: MPI - revenue mix by segment

Source: Company data and J.P. Morgan estimates.

Sector performance and valuation

Share prices in Taiwan's test interface sector, particularly for WinWay and MPI, have fluctuated in response to changes in AI accelerator demand, platform qualification and expectations around testing intensity. The sector began to re rate in early 2023 as investors shifted from a traditional semiconductor cycle framework toward accelerated earnings growth spurred on by the AI megatrend. WinWay's performance has increasingly reflected expectations for higher FT/SLT socket content, while MPI has traded more closely with probe card allocation, capacity expansion and CPO (Co packaged Optics) expectations.

The sector rally strengthened through 2024 25 as Blackwell related demand improved visibility on AI testing requirements and TPU qualification supported probe card sentiment. A further re rating occurred during 2H25 to 1H26 as record earnings, aggressive capacity plans and CPO expectations reinforced the view that test interface is one of the key beneficiaries of the AI megatrend. The sector corrected sharply from mid 2026 due to concerns about an AI bubble. Meanwhile, investor concern around the Insertion 2 testing outlook also became a negative headwind for MPI.

Figure 13: Taiwan test interface industry - share price performance

Source: Bloomberg Finance .P. Note: Share price relative performance vs 1 January 2023 level of each stock and the index. Prices are as of 22 Oct 2026 close.

Figure 14: WinWay - 1-year forward P/E band

Source: Bloomberg Finance .P., J.P. Morgan estimates.

Figure 15: MPI - 1-year forward P/E band

Source: Bloomberg Finance .P., J.P. Morgan estimates.

We expect the 15-20% local valuation premium to hold ...

We believe local test interface companies' valuations are justified by their increasingly important role in AI chip testing. Taiwan test interface suppliers have generally traded at P/E valuation premiums of 15-20% over global peers given their access to customers that are increasingly critical in AI chip testing, which is growing more strongly than the overall test interface industry. The rising number of projects - driven by chiplet proliferation and an expanding universe of chip designs beyond main accelerators - also favors local suppliers, given the intensifying need for engineering communication between vendor and customer. Taiwanese vendors offer a competitive advantage with stronger after sales support in terms of both timeliness and language - notably sharing the same language with the testing engineers - since most advanced chips are tested in Taiwan. This advantage is even more important in the socket industry due to the larger deployment scale (note that FT/SLT testing time is a lot longer than chip probing). Thus, we apply a premi m (vs global peers) to WinWay and MPI of aro nd 15-20%.

… but also see a narrowing of the valuation gap between probe card and socket players

We believe probe card suppliers should retain a premium due to higher technical barriers and margins, but we expect the historical discount applied to high end socket suppliers to narrow as qualification requirements tighten and earnings visibility improves.

Probe card peers trade at approximately 35x/25x 2027/28E P/E, vs 26x/21x for socket peers and 21x/17x for OSATs on Bloomberg consensus estimates and JPMe (for J.P.Morgan covered names, see notes for table 2 for full list). We believe WinWay deserves a premium to traditional socket peers given its higher AI exposure, stronger earnings growth and clearer allocation visibility, but should remain at a discount to probe card peers. We therefore value WinWay at 26x 2028E EPS, and MPI at 28x.

Re rating opportunities and/or stock trading momentum could arise from: 1) stronger than expected growth in AI test time, SLT mix and pin count; 2) tighter qualified socket supply as demand outgrows capacity; and 3) faster adoption of higher content solutions such as HyperSockets and MEMS probe cards.

Table 2: Valuation comparison - Global socket peers, global probe card peers, OSAT

Source: Bloomberg Finance .P., J.P. Morgan estimates. Consensus estimates used for stocks Not Covered (NC).

Note: For J.P.Morgan covered names - MPI (Jerry Tsai), CHPT (Jerry Tsai), Technoprobe (Craig A McDowell), WinWay Tech (Jerry Tsai), eeno (Sangsik ee), ISC (Sangsik ee), ASE (Gokul Hariharan), and Amkor (Mayur Ramdhani) - forward financials are based on J.P. Morgan estimates. All other data is from Bloomberg, including consensus estimates for Not Covered companies. CHPT, MPI, WinWay, ASE, and King Yuan Elec are priced as of 22 Oct 2026. FormFactor, Technoprobe, Cohu and Amkor are priced as of 23 Oct 2026. Maxone Semicon, Suzhou Uigreen, and Jcet are priced as of Oct 26, 2026.

CPO premium? Likely too early to tell

The potential to participate in CPO testing moves share prices, but we do not apply a CPO premium to our target multiples for WinWay and MPI given still limited visibility on the adoption timeline. For MPI, the risk is that Insertion 2 (MPI makes the wafer level prober) is canceled to contain the total test time. For WinWay, wafer level socket volume remains constrained by the absence of automated equipment on the market - PIC EIC wafer level optical fibre array alignment is still performed manually, limiting throughput - so volume and revenue contribution from CPO testing remain immaterial.

Test interface sector outlook

Introduction to probe cards and sockets

Probe cards are the main test interface for chip probing, which is performed on wafers to ensure no defective chips enter the packaging process. Sockets are used after semiconductor backend testing (after the chips are packaged), and the process consists of multiple steps such as final test (FT) (performed for all ICs), system level test (SLT) (performed selectively) and burn in. While the socket is mounted on PCBs in all cases, the names of the boards differ according to the process; ie, load board for FT, SLT motherboard for SLT, and burn in board.

Figure 16: Semiconductor manufacturing process overview - probe card and socket structure

Source: J.P. Morgan Probe cards and load boards both comprise mechanical components - pins and sockets - together with PCBs and substrates. These components rely on very different manufacturing technologies, so the supply chain can be complex: vendors frequently source components externally and assemble them into finished probe cards or load boards. Sourcing authority is therefore a key determinant of market dynamics, and probe card integrators can be foundries, OSATs or probe card vendors themselves.

Market outlook

We estimate that global HPC probe card TAM will grow from US$1.6bn to US$5.9bn from 2026E to 2028E, exhibiting a ~94% CAGR. The CAGR can be broken down into three key factors: 1) growth of the Device Under Test (DUT; die in this case); 2) per chip probing time increase; 3) per probe card pin count increase; and 4) migration to MEMS probe card.

We estimate that HPC FT/SLT socket TAM will grow from US$0.9bn to US$3.7bn from 2026E to 2028E, exhibiting a ~104% CAGR. The CAGR can be broken down into three key factors: 1) growth of the Device Under Test (DUT; chip in this case); 2) per chip FT/SLT testing time increase; and 3) per socket pin count increase (correlated to package size increase).

Figure 17: HPC probe card TAM and YoY growth

Source: All data is based on J.P. Morgan estimates.

Figure 18: HPC FT/SLT socket TAM and YoY growth

Source: All data is based on J.P. Morgan estimates.

Figure 19: FT vs SLT HPC socket TAM comparison 4,000

Source: All data is based on J.P. Morgan estimates.

Figure 21: Probe card TAM by segment

Source: All data is based on J.P. Morgan estimates.

2027e

Figure 20: FT vs SLT testing time - using Nvidia GPU as illustration

Source: All data is based on J.P. Morgan estimates.

From a testing time perspective, we estimate that burn in socket TAM size is smaller or close to SLT socket TAM in 2025, as suggested by the test time, though the growth could be capped at a similar CAGR going forward, as suggested by the testing time increase.

Test interface TAM growth and sensitivity analysis

Figure 22: Sensitivity of HPC probe card TAM growth

Source: All data is based on J.P. Morgan estimates.

Figure 23: FT socket TAM by segment

Source: All data is based on J.P. Morgan estimates.

Figure 25: SLT socket TAM by segment

Source: All data is based on J.P. Morgan estimates.

Figure 27: AI chip probing time trend

Source: All data is based on J.P. Morgan estimates.

Figure 24: Sensitivity of HPC FT socket TAM growth

Source: All data is based on J.P. Morgan estimates.

Figure 26: Sensitivity of HPC SLT socket TAM growth

Source: All data is based on J.P. Morgan estimates.

Longer testing times

Figure 28: AI chip FT testing time trend

Source: All data is based on J.P. Morgan estimates.

Chip probing (probe cards)

Heterogeneous integration/chiplet enables more functions per package by combining multiple dies. While each die can become simpler, which leads to probing time per die shortening, the aggregate probing time per chip - the sum across all constituent dies - still rises by 10-15% per chip generation. Wafer level test is the only opportunity to cost effectively sort out bad dies prior to backend testing, and it involves physical contact between every probe on the card (ranging from a few to 200k pins) and the DUT. For large AI class devices, aggregate probe loads can reach tens of kilograms and in extreme cases approach 200-300kg of total applied force, which must be applied uniformly to a thin, rarely perfectly flat silicon structure. Advanced packaging introduces significant topography variation through microbumps, TSVs, copper pillars, redistribution layers and chiplet attachment, so small deviations in coplanarity redistribute load unevenly and create localized stress concentrations that are difficult to predict or control.

Chip probing (CP) is also delicate, and the economic context makes the challenge more acute. A bump that loses height or develops microcracks during wafer probing may survive assembly but fail later under thermal cycling or mechanical stress. AI class devices and large chiplet modules represent enormous silicon value, and a single damaged die can force an entire module to be scrapped. Wafer probe is therefore no longer a low risk screening step but a potential yield limiter whose consequences may not surface until much later.

Final test (sockets/load boards)

We expect Final Test (FT) testing time to continue rising modestly, by generation (assume 10 20% per AI chip generation). High performance devices distribute power across thousands of pins, and degradation in a small fraction of the contacts can be masked by the parallel network, allowing devices to pass test even as local hotspots develop. Rising interface speeds compound the problem: test equipment historically carried ample speed margin, but with high speed interconnects moving from 10Gb/s a decade ago to 100Gb/s today - req iring 110Gb/s capability - margin has effectively disappeared. Testing error rates have risen from approximately 0.1% to 2-3%, and the standard remedy is to increase measurement time to suppress Gaussian random error. Longer FT time is therefore a necessary consequence of higher device speed, not a discretionary choice

J PMORGAN

J PMORGAN

Figure 29: Increase testing time (expands the vertical bounds) to reduce testing error (colored area)

Normal speed interconnect High speed interconnect

Source: J.P.Morgan

System-level test (sockets/SLT boards)

Compared to FT, System level Test (SLT) is a relatively new backend testing process that is developed to resolve the potential defects that could emerge from multi chip packaging (rather than monolithic design). SLT time rises significantly by generation, and heterogeneous integration is the principal cause. As chipmakers pack digital logic, analogue front ends, high bandwidth memory interfaces, and specialized accelerators into a single package, the number of potential cross domain failures multiplies well beyond what conventional ATE (Automated Test Equipment) can address. ATE remains highly effective at verifying individual IP blocks against faults, but was not architected to replicate the interplay among heterogeneous components under real life conditions. SLT fills this void by running the fully integrated system with realistic workloads, power management ICs, memory subsystems and high speed serial links, identifying coherency violations and thermally induced timing drift.

We see heterogeneous integration/chiplet as a structural tailwind for SLT testing time for two reasons. 1) Assembled multi chiplet packages are simply too expensive to fail, and extended SLT provides the necessary assurance - scrap costs for 2.5D/3D designs accumulate geometrically from fabrication to assembly, versus broadly linear accumulation for monolithic devices. 2) Multi vendor supply chains introduce an error tracking challenge that only a comprehensive end to end functional test can resolve: when each chiplet supplier delivers its own test program built on a proprietary methodology, the final integrator must still guarantee system level correctness and isolate root causes across the data path. This applies not only to high profile HPC chips but extends into the smartphone AP domain, where chiplets and heterogeneous integration are increasingly prevalent and mixed protocol internal interfaces create interaction level errors that only comprehensive SLT can detect.

Addressing the key debate - test time red ction

Investors frequently argue that AI and machine learning will shorten testing time. We see the impact as limited for HPC chips, particularly AI chips, where chip lifetimes are only one to two years and process maturity never arrives. Adaptive testing relies on applying only the necessary test content based on tester data, on die sensors and upstream inspection data - a technique that works for mat re processes with high, stable yield, where tests can be eliminated, sampling substituted for full testing, or two pass flows adopted. Leading edge AI silicon does not meet these preconditions.

Critically, the impact on test consumables is negligible, even where testing time reduction is achieved, because sockets and probe cards are ordered to fulfill the initial test time. Testing time reduction is therefore more relevant to OSAT throughput economics and chip launch timing than to interface consumable demand.

We expect chip probing time across major HPC chips (GPU, ASICs) to grow at a CAGR of 10-15% from 2025 to 2028e, while we expect FT/SLT testing time to grow at 15-20% CAGR.

Longer dwell time reduces throughput per socket position and increases the number of sockets required for each production ramp, while also raising contact wear and replacement demand, providing a recurring revenue stream beyond initial socket deployment.

Table 3: Key chip heterogeneous integration trend

Source: All data is based on J.P.Morgan estimates.

More chip and die designs to offload AI workload, plus localization

Advanced packaging reshapes probing. Reticle limits constrain monolithic die size, pushing designers toward chiplets, interposers and large chip on wafer structures. A chiplet is a small, unpackaged circuit optimized for a single function at its most suitable process node; the concept emerged as integrating too many components onto a single SoC compressed yield rates. By enabling modularization and design flexibility, chiplets can be integrated across different chip types on a substrate through advanced packaging.

J PMORGAN

Chiplet architecture materially expands testing demand, as each package contains multiple dies that must be screened as known good dies prior to assembly. The heterogeneous nature of these designs, spanning compute, I/O and auxiliary dies, further necessitates separate probe card designs and qualification cycles per die type. More dies and chip designs mean more probe card and socket designs are required, each needing to be customized.

Localization benefit: indeed, b t thesis even more valid in socket

Meanwhile, we believe localization could also be a driving force for both WinWay and MPI. The rising project count demands intensive, iterative communication between vendor and customer, structurally favoring Taiwan suppliers co located with the foundry and OSAT base. However, we note that there are different industry dynamics when it comes to localization for probe cards and sockets. For sockets, the global industry consists of multiple suppliers with similar production scale. Over the years, each vendor was able to build 'territories' in a given market. Hence, the competition is less fierce. In the socket space, WinWay is benefitting from localization in some areas such as SLT, which was previously mostly taken by its US/UK peer (Smiths Interconnect, now part of Molex; not listed), as it is starting to gain share in this fast growing market.

For probe cards, while the localization needs are rising to meet the increasing project numbers and rapid product cycles, the international players are still very much forces that need to be reckoned with. The industry is currently led by Technoprobe (TPRO IM, covered by Craig A McDowell) and Formfactor (FORM US, Not Covered), and these leading players have been expanding their supply chain collaborations and local support in Taiwan.

Increasing technical barriers from higher pin count and larger package size

The ASP/content per probe card and socket are both direct functions of pin count. Driven by more complex I/O layout and larger package sizes, the pin count per probe card and FT/SLT socket is expected to increase structurally, driving content growth. We estimate the major AI chips (GPU, ASICs, etc.) probe card/socket pin count to grow at a ~10-20% CAGR from 2026E to 2028E. Larger packages require more complex contact architecture, signal integrity control, thermal management, and mechanical support. We therefore expect revenue per test position to rise even under our conservative ASP assumptions (assume flat to 0 5% increase YoY), supporting a richer product mix and a more durable growth profile.

Entry barriers rise for both probe cards and sockets under higher pin counts. Chiplet adoption drives I/O count, and more I/O means higher pin count. On the probe side, probe area size has physical limits, though vendors are developing solutions to manage aggregate force and coplanarity at scale.

Figure 30: Nvidia GPU probe card pin count growth

Source: All data is based on J.P.Morgan estimates.

Figure 31: Nvidia GPU probe card ASP

Source: All data is based on J.P.Morgan estimates.

Figure 32: MEMS pin ASP trend

Source: All data is based on J.P.Morgan estimates.

Addressing the parallelism co nter-arg ment

Meanwhile, we believe some investors are concerned that parallel testing - which refers to testing multiple numbers of dies or IC packages simultaneously on the same test interface - could diminish the value add of testing. In our view, while higher chip probing (CP) parallelism can reduce total test time per chip generation, it does not reduce overall pin consumption, which is the main driver for pin producers such as MPI. Parallel testing also introduces noise, and capability depends on die size and the number of test instruments required. Test engineering teams must balance DUT power draw, pin count, and circuitry performance against ATE instrumentation; reconcile DUT properties with thermal control, probe/test interface boards, probe tips or sockets, and handler capabilities; manage thermal, mechanical, and electrical characteristics across multiple sites; and absorb increased PCB routing complexity from higher die per unit counts and board multiplexers.

Industry risks

Testing time red ction or slower-than-expected increase

The sector's growth outlook depends on longer testing times, higher pin count, and rising SLT requirements. If tester throughput improves faster than expected, test time growth can be compressed, reducing the number of socket positions required per AI platform. We believe the rising SLT mix and higher pin count provide structural offsets, but faster test time reduction would still limit FT/SLT socket TAM growth and weaken the sector's earnings visibility.

Key project (AI chip) delays

Interface demand is concentrated in a small number of large AI platforms. Delays to major GPU, ASIC or CPU roadmaps would push out qualification and volume ramps, deferring revenue recognition for suppliers that have already added capacity and incurred depreciation and staffing costs.

AI capex concerns

The sector's growth is closely tied to robust demand for AI chips and the continued expansion of AI accelerator platforms. If global AI demand weakens, CSP (Cloud Service Providers) capex converts to revenue more slowly, or major platform roadmaps slip, customers may slow capacity reservations and reduce test interface orders. This could result in excess socket or probe card capacity, longer qualification cycles, weaker utilization and downward pressure on revenue growth.

Figure 33: Top 4 US CSPs - annual datacenter capex US$bn ( HS); % (RHS)

Source: 650 Group and J.P. Morgan estimates.

Increasing competition - probe cards

Probe card competition is broader and more technology segmented, and we view it as the more acute risk. Multiple vendors participate in parallel during design in and qualification, but volume production typically narrows to a single or dual source structure. This winner takes most dynamic means that relatively small differences in technical performance, qualification timing or production readiness can drive materially different allocation outcomes. Simultaneous capacity additions across several well capitalized incumbents could reduce lead time scarcity, moderate pricing power and make supplier specific share gains more dependent on actual qualification outcomes. High technical entry barriers therefore do not necessarily imply low competitive intensity once vendors enter the qualified supplier pool.

Increasing competition - sockets

High end socket competition tends to be account and platform specific. Smiths, Leeno and ISC may possess comparable technical capability and can also add capacity. However, replicating qualification history and production learning on an active customer platform typically takes longer than adding generic equipment or outsourced pin supply. We therefore view the near term competitive risk as moderate, with the principal risk being share loss on a specific platform transition rather than broad based erosion.

Figure 34: Probe card vs socket margin

Note: Use Technoprobe and ISC as proxy for probe card and socket sectors, respectively. Source: Company data.

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Competitive landscape

Sockets - concentrated and stable market share on delivery and local support

For high-end test sockets, we view WinWay and Smiths Interconnect as the most direct competitors in AI/HPC applications. ISC is emerging for chips tested in Korea and favors local supply chain (ISC has the strong local support as competitive advantage). Leeno is strong in pogo pin sockets and rapid customization, while Yokowo, Enplas and Yamaichi are more exposed to memory, automotive and rubber socket applications. The effective qualified supplier pool for leading AI platforms therefore remains concentrated on a few qualified players instead of the overall socket peer set. Entry requires not only product capability, but also on time delivery and local debugging support.

High end socket competition tends to be account and platform specific. Early co development, local engineering support, customer specific qualification and production history can establish relatively defined supplier territories and make allocation more persistent across product generations. While the absolute technical entry barrier remains below that of advanced probe cards, the effective competitive set within an individual high volume AI program may still be limited, supporting a comparatively greater share predictability.

Table 4: Socket competitive landscape overview

Note: WinWay's market cap data is as of 22 Oct 2026 ; Cohu is priced as of 23 Oct 2026; eeno, Yokowo, ISC, enplas, and Yamaichi are priced as of 26 Oct 2026.For J.P. Morgan covered names - WinWay Tech (Jerry Tsai), eeno (Sangsik ee), and ISC (Sangsik ee) - forward financials are based on J.P. Morgan estimates. All other data is from Bloomberg. Source: Bloomberg Finance .P., J.P. Morgan estimates.

Probe cards - technology-oriented; winner-takes-most

For probe cards, competition is broader and more technology-segmented. FormFactor and Technoprobe are the global leaders in advanced MEMS probe cards, while Micronics Japan and JEM have established positions in memory and vertical probe cards. MPI is a leading Taiwanese supplier expanding from VPC into MEMS, while Suzhou UIGreen benefits from semiconductor localization in China. The transition from cobra pin to MEMS pin raises technical barriers, but may also reopen qualification and reset supplier allocation, making market share outcomes more program dependent.

J PMORGAN

Advanced probe card competition is highly technology driven. Multiple vendors may participate in parallel during the design in and qualification stage, but the supplier pool typically narrows to a single or dual source structure for volume production. This creates a winner takes most outcome, where relatively small differences in technical performance, qualification timing or production readiness can result in materially different allocation and revenue outcomes. As a result, despite higher technical barriers and stronger margin characteristics, supplier specific earnings visibility can remain limited until the final qualification and share split are confirmed.

Table 5: Probe card pin competitive landscape overview

Note: MPI's market cap data is as of 22 Oct 2026; FormFactor and Technoprobe are priced as of 23 Oct 2026; Micronics Japan, JEM, Suzhou Uigreen, and Maxone Semiconductor are priced as of 26 Oct 2026. For J.P. Morgan covered names - MPI (Jerry Tsai), Technoprobe (Craig A McDowell) - forward financials are based on J.P. Morgan estimates. All other data is from Bloomberg. Source: Bloomberg Finance .P., J.P. Morgan estimates.

Initiation

Overweight

6515.TW, 6515 TT Price (22 Oct 26):NT$4,795.00 Price Target (Dec-27):NT$7,500.00

Technology

erry Tsai AC (886-2) 2725-9867 jerry.tsai@jpmorgan.com J.P. organ Securities (Taiwan) Limited

Style Exposure

WinWay Technology

Unlocking SLT socket TAM, initiate at OW

We initiate coverage of WinWay Technology at OW, with a Dec 27 PT of NT$7,500 (26x 2028E EPS excl probe card). WinWay's test sockets, contact elements and probe card busi nesses all benefit from rising AI test intensity and supply chain localization, and we expect socket demand to outgrow visible qualified capacity through 2028E. Notably, we hold a differentiated view that the high end socket franchise - not the probe card business the market has fixated on - is where WinWay's value add is most defensible, and we therefore anchor our PT on socket related earnings.

• Expanding dominance in FT socket into SLT socket. WinWay is the global leading supplier of high end Final Test (FT) sockets, while its main competitor Smiths (not list ed) currently has the leading market share in System level Test (SLT) socket space according to our estimate. (WinWay's shares were modest before 2025). We project the FT/SLT socket market for AI/HPC will expand from US$0.9bn in 2026E to US$3.7bn in 2028E, with SLT socket the bigger incremental driver from US$0.7bn (72% of total AI/HPC) in 2026E to US$3.1bn (84%) in 2028E. WinWay is starting to expand into the SLT socket segment with Nvidia (we estimate 20%/25%/30% m/s in 2026/27/28E). We estimate that Nvidia SLT socket revenue will account for 23%/35%/44% of Win Way's total rev in 2026/27/28E, while WinWay's SLT mix will rise from 56% in 2026E to 70% of socket revenue by 2028E. Our 2028E EPS for WinWay is on par with consen sus.
• Capacity a binding constraint ind stry-wide; WinWay adding the most. We esti mate identifiable HPC socket pin capacity across players such as WinWay, Leeno (058470 KS, covered by Sangsik Lee), ISC (095340 KS, covered by Sangsik Lee), Yokowo (6800 JP, NC), and Smiths (not listed) will rise from ~950mn pins in 2026E to 2.1bn pins in 2028E, vs modeled demand rising from ~650mn to 2bn pins. Win Way's own HPC socket pin capacity grows 4x to 200-250mn pins by 2028E on our estimates - the largest absolute addition in our framework. We forecast its HPC FT/ SLT m/s rising from 28% in 2026E to 30%+ in 2028E. We see earnings upside from potential share gains in multiple major US chip makers (including networking and CPU customers) and ASIC opportunities.
• Differentiated view on what drives allocation. Contrary to the perception that socket share turns on product specifications, we think early design for test engagement, local engineering support and qualification history are the durable moats which are some times overlooked by investors. WinWay is Taiwan's biggest socket player and has mean ingfully higher client service resources locally vs any of its international peers. We do not assume any player (including WinWay) possesses irreplaceable technology; we assume product readiness and earlier qualification increases its probability of receiving and retaining allocation. The critical evidence will be repeat production orders and cross generation adoption.
• Initiate at OW. Our Dec 27 PT of NT$7,500 is based on 26x 2028E socket-related EPS, a premium to socket peers at a blended ~21x and a discount to probe card peers. In the case of WinWay, we believe such a premium is well deserved on company's strong ties to major key customers plus a decent track record for quality and delivery. We project FY26-28E EPS (socket) CAGR of 108% vs 40-50% for socket peers. Downside risks include faster than expected test time reduction, Final Test (FT) test intensity shifting left to chip probing (CP), and AI capex deceleration.

Price Performance

— 6515.TW Price (NT$)

— TSE (rebased)

Company Data

Key Metrics (FYE Dec)

Summary Investment Thesis and Valuation

Investment Thesis

We are OW on WinWay, as we believe it is the main beneficiary of the rising SLT socket TAM. While testing socket emphasizes early co development, on time local support, and delivery, we expect WinWay's strong capacity expansion and superior local support in the testing space will continue to help WinWay capture more market share on top of the TAM growth.

Val ation

Our Dec 27 TP is based on 26x 2028E socket related EPS. 26x is on par with Winway's average P/E since 2023 and is at a 15 20% premium to industry peers. We believe the multiple is justified given WinWay's accelerated revenue growth from entering the SLT socket market and further share gains in 2027/28E.

WinWay Earnings Estimates

Table 6: Income statement highlights: Annually JPMe vs Consensus

NT$ mn except for EPS

Consensus data is as of 22 Oct 2026.

Source: J.P. Morgan estimates, Bloomberg Finance .P.

Figure 35: WinWay rev & YoY growth

Source: J.P. Morgan estimates, Company data.

Figure 37: WinWay rev by segment

Source: J.P. Morgan estimates, Company data.

Figure 36: WinWay socket-related EPS & YoY growth

Source: J.P. Morgan estimates, Company data.

Figure 38: WinWay rev mix by segment

Source: J.P. Morgan estimates, Company data.

WinWay Investment Thesis

We are constructive on WinWay over the next three years. AI and HPC are the key growth areas, supported by Nvidia and AMD exposure, dominant local OSAT support, customer design in stickiness and specification design know how. Our core forecast is that AI related socket demand will grow materially faster than qualified capacity growth through 2028E.

Our stock preference within the test interface space reflects this. Probe cards retain higher technical barriers, ASPs and margins, but high end sockets currently offer fewer qualified competition, better allocation visibility after qualification and a slower qualified capacity response. We believe these factors provide a clearer path from AI demand to allocation, utilization and EPS for WinWay than for probe card suppliers, where volume production typically narrows to a single or dual source.

Unlocking SLT socket TAM

HPC SLT socket TAM expands sharply with 110% CAGR

We estimate the HPC System level Test (SLT) socket TAM will rise from US$0.7bn in 2026E to US$3.1bn in 2028E (~110% CAGR), with HPC applications - AI chips (incl. AI CPUs), regular server CPUs, and gaming chips - accounting for ~95% of demand by 2028E. SLT is increasingly important for AI chips because it tests packaged devices under system level operating conditions closer to real world workloads than conventional final test (FT). As AI accelerators become larger, more power dense and more complex, SLT surfaces thermal, power delivery, high speed interface and intermittent reliability issues that shorter electrical tests do not.

The mechanics of why this matters for a socket supplier are straightforward. Longer dwell times and sustained high power workloads make SLT more socket intensive than conventional FT on two counts: 1) longer test duration reduces throughput per socket position, requiring customers to add parallel positions to sustain production output, while 2) higher pin count raises socket content and ASP per position. Longer testing also increases contact wear and replacement frequency, providing recurring revenue beyond initial deployment. We project WinWay's SLT mix rises from ~56% in 2026E to 70% of socket reven e by 2028E.

Heterogeneo s integration is the str ct ral SLT driver

We see heterogeneous integration as a structural tailwind rather than a cyclical one. When multiple ICs and passive elements are packaged together, design for test capability at the assembly level becomes critical, and the challenge resembles a printed circuit board more than a piece of silicon: the objective shifts toward finding assembly errors, which become more prevalent than silicon problems. Conventional ATE isn't effective in replicating the interplay among heterogeneous components under real life conditions. SLT fills that gap by running the fully integrated system with realistic workloads, power management, memory sub systems and high speed serial links, identifying coherency violations and thermally induced timing drift. Multi vendor chiplet supply chains compound the requirements: when each supplier delivers its own test program using a proprietary methodology, the final integrator must still guarantee system level correctness and isolate root causes across the data path.

J PMORGAN

Figure 39: SLT testing time increase - Nvidia GPU

Source: All data is based on J.P.Morgan estimates.

Figure 41: FT/SLT mix of WinWay socket revenue

Leeno Yokowo Others

Source: All data is based on J.P.Morgan estimates.

Figure 40: HPC SLT socket TAM & YoY growth

Source: All data is based on J.P.Morgan estimates.

Figure 42: WinWay socket revenue & growth

Source: All data is based on J.P.Morgan estimates.

5x pin co nt per socket, 5x ASP plift

Socket content per test position should rise materially as AI packages become larger and more pin intensive. We estimate Nvidia GPU pin count will increase from approximately 0.8k in 2026E to 13.5k in 2028E, while AWS accelerator pin count will rise from ~5.8k to 9.9k and Google TPU from ~4.4k to 8.9k over the same period. Larger packages require more complex contact architecture, signal integrity control, thermal management, and mechanical support, and we therefore expect revenue per test position to rise even under conservative ASP assumptions - supporting a richer product mix and a more durable growth profile than unit driven models would imply.

Figure 43: Nvidia GPU test socket pin count

Source: All data is based on J.P. Morgan estimates.

Figure 44: Nvidia GPU test socket ASP

Source: All data is based on J.P. Morgan estimates.

Figure 45: Socket pin ASP assumption

Source: All data is based on J.P. Morgan estimates.

Market share gains from capacity expansion & strong execution

Figure 46: FT/SLT test socket m/s overview

Source: All data is based on J.P. Morgan estimates.

Figure 48: FT/SLT socket pin global supply and demand

Source: All data is based on J.P. Morgan estimates

Figure 47: Capacity expansion for WinWay and peer average

Source: All data is based on J.P. Morgan estimates.

Figure 49: FT/SLT socket pin global supply breakdown

Source: All data is based on J.P. Morgan estimates

We forecast WinWay's FT/SLT socket market share to increase from 20-25% in 2026E to ~30% in 2028E. The principal drivers are greater access to high end AI programs, new SLT exposure - mainly from Nvidia - and sufficient capacity to support customer volume ramps. Historically, high end SLT sockets were dominated by Smiths (not listed), which combined strong socket capability with Nvidia's preference for balancing supply chain orders. We expect the situation to start to change in 2026, as Nvidia chip shipments continue to grow, and our checks suggest one of WinWay's main competitors could be facing under staffing issues locally in Taiwan, while not ramping capacity as quickly as WinWay. We assume WinWay enters Nvidia's SLT market and captures ~20% share in 2026e, reaching 25%/30% in 2027/28E as our base case. Meanwhile, we see no meaningful new socket vendors emerging.

Figure 50: WinWay m/s forecast for FT/SLT sockets

Source: All data is based on J.P. Morgan estimates.

Early co-development and superior local support

The test socket industry is characterized by rapid customer ramps, frequent engineering changes and tight delivery schedules. In this environment, we believe the more durable source of differentiation is not new technologies (say HyperSocket..etc), but WinWay's ability to engage customers and handler partners early in the design for test process.

S pplier selection: on-time delivery and after-sales s pport

Advanced AI sockets are customized around package dimensions, contact mechanics, thermal requirements, system integration and customer specific reliability criteria. Supplier selection therefore depends on engineering responsiveness and qualification execution. Early participation can generate a flywheel: customer co development, faster design iteration, successful qualification, volume production data, and potential carryover into the next product generation. Competitors such as Smiths, Leeno and ISC may possess comparable technical capabilities and can also add capacity, but replicating qualification history and production learning on an active customer platform may require more time than adding generic equipment or outsourced pin supply.

Our share gain thesis does not assume WinWay is technologically irreplaceable - it assumes earlier qualification raises the probability of receiving and retaining allocation. The critical evidence will be repeat production orders and cross generation adoption. On the key debate of whether WinWay can retain allocation across successive Nvidia and other AI platforms, we think it is likely: market shares appear sustainable as long as socket vendors sustain service level and product quality.

Design For Test (DFT) emphasizes early co-development

Design For Test (DFT) methodologies must be adapted to accommodate the specific requirements of 3D package testing, ensuring thorough fault coverage and minimizing test escapes. As DFT moves earlier and becomes more package specific, the supplier involved at the DFT stage gains an information advantage that is difficult for a later entrant to replicate - which is precisely why we weight early engagement more heavily than specification parity in assessing competitive risk.

The market debates whether next generation AI workloads genuinely require a purpose built socket; our view is that HyperSockets will gain share within high end AI programs without displacing coaxial.

HyperSocket: designed for next-gen extra-large package size

Existing coaxial sockets remain viable for most AI chips through 2028E, while HyperSockets address the high end tier where elevated power, pin count and signal speed demand superior durability and signal integrity. Some adoption, which likely started from 2025, will remain selective, as higher unit cost confines deployment to the most demanding applications. Critically, total cost of ownership favors HyperSockets at scale, since extended socket life and reduced replacement frequency offset the higher upfront price.

In our view, the structural FT/SLT demand drivers do not benefit all socket suppliers equally - as packages move beyond the 100mm class, qualification depends on managing warpage, contact force, current delivery, signal integrity and thermal stability simultaneously. This is the point at which conventional architectures begin to face physical trade offs, and where we think content and share opportunity concentrate.

This is where HyperSocket comes in. The proprietary technology is positioned as a hybrid architecture for these applications, with ~30% better contact resistance, current capability and Joule heat performance, at ~30% ASP premium and lower total cost of ownership. Importantly, the higher ASP coexists with a lower total cost of ownership for the customer: longer socket life, supported by the company's elastomer patent position, reduces replacement frequency, while higher test quality and shorter replacement time improve effective throughput.

We do not assume that HyperSockets will become the only viable solution or broadly replace coaxial sockets - conventional architectures remain suitable for a meaningful portion of the market. Rather, we view HyperSockets as expanding WinWay's addressable opportunity in ultra large, high pin count and high power FT/SLT applications where traditional architectures become less optimal.

Table 7: HyperSocket vs other socket types

Source: J.P. Morgan estimates, Company data.

Investment Risks

Downside risk: FT & SLT test time red ction across chip generations

Our socket TAM and share forecasts rest on test time extending across chip generations; faster than expected test time reduction is the single most consequential downside variable.

The sector's growth outlook depends on longer test time, higher pin count and rising SLT mix. If tester throughput improves faster than we expect, test time growth could compress, reducing the number of socket positions required per AI platform. We analyze the sensitivity of WinWay's earnings to FT test time and market share jointly, since the two variables interact: a shorter test time requires a higher share to sustain the same revenue. We believe the rising SLT mix and higher pin content provide structural offsets, but faster test time reduction would still limit FT/SLT socket TAM growth and weaken earnings visibility across the space.

Downside risk: FT test intensity shifts to chip probing

If test coverage migrates left into chip probing, FT and SLT socket intensity could grow more slowly than we model - a risk that is partly naturally hedged by WinWay's own probe card exposure. A structural risk to our socket led thesis is that test coverage migrates left into wafer level probing rather than right into SLT. The industry rationale for shifting left is real: packaging bad silicon alongside good silicon in advanced 2.5D/3D architectures is financially punitive, and known good die screening at chip probing (CP) is the only cost effective opportunity to sort out bad die before assembly. If customers conclude that incremental coverage is cheaper at CP than at FT or SLT, socket position requirements per platform could grow more slowly than we forecast.

Downside risk: Chip probing shares co ld be volatile

We assume WinWay captures 30% of the addressable Vera/Rosa chip probing opportunity, and estimate related probe card revenue accounts for ~15%/14%/13% of gro p reven e across o r 2026/27/28E forecasts. This is a meaningful share of the group and a meaningful share of the risk: probe card allocation is decided program by program, competition is broader than in sockets, and vendor choice across successive project generations often lacks continuity. Our deliberate decision to anchor the valuation on socket related earnings reflects this - we would rather underwrite the franchise we believe is defensible than capitalize an allocation outcome we cannot yet verify.

Table 8: Nvidia Vera/Rosa CPU probe card rev contribution to WinWay

Source: All data is based on J.P. Morgan estimates.

Unable to sec re s fficient MEMS pins from Technoprobe: WinWay accesses MEMS probe card technology through a partnership and licensing arrangement with Technoprobe (TPRO IM, covered by Craig A McDowell), under which WinWay performs probe card assembly and design in work with customers while sourcing MEMS pins - the critical, highest value component - from its partner. The arrangement gives WinWay credible MEMS capabilities without the capital intensity and development timeline of building an MEMS pin franchise from scratch, but it also means the company's MEMS volume is bounded by its pin allocation. If Technoprobe prioritizes its own direct business or other partners during a period of tight MEMS supply, WinWay could lose share on programs it has already won. This dependency is, in our view, a further argument for valuing WinWay on its socket franchise, where production internalization is higher and the value chain is more fully controlled.

Margin - probe card is the swing factor: Probe card, not socket, is the swing factor for WinWay's consolidated margin. Socket gross margin was comparatively stable and structurally higher, reflecting greater production internalization; probe card margin has been the drag and is now the swing factor. The Technoprobe phase 2 agreement, effective from 1Q26, materially improves the gross profit of WinWay's MEMS probe card business. Under the earlier arrangement, MEMS probe card profitability was reportedly close to breakeven, limiting earnings contribution despite revenue growth. We now model a margin range at 30-35%, vs the 40%+ for sockets and contact elements.

Table 9: WinWay/Technoprobe MEMS probe card agreement

Source: WinWay, J.P. Morgan estimates..

Downside risk: elastomer patent and later entry vs ISC

HyperSocket's total cost of ownership advantage depends materially on socket life, which in turn rests on WinWay's elastomer patent position. Two risks follow. 1) The patent scope and durability are not settled, and an adverse outcome or successful design around would erode the replacement frequency advantage that justifies the ASP premium. 2) ISC entered the elastomer based solutions market earlier, and in a market where qualification history matters more than specifications - the argument we make in WinWay's favor on sockets generally - incumbency can cut against WinWay in this specific sub segment. We do not treat this as thesis breaking, since HyperSockets is incremental to rather than the basis of our base case, but it is the clearest instance where our own framework works against the company.

Upside risk: CPO extending testing time f rther

In our view, CPO is a longer term optionality rather than a core earnings driver, and we exclude the full opportunity from the base case. CPO represents a longer dated test interface opportunity rather than a core earnings driver. WinWay can supply sockets and related interfaces for later optical engine test insertions, where long test times, precise alignment and higher pin count increase the value of reliable contact solutions. Under an upside scenario, we estimate CPO could add roughly high single digit percent to 2028E revenue. We have not incorporated the content increase in our base case given the uncertainty around architecture, supplier selection and commercialization timing.

J PMORGAN

WinWay began its CPO efforts as early as 2019, when market discussion of related applications was limited and much of the technology and supply chain had yet to mature. Management has indicated that the company's strategy remains focused on its core testing business and does not span all CPO segments, concentrating primarily on electrical testing. We note that the industry level constraint on CPO: Insertion 2 volumes at wafer level remains limited by the absence of automated equipment for PIC EIC optical side fiber array alignment, which is still largely performed manually. Until that bottleneck clears, volume and revenue contribution will stay small regardless of supplier positioning.

Figure 51: WinWay CPO insertion-2 socket offering

Source: WinWay

Valuation: 26x on 2028E socket-related EPS

We value WinWay at 26x 2028E socket related EPS - a premium to socket peers, and a discount to probe card peers, assuming the valuation gap narrows but does not disappear. WinWay currently trades at a ~27x/14x 2027/28E P/E, vers s 35x/25x for probe card peers and 26x/21x for socket peers excl ding Smiths (not listed). We believe WinWay deserves a premium to traditional socket suppliers because high end AI sockets are increasingly technology , qualification and platform driven rather than commoditized mechanical components. However, we retain a discount to probe card peers given their higher technical barriers and margin profile.

Our target P/E for WinWay is 15-20% above industry peers. We note that WinWay's FY26-28E socket EPS CAGR of 108% - vers s 30-35% for peers - supports the premium. Our 26x therefore assumes the historical socket to probe card valuation gap narrows, but does not close: we assign 28x to MPI on the same 2028E basis, a 2x spread that is considerably narrower than the typical street premium of 6 8x. We think this narrowing is the correct direction of travel. The probe card technical barrier argument is sound, but the competitive environment for probe cards should not be overlooked, while we expect incumbent socket vendors to hold their leadership positions comparatively well.

We do not view probe card as the main value proposition as WinWay has has relatively lower value add in this business (recall that WinWay sources probe card pins from Technoprobe) (Technoprobe: TPRO IM, covered by Craig A McDowell). We therefore exclude probe card EPS contribution and use only socket related EPS in our valuation model.

Figure 52: WinWay socket EPS & growth

Source: J.P. Morgan estimates, Company data.

Figure 53: WinWay 1-year forward P/E band

Source: J.P. Morgan estimates, Bloomberg Finance .P.

Figure 54: WinWay rev mix by product

Source: J.P. Morgan estimates, Company data.

Company Background

Leading socket suppliers in Taiwan; strong footprint in AI/HPC

WinWay Technology is a Taiwan based semiconductor test interface solutions provider, with core manufacturing in Taiwan - Kaohsiung for sockets and in house pins, and Hsinchu for probe cards - alongside capacity in Suzhou, China, and regional offices supporting customers across geographies. The company positions itself as a provider of end to end semiconductor test interface solutions spanning front end chip probing (CP) probe cards through to back end FT/SLT sockets, and has described its market position as test socket global No.1 and No.5 in probe cards.

WinWay focuses on high end test interface hardware and related thermal and mechanical solutions. Demand is driven by a consistent set of structural trends: higher pin count, higher speed and frequency, larger package sizes, higher power and longer test times. Each of these raises the engineering content of a socket and, critically, raises the cost of getting it wrong - a dynamic that we think favors incumbent suppliers with qualification history on active platforms.

Three major lines of products; socket the most important by far

WinWay's revenue is split across three lines: test sockets (FT/SLT/burn in), including coaxial sockets and the next generation HyperSocket architecture designed for high speed, high power and large packages; probe card and probe head solutions for chip probing, where the company is expanding into MEMS via partnership and licensing arrangements; and lastly contact elements and pins, which are the replacement parts, are produced through a mix of in house and outsourced manufacturing with ongoing capacity expansion. Sockets and contact elements together account for ~70% of reven e and probe cards ~25%.

Figure 55: WinWay 2026E rev mix by client

Source: J.P.Morgan estimates.

Table 10: WinWay income statement

Source: J.P. Morgan estimates, Company data.

WinWay income statement

Investment Thesis, Valuation and Risks

WinWay Technology(Overweight; Price Target: NT$7,500.00)

Investment Thesis

We are OW on WinWay, as we believe it is the main beneficiary of the rising SLT socket TAM. While testing socket emphasizes early co development, on time local support, and delivery, we expect WinWay's strong capacity expansion and superior local support in the testing space will continue to help WinWay capture more market share on top od the TAM growth.

Val ation

Our Dec 27 TP is based on 26x 2028E socket related EPS. 26x is on par with Winway's average P/E since 2023 and is at a 15 20% premium to industry peers. We believe the multiple is justified given WinWay's accelerated revenue growth from entering the SLT socket market and further share gains in 2027/28E.

Risks to Rating and Price Target

1) FT/SLT testing time reduction, 2) slower than expected socket pin count growth, 3) market share loss in key AI chip projects, and 4) deceleration of CSP's AI capex

WinWay Technology: Summary of Financials

Cash Flow Statement FY24A FY25A FY26E FY27E FY28E

Cash flow from operating activities

193 3,312 2,618 8,486 17,366

o/w Depreciation & amortization

237

258

314

480

660

o/w Changes in working capital

(1,853)

426 (2,199) (3,449) (4,472)

Cash flow from investing activities

(187)

(409) (1,644) (2,500) (2,600)

o/w Capital expenditure

(299)

(280) (1,352) (2,500) (2,600)

as % of sales

5.2% 3.6% 9.5% 9.5% 5.6%

Cash flow from financing activities

1,118 (310) 2,978 1,742

808

o/w Dividends paid

(378)

(890) (1,787)

(395) (1,713)

o/w Shares issued/(repurchased)

1,173

359 1,719

0

0

o/w Net debt issued/(repaid)

311

228 3,029 2,117 2,496

Net change in cash

1,120 2,591 3,938 7,728 15,574

Adj Free cash flow to firm

(106) 3,032 1,266 5,986 14,766

y/y Growth

(109.4%)(2961.8%) (58.2%) 372.8% 146.7%

Ratio Analysis FY24A FY25A FY26E FY27E FY28E

Gross margin

-

-

-

-

-

EBITDA margin

27.7% 29.6% 27.7% 32.4% 34.9%

EBIT margin

23.6% 26.3% 25.4% 30.6% 33.5%

Net profit margin

20.5% 21.3% 21.2% 24.7% 27.0%

ROE

26.3% 27.9% 41.0% 58.0% 64.2%

ROA

19.0% 20.1% 25.9% 35.1% 41.7%

ROCE

23.6% 27.6% 35.3% 49.7% 58.2%

SG&A/Sales

14.1% 13.6% 10.7% 7.2% 6.1%

Net debt/Equity NM NM NM NM NM

Net debt/EBITDA

NM NM NM NM NM

Sales/Assets (x)

0.9

0.9

1.2

1.4

1.5

Assets/Equity (x)

1.4

1.4

1.6

1.7

1.5

Interest cover (x)

NM NM NM NM NM

Operating leverage

253.6% 144.4% 92.4% 144.0% 121.6%

Tax rate

17.3% 18.8% 20.2% 20.0% 20.0%

Revenue y/y Growth

57.5% 35.5% 80.8% 85.4% 76.1%

EBITDA y/y Growth

134.6% 45.0% 68.8% 117.4% 89.5%

EPS y/y Growth

152.4% 37.7% 77.8% 115.9% 92.1%

Valuation FY24A FY25A FY26E FY27E FY28E

P/E (x)

141.9 103.0

57.9

26.8

14.0

P/BV (x)

30.4

26.7

21.2

12.3

7.1

EV/EBITDA (x)

108.3

74.0

43.9

19.8

9.9

Dividend Yield

0.2% 0.5% 1.0% 0.2% 1.0%

Source: Company reports and J.P. Morgan estimates.

Note: NT$ in millions (except per-share data).Fiscal year ends Dec. o/w - out of which

Initiation

Neutral

6223.TW, 6223 TT Price (22 Oct 26):NT$4,890.00

Price Target (Dec-27):NT$5,350.00

Technology

erry Tsai AC (886-2) 2725-9867 jerry.tsai@jpmorgan.com J.P. organ Securities (Taiwan) Limited

Style Exposure

PI

Competition Risk Looms, initiate at Neutral

We initiate coverage of MPI at Neutral, with a Dec 27 PT of NT$5,350 (28x 2028E P/E), given the balanced risk reward. Our N rating is non consensus: all other brokers covering the stock rate the company as OW. We are genuinely positive on the structural growth of advanced probe card demand and we forecast an FY2026-28E EPS CAGR of 73%. Our caution is about price and and the competitive landscape, not about the momentum of growth of the probe card industry.

• Probe card ind stry: aggressive capacity expansion across vendors leads to competition risk. We project the HPC probe card TAM rising from approximately US$1.6bn in 2026E to US$5.9bn in 2028E. MPI is the most aggressive expander in our industry forecast model, with MEMS probe card capacity expanding by more than 4x vs 2025 levels in 2027E (100% CAGR), while probe card peers are also expanding capacity by 35 40% CAGR. We acknowledge that selected chip probing workloads moving from TSMC turnkey towards OSATs opens an accessible opportunity for MPI, but we see competition risk as global leading probe card players are also actively invest ing, even locally in Taiwan, to grasp this opportunity.
• Not yet a leader in MEMS technology.Probe card m/s allocation is very technology driven and the industry dynamic is winner takes most. While the market is optimistic about MPI's capability to grasp MEMS probe card m/s in key HPC projects, we are reserved on this front given already well established players such as Technoprobe (TPRO IM, covered by Craig A McDowell) and FormFactor (FORM US, NC) are also aggressively expanding. We acknowledge that MPI also benefits from the solid probe card TAM growth but we think it should be viewed as one of the beneficiaries instead of of the only one. Our base case includes the confirmed new projects for MPI: we assume MPI takes 20%/25%m/s of AMD's probe card demand in 2027/28E. Howev er, we are more cautious in our assumptions about MPI expanding meaningfully into other HPC projects apart from existing customers (Broadcom switch/TPU, AWS Trai mium/Graviton, Nvidia CPU/LPU /gaming GPU etc). At the company level, we expect MEMS probe cards to account for 20%/35%/48% of MPI's total rev in 2026/27/28E.
• CPO an optionality rather than a major rev pillar. MPI's development spans Inser tion 2 wafer level testing and Insertion 3 die level testing. Our base case already assumes MPI captures 50% of the addressable Ins 2 opportunity (vs street 70%+ m/s), while we also discount the rev by 50% to factor in the possibility for ins 2 to be canceled due to testing time optimization. The result implies ~3%/3% rev mix from ins-2 eq ipment in 2027/28E. We also assume MPI ships 56/80 units of CPO ins 3 die level prober in 2027/28e and estimate this business to account for 6%/6% of MPI 2027/28E rev. While MPI's share has been volatile on CPO equipment chatters (m/s allocation and whether ins 2 will be cancelled), we believe it should be viewed as a good to have optionality instead of a major rev driver (note that CPO equipment margin is only similar to slightly higher vs corporate average so the OP contribution is similar to the rev contri bution). Our 2028E EPS forecast for MPI is 12% lower than consensus.
• Initiate at N. O r Dec-27 PT of NT$5,350 is based on 28x 2028E P/E, a 2x premium to WinWay's 26x, narrower than the typical street premium of 6 8x. We see limited scope for further multiple expansion absent clearer evidence of sustained MEMS share and CPO equipment order finalization. Key upside risks include higher Insertion 2 share, peer delivery delays and stronger than expected localization benefit.

Sources for: Style Exposure - J.P. Morgan Global Markets Strategy; all other tables are company data and J.P. Morgan estimates.

— 6223.TW Price (NT$)

— TSE (rebased)

Company Data

Key Metrics (FYE Dec)

Summary Investment Thesis and Valuation

Investment Thesis

We are Neutral on MPI. Despite expected strong probe card TAM growth in the coming years and MPI's strong capacity expansion, competition across MEMS probe cards remains a big concern as the market is already dominated by other established players such as Technoprobe and FormFactor (both also expanding aggressively). We are genuinely positive on the structural growth of advanced probe card demand and we forecast an FY2026-28E EPS CAGR of 73%. Our caution is about valuation multiple and and the competitive landscape, not about the momentum of growth of the probe card industry.

Val ation

Our Dec 27 TP is based on 28x 2028e EPS. 28x is on par with its P/E average since 2023 (excl extremes). We believe this multiple is justified given the probe card industry is witnessing a structural upcycle driven by stong AI demand.

PI Earnings Estimates

Table 11: J/S Highlights: Annual JPMe vs Consensus

NT$ mn except for EPS

Consensus data is as of 22 Oct 2026.

Source: J.P. Morgan estimates, Bloomberg Finance .P.

Figure 56: MPI rev & YoY growth

Source: J.P. Morgan estimates, Company data.

Figure 58: MPI rev by segment

Source: J.P. Morgan estimates, Company data.

Figure 57: MPI EPS & YoY growth

Source: J.P. Morgan estimates, Company data.

Figure 59: MPI rev mix by segment

Source: J.P. Morgan estimates, Company data.

Figure 60: MPI 2026E rev mix by client

70%

Source: J.P. Morgan estimates.

80%

Figure 61: MPI 2026E probe card rev mix by client

Source: J.P. Morgan estimates.

Figure 62: HPC probe card TAM growth

Source: All data is based on J.P. Morgan estimates.

PI Investment Thesis

Strong probe card TAM growth

Figure 63: Probe card players' capacity expansion CAGR (2025-27E)

Source: All data is based on J.P. Morgan estimates.

New c stomer AMD

We expect MPI to start supplying probe card for AMD starting from its PC CPU project and to later expand into regular server CPU and GPU projects. We are estimating MPI's m/s for these chip projects at 20%/25% in 2027/28E. Our scenario analysis suggests that there's 2%/3% upside to MPI's rev if it captures 35/50% m/s in 2027/28E.

Table 12: Scenario analysis on AMD project contribution

Source: J.P. Morgan estimates.

Chip probing o tso rcing

Opport nity: Selected chip probing workloads moving from TSMC toward OSATs

Chip probing (CP) can be performed in house at TSMC (typically for more technically advanced projects or extrernally by the OSAT/testing houses. Based on our channel checks, TSMC capacity constraints could gradually drive selected CP workloads shifting toward OSATs, although sourcing decisions remain program specific. One example is Vera/Rosa CPU probing begins to move toward Amkor from 2026E, gains greater momentum in 2027, and may broaden toward ASE/SPIL thereafter, with selected peripheral programs following from 2028E. Historically, TSMC sources the components from selected vendors, with very close collaboration with Technoprobe (TPRO IM, covered by Craig A McDowell), which provides the majority of pins for TSMC turnkey products. Hence, this increasing CPU and peripheral chip outsourcing provides the more accessible opportunity for other probe card suppliers, especially the domestic players.

We assume MPI captures 55% of the outsourced Vera/Rosa probing opportunity, translating into estimated revenue of approximately NT4bn /6.7bn/11.3bn in 2026/27/28E, equivalent to roughly 19%/18%/21% of group revenue. Our share assumption leaves upside potential if the final supplier pool remains concentrated.

Table 13: MPI Vera/Rosa probe card rev contribution

%; NT$mn

Source: J.P. Morgan estimates.

Capacity expansion & strong local support

3x capacity expansion to tackle strong TAM growth

Our modelled probe card pin capacity across major suppliers increases from ~355mn pins in 2026E to 632mn pins in 2028E, led by MPI, Technoprobe, FormFactor and Micronics Japan (6871 JP, NC). MPI is the most aggressive expander in our framework, with modeled VPC capacity (cobra + MEMS pins) reaching approximately 3x its 2025 level by 2027E (~80% CAGR), vs other probe card players' aggregate expansion cadence at ~38% CAGR. We read this two ways: capacity is a necessary condition for capturing the AI probing upcycle, and MPI is positioning more decisively than anyone, but simultaneous additions across several well capitalized incumbents erode the lead time scarcity that supports pricing power.

Also note that in advanced probe cards, capacity availability does not by itself secure revenue due to more concentrated market share landscape (winners take the most). MPI's utilization will therefore depend on the outcome of qualifications outcomes of the major AI chip testing projects, rather than on industry demand alone.

Strong local s pport the key advantage; b t migration to MEMS introd ces ncertainties

We believe that local support and response time is a key factor behind share allocations, and these are probably the key advantages vs global peers such as Technoprobe and FormFactor. However, we would not overstate the durability of this: service advantage improves the probability of retaining allocation, but it does not override a qualification outcome in the probe card industry, where technology is still the dominant factor. MEMS technology is where we think MPI's position is weaker relative to global probe card leaders such as Technoprobe and FormFactor. For years, MPI has excelled in cobra pin probe cards, a more mature type of pin technology vs the MEMS which is becoming more prevalent. Currently, Broadcom, which is one of MPI's largest customers, still adopts Cobra pins. We have not yet modelled Broadcom's transition to MEMS through 2028E. But note that the migration, if it happens, could open doors to more competition.

This leads to an important development trend that's not well discussed by investors: that key global competitors are also ramping up their operation scale in Taiwan. Globally, the probe card industry is led by two players, Technopobe and Formfactor, which together have 60 70% m/s in 2026E, according to our estimates. In the past, Technoprobe has been more focused on a major customer (TSMC), while Formfactor has been focused on memory plus US foundries. The investment efforts across several of these well capitalized incumbents could reduce lead time scarcity, moderate pricing power and make supplier specific share gains more dependent on actual qualification outcomes. High technical entry barriers therefore do not necessarily imply low competitive intensity once vendors enter the qualified supplier pool.

We see Technoprobe raising its capex for 2027E. Meanwhile, the company has built multiple in house PCB producers, including some located in Taiwan (such as DIS Tech). Technoprobe also works closely with Taiwan supply chain, including WinWay (Technoprobe signed a 5 year supply agreement with WinWay), plus equipment vendor Innostar (7828 TT, covered by William Yang), where Technoprobe has the exclusive right to utilize the patented double arm needle assembly machine.

Figure 64: Global probe card MEMS pin supply and demand

Source: All data is based on J.P. Morgan estimates Source: All data is based on J.P. Morgan estimates

Figure 65: Global probe card MEMS pin supply breakdown

Figure 66: Technoprobe global presence and presence in Taiwan - DIS (probe card PCB) and YeeWei (probe card assembly equipment)

Source: Technoprobe

Another consequential recent development, in our view, is FormFactor (FORM US, NC) sec ring a position as a second q alified probe card s pplier for Nvidia GPUs man fact red at TSMC. It has announced a target to increase foundry & logic rev mix (logic probe card) relative to memory probe card in 2030E vs 2025. With both global leaders now committed to logic MEMS and both adding capacity, we think MPI's position looks less like a dominant VPC incumbent extending into MEMS and more like a capable third entrant in a market where the two largest players hold materially longer MEMS track records.

Accordingly, MPI's earnings upside will increasingly depend on differentiated qualification wins, product mix and sustained customer allocation - not simply on being the fastest supplier to add capacity. This execution burden remains an important reason for our Neutral stance.

Prober business leads to CPO and other opportunities

MPI was founded as a semiconductor equipment company, and three decades of prober and photonics engineering positions it for CPO and emerging test solutions. The company's equipment heritage is, in our view, the least appreciated asset on the balance sheet. Both the chairman and current CEO came from semiconductor backgrounds and positioned MPI as an equipment company from the outset; probe cards arrived later, when Micronics Japan (6871 JP, NC) transferred CPC (Cantilever Probe Card) technology in 1995 to stay focused on memory. MPI did not pivot away from equipment thereafter: it entered optical electrical measurement in 2001, became the global No.1 in LED equipment by 2002, launched its prober in 2014, and acquired US and European teams in 2014 15 that brought thermal capability. VPC and MEMS were subsequently developed in house.

Equipment accounts for ~25% of MPI's total revenue. Advanced Semi Test segment (AST), which is wafer prober equipment, accounts for ~80% of equipment rev (10 15% of total rev). MPI's wafer prober is mainly used for R&D purposes, with customers ranging from companies, labs, to universities. We note that the same engineering base that produces a flexible R&D prober, an optical electrical LED tester and a -100°C to +300°C thermal device is the base from which CPO tooling and advanced thermal chucks are built. The Focus Microwaves acquisition (completed in 2025) - one of only two tuner patent holders - fits a consistent pattern of securing capability ahead of demand. CPO insertion tooling is therefore a natural course of development.

Table 14: CPO testing insertion 1-4

Source: J.P. Morgan

We believe MPI's prober expertise confers two advantages: better compatibility between the probe card and the prober, and the ability to develop customized probers as new test demands emerge. More consequentially, it can integrate new functions into a prober rather than supplying a standard platform when new test demands appear this flexibility is important when it comes to providing timely equipment solutions to new testing specifications like Co Packaged Optics (CPO).

CPO co ld help re-rating; however the o tlook for insertion-2 stage is still ncertain...

CPO (Co packaged Optics) is the chip design that integrates optical engines (OEs), which converts signals between electrical form and optical form. The manufacturing process involves bonding an optical wafer (PIC) and an electrical wafer (EIC) together, dicing the double sided wafer into OE, and mounting the OE onto the substrate alongside switch chip. As each step poses failure risk, CPO requires testing after each stage CPO testing is called insertion 1 to 4. Insertion 1 is the test for PIC. Insertion 2 is the double sided test after PIC and EIC are bonded with each other. Insertion 3 is to test each separate OE after they are diced from wafers. Lastly, insertion 4 takes place after OEs are mounted onto the substrate next to switch chip and serve as the test for the whole chip system's function.

MPI's CPO development spans both Insertion 2 wafer level optical electrical testing and Insertion 3 die level optical engine testing, extending the company's role beyond probe cards and test interfaces into integrated test equipment. We believe MPI's relevant differentiation lies in system integration: few suppliers hold all of these capabilities, and assembling them across multiple vendors is slower than sourcing from one.

Insertion 3 die-level prober

We are modelling CPO insertion 3 to account for 6%/6% of MPI's total rev in 2027/28E. Key assumptions include 1) 20/15 seconds testing time per die in 2027/28E, 2) 50% testing buffer (in addition to the testing demand), and 3) MPI holds 100% m/s.

Table 15: MPI CPO insertion-3 equipment model

Source: J.P. Morgan estimates.

Insertion-2 wafer level prober

We are modelling CPO insertion 2 to account for 3%/3%% of MPI's total rev in 2027/28E. Key assumptions include 1) 20/15 seconds testing time per die in 2027/28E, 2) 50% testing buffer (in addition to the testing demand), and 3) MPI holds 50% m/s.

However, recent industry discussions have repeatedly raised the prospect of the Insertion 2 being reduced or removed to contain total test time - a recurring driver of share price volatility on which investors remain divided. Management regards cancellation as unlikely while COUPE yields sit well below 100%. We nevertheless believe reduction/removal of Insertion 2 can't be ruled out at this point due to the substantial time and resources required by the process. Therefore, we discount our 2027E ins 2 equipment rev by 50% of probability (of the process to be included) to factor in the possibility that insertion 2 is cancelled. We note that the decision rests with the chip designer rather than with MPI, the foundry or the OSAT.

On the market share/competition side, we currently assume 50% share. Main competitor FiconTEC (under RoboTechnik Intelligent Technology, 300757 CH, NC), had its equipment qualified earlier, but we note that MPI's competitors' probers could be short of mass production requirements on speed, cooling and automation, according to our industry checks. Meanwhile, we believe MPI outperforms peers on automation readiness and wafer level test experience from wafer sorting. Hence, we think it's reasonable to assume 50% m/s for MPI despite the later qualification.

Table 16: Scenario analysis for MPI's CPO insertion-2 rev

Source: J.P. Morgan estimates.

Strong earnings revisions so far, but risks should not be overlooked

We remain constructive on the structural growth of advanced probe card demand, supported by rising AI accelerator shipments, increasing test complexity and higher probe content per device. However, we believe the current valuation already discounts a meaningful portion of MPI's medium term earnings growth and CPO related optionality. Several assumptions required to sustain further upside - MEMS supplier allocation, the probe card sourcing decision flow, peer capacity expansion, the in house PCB ramp, and the commercialization path for Insertion 2 and Insertion 3 equipment - remain difficult to underwrite with high confidence.

MPI's current valuation implies investors are already underwriting robust probe card growth through 2027 28E, continued margin expansion and a meaningful contribution from CPO related equipment. While our earnings forecasts remain strong - we project a FY2026E 28E EPS CAGR of 73% - we see limited scope for further multiple expansion unless the company provides clearer evidence of sustained MEMS share, successful CPO equipment qualification and repeat production orders. Our Neutral rating is a statement about what is already in the price, not about the quality of the franchise.

Figure 67: Recent sell-side MPI 2027E EPS revisions

Source: Bloomberg Finance .P.

Figure 68: Recent sell-side MPI 2028E EPS revisions

Source: Bloomberg Finance .P.

Valuation: 28x 2028e EPS

We believe probe cards still command a technology premium over sockets, but a narrower one than the market applies: MPI at 28x vs WinWay at 26x. Our Dec 27 PT is based on 28x 2028E P/E. We retain a premium for probe cards over sockets, consistent with general market practice and with the view that higher technical requirements warrant a higher multiple.

We would stress, however, that our 2x spread to WinWay's 26x is considerably narrower than the typical street premium of 6 8x, as we re iterate that MPI does not necessarily stand out to us in the industry's migration to MEMS probe card (even with higher technology barriers). The probe card technical barrier argument is sound, but the competitive environment should not be overlooked: allocation is winner takes most and resets at each qualification, whereas we expect incumbent socket vendors to hold their leadership positions comparatively well.

MPI currently trades at 40x/25x 2027/28E EPS (JPMe). Probe card peers are currently trading at approximately 35x/25x 2027/28E EPS, versus 26x/21x for FT/ SLT sockets. We assign a ~15-20% PE premium vs global peers to MPI due to its competitive advantage from strong local support.

Figure 69: MPI 1-year forward P/E band

Source: J.P. Morgan estimates, Bloomberg Finance .P.

Investment Risks

Downside risk: CP test time reduction across chip generations

Our CP TAM build assumes test time and insertions rise with device complexity (10 15% CAGR). If adaptive testing, improved analytics or tester throughput gains compress CP test time faster than we model, pin consumption and card replacement frequency per platform would grow more slowly. We regard the risk as lower at the leading edge than in mature nodes - adaptive test reduction is most applicable where processes are stable and yields high, which is not the case for new AI accelerator ramps - but it remains a structural check on the TAM.

Downside risk: CPO insertion-2 cancellation

Our base case includes Insertion 2 revenue of approximately NT$1.1bn/1.4bn in 2027/28E (3%/3% of 2027/28E rev). Insertion 2 has been a key cause of share price fluctuations given recurring industry discussion of the process being reduced or removed to control total test time, and investors remain divided on the outcome. The corollary is symmetric: if the process remains in place, there is potential upside to both earnings and the multiple. The industry level constraint is that Insertion 2 wafer level volumes remains limited by the absence of automated equipment for PIC EIC optical side fiber array alignment, which is still performed largely manually - until that clears, volume and revenue contribution will stay modest regardless of share.

Downside risk: PCB importance rising in probe cards, and MPI's in-house ratio is still low

PCB is becoming the bottleneck and the value add in probe cards, and MPI is starting from a low in house base; planned ramp from ~5% to 50% by 2H27E is ambitious and, in our view, carries some execution risk. We regard the rising importance of the probe card PCB as one of the more underappreciated risks to MPI's competitive position. The physics are demanding: the distance that power current and electrical signal travel through the PCB is far greater than through the pin, and while an individual pin carries current from a single IO or bump, the PCB aggregates all of them. Power delivery and thermal management problems are therefore multiplied at the PCB rather than at the pin, and as pin counts and power envelopes rise, the PCB increasingly determines whether a probe card qualifies at all. Several of MPI's competitors recognized this early and secured captive supply - Technoprobe through DIS in Taiwan, which it acquired in 2023; FormFactor through Microprobes in US, which it acquired in 2012.

PCB expansion bottleneck: 1) technology and experience, 2) eq ipment lead time

MPI is responding. Management aims to raise its in house PCB ratio from approximately 5% currently to around 50% by 2H27, which would materially reduce dependence on external supply at a time when testing PCB availability is tightening. We are cautious on the timeline for two reasons. First, probe card PCBs are genuinely difficult to mass produce at scale; yields on high layer count, fine line designs are hard won, each design is customized to a specific chip design, and the learning curve is measured in years rather than quarters - which is precisely why incumbents buy capability rather than build it. Second, equipment lead times for the relevant process tools currently exceed twelve months, which compresses the window for installation, qualification and yield ramp ahead of a 2H27E target.

J PMORGAN

J PMORGAN

A shortfall against this plan would leave MPI exposed to external PCB tightness in the period when probe card demand is scaling fastest, and could constrain its ability to convert pin capacity into shipped cards. We would note the read across: the same dynamic that creates risk for MPI creates opportunity for CHPT, which we discuss below.

Downside risk #4: competition

Ind stry expanding aggressively with no stable market share

We believe the debate is no longer whether advanced AI programs will adopt more MEMS probe cards, but which suppliers will ultimately secure production allocation. Probe card selection is highly technology driven: multiple vendors may participate in parallel during design in and qualification, but volume production typically narrows to a single or dual source structure. This creates a winner takes most outcome, where relatively small differences in technical performance, qualification timing or production readiness can lead to materially different revenue allocation. Procurement ownership and procurement authority also vary across TSMC turnkey, customer managed and outsourced CP models, making supplier outcomes project specific rather than uniform.

Capacity availability does not by itself secure revenue. MPI's utilization will depend on the outcome of several large AI programs rather than broader industry demand alone. A favorable qualification outcome could allow the company to convert capacity into share gains, but weaker allocation or delayed ramp could leave utilization below plan despite a structurally strong end market. MPI's capacity nearly triples between 2025 and 2027E, meaning depreciation, staffing and ramp up costs were incurred ahead of the full revenue contribution. On the flip side, we do not see signals of this today: lead times remain long, and some players in the industry require customers to pre pay to secure capacity - a reliable indicator of genuine tightness.

Peer investment also limits the extent to which MPI's expansion creates a lasting scarcity advantage. Technoprobe, FormFactor and Micronics Japan are all adding capacity, while our model does not fully capture potential additions from emerging Chinese suppliers.

Litigation is an established feat re of this market

Probe card IP is actively enforced rather than merely held. Technoprobe sued FormFactor in the District of Delaware in August 2023. The case was dismissed with prejudice in June 2025, with a second Delaware action filed May 2024 and terminated the same month. For MPI specifically, we would highlight that it is already a participant in this dynamic: in April 2026 MPI sued Technoprobe in the Eastern District of Texas alleging infringement of patents covering probe card technology.

Upside risk #1: CPO ins-2 mass shipment could lead to rerating

Peer capacity ramp slippage or q alification delay

Given extended industry lead times and the winner takes most structure of probe card allocation, a peer delivery delay - whether from capacity ramp execution, qualification slippage or PCB supply constraint - could redirect allocation to MPI faster than we model. Localization becoming a stronger advantage than we anticipate is a related upside.

Upside risk #2: m/s gain if peer delivery delays

In a d al-so rce str ct re, the s pplier that delivers capacity gains share

Probe card capacity remains tight across the industry. Pins, PCBs and equipment assembly are all constrained at once, and adding capacity is limited by hiring as much as by equipment. Customers typically qualify two vendors, and the split can move from 50/50 to 70/30 or 80/20 depending on how each vendor performs. Because a single card takes at least 12 weeks to fabricate and 60 70% of orders are placed before volume production, a peer that falls behind on capacity ramp, pin yield or PCB supply can lose allocation quickly. There is precedent: MPI regained major supplier status at a key GPU account after a competitor's solution proved unstable, and shortened product cycles left the customer no time to tune it.

We think MPI is positioned to capture this kind of reallocation. Management cites product stability - in one customer comparison, two months of continuous running against two weeks for a peer - along with faster local repair and response than Western competitors. MPI is also adding capacity, with MEMS pin capacity expanding by 810mn/month in 2027E from 2.5mn/month in 2Q26. We do not include peer slippage in our base case, since Technoprobe has raised its equipment investment outlook through 2028. But if a peer delays, the share gain would flow to MPI faster than our allocation assumptions imply.

Company Background

Leading probe card supplier in Taiwan; dominant in AI ASIC

MPI Corporation is a Taiwan based semiconductor test and measurement company, founded in 1995 and headquartered in Hsinchu, where its probe card and equipment manufacturing is concentrated. The company was set up as a semiconductor equipment business, and probe cards came later through a technology transfer from Micronics Japan (6871 JP, NC), which wanted a logic partner so it could stay focused on memory. We estimate MPI ranks as No.3 in global non memory probe card. Its VPC and MEMS technologies were both developed in house.

MPI focuses on logic probe cards and does not compete in memory. Its main customers are AI ASIC, networking, gaming GPU and consumer SoC designers. It has supplied many of the largest AI ASIC programs since 2024, including Broadcom's TPU and AWS's Trainium, and works both through networking design houses and directly with hyperscalers. Structural trends are pushing demand up: more pins per card, migration from VPC to MEMS, and higher power. Each of these raises the engineering content of a probe card and makes a stable, high volume pin supply more valuable.

Also an equipment company

MPI's revenue comes from four businesses:

• Probe cards (~70% of revenue): cantilever (CPC), vertical (VPC) and MEMS. Substrates are already 100% in house. The company aims to raise its in house PCB ratio from about 5% to around 50% once a new PCB factory starts production in 2H27E, which would make all three key components in house.
• Advanced Semicond ctor Test (AST): R&D probers, where MPI and FormFactor (FORM US, NC) split the market roughly 50/50.
• Thermal test: systems that can move test temperatures between -100°C and +300°C within seconds.
• Photonics a tomation: built on its LED equipment heritage. This is the foundation of its optical electrical CPO test development.

Table 17: MPI income statement

NT$m

Source: J.P. Morgan estimates, Company data.

PI income statement

Investment Thesis, Valuation and Risks

MPI(Neutral; Price Target: NT$5,350.00)

Investment Thesis

We are Neutral on MPI. Despite expected strong probe card TAM growth in the coming years and MPI's strong capacity expansion, competition across MEMS probe cards remains a big concern as the market is already dominated by other established players such as Technoprobe and FormFactor (both also expanding aggressively). We are genuinely positive on the structural growth of advanced probe card demand and we forecast an FY2026-28E EPS CAGR of 73%. Our caution is about valuation multiple and and the competitive landscape, not about the momentum of growth of the probe card industry.

Val ation

Our Dec 27 TP is based on 28x 2028e EPS. 28x is on par with its P/E average since 2023 (excl extremes). We believe this multiple is justified given the probe card industry is witnessing a structural upcycle driven by stong AI demand.

Risks to Rating and Price Target

Upside risks: 1) rev contribution and re rating from earlier than expected CPO equipment insertion 2 orders, 2) m/s gain in key HPC projects .

Downside risks: 1) Chip probing time reduction, 2) slower than expected probe card pin count growth, 3) market share loss in key AI chip projects, and 4) deceleration of CSP's AI capex.

MPI: Summary of Financials

Source: Company data and J.P. Morgan estimates

Note: NT$ in millions (except per-share data).Fiscal year ends Dec. o/w - out of which

Overweight

6510.TWO, 6510 TT

Price (22 Oct 26):NT$3,065.00 Price Target (Dec-27):NT$4,900.00

Technology

erry Tsai AC (886-2) 2725-9867 jerry.tsai@jpmorgan.com J.P. organ Securities (Taiwan) Limited

Style Exposure

Chunghwa Precision Test Tech

PCB becoming the next technology bottleneck; OW

We re iterate our Overweight rating on CHPT, which we view as the most direct beneficiary of rising test intensity within the PCB layer of the test interface stack. As probe cards scale toward higher pin counts and multi kilowatt power envelopes, the PCB - not the pin - is increasingly where the engineering difficulty and the bottleneck sit (recall in an earlier section that ASP per pin increase is only 0 5% annually), and CHPT is the only player spe cializing in probe card PCBs.

• PCB content in probe cards is rising, and the technology barrier is rising with it. The physics favor the PCB as the hard problem. Current and signal travel far further through the PCB than through the pin, and while a pin carries load from a single IO or bump, the PCB aggregates every one of them - so power delivery and thermal stress are multiplied precisely where the design is most constrained. As pin counts move from thousands to tens of thousands, high layer count, fine line probe PCBs increasingly determine whether a card qualifies at all. The evidence that the market is catching up to this is in CHPT's order book: the company is being approached by a widening set of chip makers directly, and is now winning probe card total solution orders rather than compo nent orders alone. Supply is tightening on two fronts simultaneously - a rising number of chip designs, each requiring its own customized probe PCB design, and the value add from advanced packaging proliferation. That the established probe card players secured captive PCB capability early is the clearest validation of the thesis: FormFactor acquired Microprobe in US in 2012 and Technoprobe acquired DIS in Taiwan in 2023.
• CHPT at 30x 2028E P/E; re-rating is possible - PCB deserves the premi m over probe card pins. We re iterate our target 30x multiple on 2028E EPS (36x 2027/28E average EPS), the highest in our test interface coverage. Meanwhile, we don't rule out the possibility for CHPT to be re rated. We believe the company has the best chance of upward earnings revisions driven by more PCB (CHPT is the top player in probe card PCB) and probe card total solution order wins over the coming years, due to rising com plexity of probe card PCB and technology barriers. In addition, PCBs - where the com pany leads globally - are required for both probe cards and load boards (FT, SLT, burn in), the latter being where sockets are installed. CHPT therefore participates in the growth of both halves of the test interface market rather than taking a side, and benefits whether test intensity shifts left into CP or right into FT and SLT. We expect the impor tance of probe card PCB to be increasingly recognized, and see that recognition as the mechanism by which the multiple is sustained.
• B y on p ll-back. In the past 1 month, CHPT's share has fallen 17% vs TWSE 5% due to profit taking actions on the overall test interface segment (WinWay 17% while MPI 9%). The stock is now trading at 26x/19x 2027/28E JPMe EPS, which we think is unde manding given that the company is becoming the key technology value add in the probe card design and therefore enjoys bargaining power to ask for probe card pin business (while PCB's importance should surpass pin in probe card, we note that pin's content value is 4 5x vs PCB in one single probe card). We see upside risk to our 2027E and 2028E estimates on more total solution probe card (PCB+pin) project wins. We encour age investors to accumulate the stock on the recent pull back.

— 6510.TWO Price (NT$)

— TSE (rebased)

Company Data

Key Metrics (FYE Dec)

Summary Investment Thesis and Valuation

Investment Thesis

CHPT's share price has been volatile YTD on lingering concerns about TPU v9 probe cards. As the project settles, we believe the spotlight will shift back to the strong earnings growth driven by Nvidia's GPU project. With strong technology expertise in producing high pin count and high layer test interface PCBs, we believe the increasing test interface complexity will help increase CHPT's presence in AI accelerator testing boards, which includes not only the flagship probe card and FT PCBs, but also SLT and burn in testing boards. The current valuation (discounted to other Taiwanese probe card peers) marks a good entry point for the stock, in our view.

Val ation

Our Dec 27 PT of NT$4,900 is based on a P/E multiple of 30x 2028E earnings (36x 2027/28E average earnings), the average of mid cycle multiple since 2019 (excluding extremes). 30x is the highest multiple in our test interface coverage (we assign 26/28x to WinWay/MPI), as we see the strongest earnings upgrade potential on CHPT's strength in probe PCBs, which is becoming a key binding constraint on probe PCB supply.

Performance Drivers

64%

Figure 70: Probe card structure

Source: J.P. Morgan

Table 18: Technoprobe & FormFactor's recent PCB company acquisitions

Source: Company data, J.P. Morgan.

Figure 71: CHPT potential total-solution probe card rev

Source: J.P. Morgan estimates.

Investment Thesis, Valuation and Risks

Chunghwa Precision Test Tech(Overweight; Price Target: NT$4,900.00)

Investment Thesis

CHPT's share price has been volatile YTD on lingering concerns about TPU v9 probe cards. As the project settles, we believe the spotlight will shift back to the strong earnings growth driven by Nvidia's GPU project. With strong technology expertise in producing high pin count and high layer test interface PCBs, we believe the increasing test interface complexity will help increase CHPT's presence in AI accelerator testing boards, which includes not only the flagship probe card and FT PCBs, but also SLT and burn in testing boards. The current valuation (discounted to other Taiwanese probe card peers) marks a good entry point for the stock, in our view.

Val ation

Our Dec 27 PT of NT$4,900 is based on a P/E multiple of 30x 2028E earnings (36x 2027/28E average earnings), the average of mid cycle multiple since 2019 (excluding extremes). 30x is the highest multiple in our test interface coverage (we assign 26/28x to WinWay/MPI), as we see the strongest earnings upgrade potential on CHPT's strength in probe PCBs, which is becoming a key binding constraint on probe PCB supply.

Risks to Rating and Price Target

Downside risks include: 1) slower than expected capacity expansion; and 2) market share losses in key HPC projects.

Upside catalysts include: 1) better than expected share allocations for major SoC clients; and (2) a faster than expected pace of new application adoption.

Chunghwa Precision Test Tech: Summary of Financials

Source: Company reports and J.P. Morgan estimates.

Note: NT$ in millions (except per-share data).Fiscal year ends Dec. o/w - out of which Analyst Certification: The Research Analyst(s) denoted by an 'AC' on the cover of this report certifies (or, where multiple Research Analysts are primarily responsible for this report, the Research Analyst denoted by an 'AC' on the cover or within the document individually certifies, with respect to each security or issuer that the Research Analyst covers in this research) that: (1) all of the views expressed in this report accurately reflect the Research Analyst's personal views about any and all of the subject securities or issuers; and (2) no part of any of the Research Analyst's compensation was, is, or will be directly or indirectly related to the specific recommendations or views expressed by the Research Analyst(s) in this report. For all Korea based Research Analysts listed on the front cover, if applicable, they also certify, as per KOFIA requirements, that the Research Analyst's analysis was made in good faith and that the views reflect the Research Analyst's own opinion, without undue influence or intervention.

All authors named within this report are Research Analysts who produce independent research unless otherwise specified. In Europe, Sector Specialists (Sales and Trading) may be shown on this report as contacts but are not authors of the report or part of the Research Department.

Important Disclos res

• Market Maker/ Liq idity Provider: J.P. Morgan is a market maker and/or liquidity provider in the financial instruments of/related to WinWay Technology, MPI, Chunghwa Precision Test Tech or related entities.
• Beneficial Ownership (1% or more): J.P. Morgan beneficially owns 1% or more of a class of common equity securities of WinWay Technology or related entities.
• Client: J.P. Morgan currently has, or had within the past 12 months, the following entity(ies) as clients: WinWay Technology, MPI, Chunghwa Precision Test Tech or related entities.
• Client/Non-Investment Banking, Sec rities-Related: J.P. Morgan currently has, or had within the past 12 months, the following entity(ies) as clients, and the services provided were non investment banking, securities related: WinWay Technology, MPI, Chunghwa Precision Test Tech or related entities.
• Non-Investment Banking Compensation Received: J.P. Morgan has received compensation in the past 12 months for products or services other than investment banking from WinWay Technology, MPI, Chunghwa Precision Test Tech or related entities.
• Debt Position: J.P. Morgan may hold a position in the debt securities of WinWay Technology, MPI, Chunghwa Precision Test Tech or related entities, if any.

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WinWay Technology (6515.TW,6515 TT) Price Chart

Source: Bloomberg Finance L.P. and J.P. Morgan; price data adjusted for stock splits and dividends.

MPI (6223.TW, 6223TT) Price Chart

Source: Bloomberg Finance L.P. and J.P. Morgan; price data adjusted for stock splits and dividends. Initiated coverage Aug08, 2014. All share prices are as of market close on the previous business day. Break in coverage Feb 25, 2016 - Oct 26, 2026.

Chunghwa Precision Test Tech (6510.TWO, 6510 TT) Price Chart

Source: Bloomberg Finance L.P. and J.P. Morgan; price data adjusted for stock splits and dividends. Initiated coverage Jun 06, 2018. All share prices are as of market close on the previous business day.

The chart(s) show J.P. Morgan's continuing coverage of the stocks; the current analysts may or may not have covered it over the entire period. J.P. Morgan ratings or designations: OW = Overweight, N= Neutral, UW = Underweight, NR = Not Rated

Explanation of Eq ity Research Ratings, Designations and Analyst(s) Coverage Universe:

J.P. Morgan uses the following rating system: Overweight (over the duration of the price target indicated in this report, we expect this stock will outperform the average total return of the stocks in the Research Analyst's, or the Research Analyst's team's, coverage universe); Neutral (over the duration of the price target indicated in this report, we expect this stock will perform in line with the average total return of the stocks in the Research Analyst's, or the Research Analyst's team's, coverage universe); and Underweight (over the duration of the price target indicated in this report, we expect this stock will underperform the average total return of the stocks in the Research Analyst's, or the Research Analyst's team's, coverage universe. NR is Not Rated. In this case, J.P. Morgan has removed the rating and, if applicable, the price target, for this stock because of either a lack of a sufficient fundamental basis or for legal, regulatory or policy reasons. The previous rating and, if applicable, the price target, no longer should be relied upon. An NR designation is not a recommendation or a rating. Some stocks under coverage have a rating but no price target; in these cases, we expect the stock will outperform/perform in line/underperform the average total return of the stocks in the Research Analyst's, or the Research Analyst's team's, coverage universe of the relevant duration of the region. In our Asia (ex Australia and ex India) and U.K. small and mid cap Equity Research, each stock's expected total return is compared to the expected total return of a benchmark country market index, not to those Research Analysts' coverage universe. If it does not appear in the Important Disclosures section of this report, the certifying Research Analyst's coverage universe can be found on J.P. Morgan's Research website, https://www.jpmorganmarkets.com.

Coverage Universe: Tsai, Jerry : Chicony Power Technology (6412.TW), Chroma ATE (2360.TW), Chunghwa Precision Test Tech (6510.TWO), E Ink (8069.TWO), Elite Material Co (2383.TW), Flexium Interconnect Inc (6269.TW), Radiant Opto Electronics Corp. (6176.TW), Sunonwealth (2421.TW), Taiwan Surface Mount Tech (6278.TW), Tripod Technology Corp (3044.TW), Unimicron (3037.TW), WIN Semiconductors Corp (3105.TWO), YAGEO (2327.TW)

J.P. Morgan Eq ity Research Ratings Distrib tion, as of October 03, 2026

For p rposes of FINRA ratings distrib tion r les only, o r Overweight rating falls into a b y rating category; o r Ne tral rating falls into a hold rating category; and o r Underweight rating falls into a sell rating category. Please note that stocks with an NR designation are not incl ded in the table above. This information is c rrent as of the end of the most recent calendar q arter.

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Completed 26 Oct 2026 08:04 PM HKT

Disseminated 26 Oct 2026 08:11 PM HKT