PDF 原檔：產業_SEMICON2026矽光子論壇_ficonTEC簡報_20260831_original.pdf
原始內容
AI Is Scaling Faster Than Test
Rethinking Wafer, Chip and Module Test for the Photonics Era September 1, 2026 André Lalonde President -ficonTEST Business Unit
TRANSFORM TOMORROW
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With the AI Explosion we need More…
MORE BANDWIDTH
- Higher data rates
- More lanes
- More channels
MORE PHOTONICS
- More optical 1/0
- More integration
- More performance
MORE PROCESS INTEGRATION
- Heterogeneous integration
- Advanced packaging
- System in a package
- Multi-domain test
- Tighter tolerances
- More parameters
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AI Is Scaling Faster Than Test
The AI revolution isn't only a compute problem. It's a manufacturing scale problem -and test is rapidly becoming one of its biggest bottlenecks.
- Greater lanes + higher baud rates
- Greater number of optical channels + electrical I/O
- Tighter tolerances + higher packaging complexity
- Higher device value → higher cost of test escapes
The manufacturing challenge is no longer simply whether a device can be measured; it is whether millions+ can be measured economically
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Moore's Law Is Becoming a Packaging Problem
The device is no longer a chip. It is a system. Test architecture must evolve accordingly.
Photonics must now meet semiconductor standards for volume, yield, quality, and reliability -while adding the optical, precision alignment, automation, and data expertise required beyond traditional electrical test.
The next five years may require the photonics industry to build more high-volume manufacturing and test capacity than it developed during the previous twenty-five.
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Photonics Breaks Traditional Semiconductor Test
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Photonics Breaks Traditional Semiconductor Test
NEW PHOTONIC TEST CAPABILITIES REQUIRED
OPTICAL ARCHITECTURE & SYSTEM DESIGN
PIC architecture, optical system design, wavelength planning
PACKAGING & INTEGRATION
Optical packaging, hermetic sealing, CPO / LPO integration
OPTICAL ENGINEERING & MEASUREMENT
Propagation, insertion loss, ER/OSNR, dispersion, crosstalk, polarization
NEW TEST METHODOLOGIES
Electro-optical test, wavelength sweep, coherent & bidirectional
PRECISION ALIGNMENT & POSITIONING
Sub-micron alignment, vibration control, 6-DOF control
PHOTONIC DATA & Al ANALYTICS
Optical data models, ML/Al for yield, anomaly detection
MATERIALS & FABRICATION
SiPh / III-V / LN, heterogeneous integration, wafer-level features
STANDARDS & QUALITY SYSTEMS
Photonic PDKs, test standards, reliability models
High-volume | High-yield| Low cost per device | Reliable | Scalable for the Al era
PHOTONIC DEVICE ENGINEERING
Modulators, detectors, lasers, couplers, PIC building blocks
FIBER & COUPLING TECHNOLOGY
Fiber attach, array align, mode control, low-loss coupling
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Integrated Disciplines to Enable Photonic Test at Semiconductor Scale
No single traditional test discipline solves the photonic production problem.
Scalability demands top-level expertise in each one of these categories for success.
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Test Must Follow the Device Through Manufacturing
SINGULATED DIE
CPO PRODUCT FLOW: FROM WAFER TO SYSTEM
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Find Failures Early (COUPE example)
1× → 10 × → 100 × → 1,000 × COST OF FAILURE
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Double-Sided Wafer Test Changes the Architecture
TOP Electrical Probes / Probe Card
WAFER
Thermal Chuck
BOTTOM Fiber Array Unit (FAU) Interface
INSERTION 2
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Double-Sided Wafer Tester WLT-D2
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Singulation Creates a New Test Problems
TOP Optical Head Assembly (OHA) / Fiber Array Unit (FAU)
Thermal Chuck
Chip
BOTTOM High Speed Socket Interface
High Speed Probe Card
INSERTION 3
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Double-Side Chip Test DLT-D2
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SLT vs ATE vs Characterization for Insertion 3
| SLT / Loopback | 224G HSIO/ATE Production Test | Full Characterization | |
|---|---|---|---|
| Role | 100% functional production screen | Targeted 224G production measurements | Deep engineering measurement |
| Architecture | DUT optical loopback / mission-mode | External 224G BERT/ O'scope + automation | Bench-class PPG/BERT + O'scopes |
| Coverage | Link, BER, lock, functional faults, power | Selected Tx/Rx parametrics | Full Tx/Rx performance & margins |
| Throughput | Highest | Medium | Lowest |
| Cost/device | Lowest ($) | Medium - High ($$) | Highest ($$$) |
| Best use | HVM screening | Targeted production coverage | Qual / margin / debug / correlation |
THE CHALLENGE: Enable SLT with Near Bench-Class Performance at the Right Cost
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Module Test Moves From Characterization to Production
- Standalone instruments: Individual optical and electrical test equipment
- Engineering Supervised: Manual setup, execution and troubleshooting
- Connections: Lasers, loopback hardware all connected by hand
INSERTION 4
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Module test solutions -High Density
Summary
END-TO-END SCALABLE PLATFORM
· Wafer → Chip/Die → Module seamless continuity
· One architecture across the entire flow
for next-gen speeds
- Future-ready and adaptable
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MAXIMUM THROUGHPUT AND YIELD
- High UPH at every stage
· Advanced alignment, handling, and sorting
- Active control and thermal
management for stability and uniformity
HIGH CHANNEL DENSITY AND INTEGRATION
- Hundreds of optical and electrical channels
Parallel test with 224G+ electrical and optical
- Integrated instrumentation,
optics, motion, and automation
BUILT FOR PRODUCTION
- Production automation end-to-end
Consistent, repeatable, and reliable results
Lower cost of test and higher first-pass yield
Thank you
TRANSFORM TOMORROW
圖片清單（已驗證 2026-10-23）
以 contact sheet 逐張檢視全部 61 張 png＋7 張整頁渲染 jpg。
_001／_003／_009／_016等紫色 SEMICON Taiwan 頁首 banner 帶有講者端訂閱者浮水印（IP／email），一律不引用；整頁渲染_p*.jpg無浮水印，lib 嵌圖只用_p*.jpg。
| 檔名 | size | 分類 | 親眼所見內容 |
|---|---|---|---|
…_ficonTEC簡報_20260831_p08.jpg |
373KB | 真資料圖 | 「Test Must Follow the Device Through Manufacturing」：CPO 產品流程 Wafer→Singulated Die→Assembly→Optical Engine→Module→System，下方 Insertion 1（EIC Probe／PIC Top Side Optical Probe）→2（Dual-Side Wafer Electro-Optical Probing）→3（Die／Engine Test）→4（Module Test & Final Qualification pre-System），箭頭標「Increasing device value – increasing cost of failure」 |
…_p09.jpg |
449KB | 真資料圖 | 「Find Failures Early (COUPE example)」11 步流程：兩片晶圓→Insertion 1→切 EIC、薄化 PIC 並貼合→加透鏡層→Insertion 2 雙面晶圓測試→切 COUPE→貼透鏡陣列→Insertion 3→KGD 合格才進組裝→組模組→Insertion 4；底部箭頭 1×→10×→100×→1,000× COST OF FAILURE |
…_p10.jpg |
310KB | 真資料圖 | 「Double-Sided Wafer Test Changes the Architecture」：Insertion 2 七項挑戰（Mechanical、Correlation、Warpage、Crashes、Repeatability、Thermal、Operational Efficiency）；右為探針照片與堆疊：TOP 電性探針／Probe Card、WAFER、Thermal Chuck、BOTTOM Fiber Array Unit(FAU) Interface |
…_p12.jpg |
323KB | 真資料圖 | 「Singulation Creates a New Test Problems」：Insertion 3 六項挑戰（Mechanical、Optical、Electrical、Thermal、Cleaning、High UPH）；右為治具堆疊：TOP OHA／FAU、Thermal Chuck、Chip、BOTTOM High Speed Socket Interface、High Speed Probe Card |
…_p14.jpg |
427KB | 真資料圖 | 「SLT vs ATE vs Characterization for Insertion 3」比較表（Role、Architecture、Coverage、Throughput、Cost/device、Best use）＋「Enable SLT with Near Bench-Class Performance at the Right Cost」四要素（近 bench 級效能、縮小體積、提高平行度、單通道成本）＝SLT-ready 方案 |
…_p16.jpg |
302KB | 真資料圖 | 「Module test solutions – High Density」Insertion 4 模組測試載板示意：主熱區（可處理 >2–3kW 排熱）、周邊多個低功率熱區、BGA 高壓縮力、專有多頭光纖介面（High Density Fiber Interconnect） |
…_p04.jpg |
374KB | 文字卡 | 「Moore's Law Is Becoming a Packaging Problem」：GPU/Switch＋HBM＋EIC＋PIC＋Lasers＋Fibers 六個 icon 相加與兩段說明文字 |
…_019.png |
2.7MB | 真資料圖 | 半導體測試專長演進（1970s Foundation→2020s Intelligence）與八項核心能力（Test architecture & automation、High-speed electrical、Semiconductor knowledge、Mechanical & handling、Software、Data analytics、Quality & reliability、Ecosystem、Scale & cost），結論列「Outcome: Semiconductor test at massive scale」 |
…_026.png |
1.3MB | 真資料圖 | 環形圖「High-Volume Photonic Test Solutions」：Optics、Signal Integrity、Precision Handling、Thermal、Semiconductor Level Production Test Execution、Standards Development、Software Automation、Data Analytics |
…_040.png |
1.5MB | 真資料圖 | ficonTEC 雙面晶圓測試機 WLT-D2 機台照（機身標示 ficonTEC，側面可見 Teradyne 字樣） |
…_046.png |
1.3MB | 真資料圖 | 雙面晶粒測試機 DLT-D2 機台照（開門可見內部多軸平台，左下標 INSERTION 3） |
…_028、_029、_030、_032、_033（237–357KB） |
— | 裝飾·logo·banner | 流程卡 icon（WAFER／ASSEMBLY／OPTICAL ENGINE／MODULE／SYSTEM）的拆圖，內容已含於 _p08.jpg |
…_035.png |
2.4MB | 真資料圖 | COUPE 11 步流程原圖（內容同 _p09.jpg，含上方 11 張步驟卡，字小） |
…_037.png、_043.png、_052.png |
1.1–1.4MB | 真資料圖 | Insertion 2／3／4 的挑戰環形圖（內容同 _p10／_p12，Insertion 4 為 Cleaning、Precision Alignment、Fiber Handling、Laser Sources、Thermal、Fiber Coupling、Mechanical 七項） |
…_038.png、_044.png |
459／771KB | 真資料圖 | 探針與光纖陣列近照（_038）、高速 socket 與光纖治具特寫（_044） |
…_049.png |
1.2MB | 真資料圖 | SLT 四要素相加等式（內容同 _p14.jpg 下半） |
…_055.png |
2.0MB | 真資料圖 | Insertion 4 高密度模組測試載板（內容同 _p16.jpg） |
…_004–_006、_021–_024、_057–_060（<250KB） |
— | 裝飾·logo·banner | 速度表、光纖束、堆疊晶片、四個圓形 icon 等純圖示，無資料 |
…_007、_008、_010–_015、_017、_031、_050（<350KB） |
— | 裝飾·logo·banner／文字卡 | 「MORE TEST COMPLEXITY」標題圖、Scalable Test Ecosystem 圓環、COMPUTE／MEMORY／PACKAGING／INTERCONNECT／PHOTONICS／TEST 六張示意卡、六元件相加條、Insertion 1–4 單行流程、「INSERTION 3」標籤 |
…_001、_002、_003、_009、_016、_018、_020、_025、_027、_034、_036、_039、_042、_045、_048、_051、_054、_056、_061 |
38–282KB | 裝飾·logo·banner | SEMICON Taiwan 紫色頁首（含訂閱者浮水印，禁引用）／ficonTEC logo／結尾頁 |