產業_SEMICON2026矽光子論壇_ficonTEC逐字稿_20260831

場次：2026 SEMICON Taiwan 矽光子國際論壇（2026-08-31） 講者：André Lalonde（President, ficonTEST Business Unit, ficonTEC） 題目：AI Is Scaling Faster Than Test — Rethinking Wafer, Chip and Module Test for the Photonics Era 對應簡報：產業_SEMICON2026矽光子論壇_ficonTEC簡報_20260831

[00:00:00.00] Hi, I'm the president of FICONTEC, and his title of his talk is AI, Scaling Faster Than Test, Rethink Wafer, Chip, and Module Test for the Photonics Era. Welcome. [00:00:11.68] Thank you. [00:00:20.56] Hello, everyone. I'm Andre. I'm not exactly the president of FICONTEC. I'm the president of FICONTEC, which is a business unit within FICONTEC. [00:00:30.00] So I just wanted to make that distinction. [00:00:32.00] I appreciate the accolades. [00:00:34.00] I try. [00:00:35.00] So. [00:00:36.00] Well, thank you very much. [00:00:39.00] And as you know, ficonTEC has been around for 25 years, and it is our very first time [00:00:44.00] that we do a presentation here at the Semicon conference. [00:00:48.00] So thank you very much for sending me for the opportunity of doing this. [00:00:51.00] Now, I've been doing photonic wafer-level tests for 25 years, and Dr. Haynes, you're [00:00:57.00] absolutely right. [00:00:58.00] You ain't seen nothing yet. This is really going to be something spectacular. [00:01:03.40] And because of AI, photonics, I like to call it a 25-year overnight success. [00:01:10.00] Everything we've done in the past 25, 30 years has really led us to this point. [00:01:14.90] And now photonics really has to grow up and be able to perform like the semiconductor industry. [00:01:20.16] So with the AI explosion, out of all the presentations that you're going to see today and this week, there are three main takeaways. [00:01:30.16] It's going to be more bandwidth, so faster data leads, more wavelengths, more channels. [00:01:35.16] It's going to be more photonics, so like Dr. Harris from Light Matters said earlier today, [00:01:40.16] optics doesn't want to be a long-blown mover. It wants to go inside the box, and so more integration for time. [00:01:47.16] And also more process integration. So you can see in slides today a tremendous amount more process integration that happens now today. [00:01:55.16] So what does that mean for test? That means a tremendous amount more test complexity. [00:02:02.16] So two things that are orthogonal to each other. One, we have to do electrical tests, we have to do optical tests, we have to control thermal, [00:02:11.16] We have to do mechatronic automation. [00:02:13.70] We have to do all these new things to the test process. [00:02:17.96] But orthogonal to that, we have to do it multiple times. [00:02:21.28] We have to do it for wafers. [00:02:22.56] We have to do it for chips. [00:02:23.78] We have to do it for packages. [00:02:25.76] So all these disciplines have to come together and perform at multiple levels. [00:02:31.80] Now, we've talked about Moore's Law morphing a little bit, and now it's becoming more of a packaging problem. [00:02:37.66] Now, the device is no longer a chip, it's a system. [00:02:42.66] As you've seen, you see the entire module is acting as one. [00:02:47.66] So test architecture has to evolve accordingly. [00:02:51.66] So now we have to lump all these things together. [00:02:54.66] We have the GPU, we have the high bandwidth memory, [00:02:58.66] we have electronic ICs, photonic ICs, we have lasers, [00:03:02.66] and we have fibers all together as one. [00:03:05.66] So what does that mean now? We have to scale at the semiconductor level for volume, for yield, for quality and reliability. [00:03:15.66] While we have to add all these other disciplines, precision alignment, automation, and all this other expertise together in order to be able to do a cohesive manufacturing test ecosystem. [00:03:29.66] Now one of the things that we like to say is there's going to be more capacity need in the next five than the next 25 years. [00:03:39.66] Now one thing for Ficotech, we've shipped about 2,000 tools in the last 25 years. [00:03:48.66] And anybody want to guess what we're going to have to ship in the next 12 to 18 months? [00:03:54.66] 1,000 systems. So half of what we shipped in the last 25 years, we're going to have to do in the next 12 to 18 months. So this is crazy. [00:04:07.66] Now essentially, what we need is more factories, we need more infrastructure, but more importantly, one thing that no one has spoken about today is we need more people. [00:04:19.66] We need more graduates, we need more expertise, because these are expertise that are not native into the semiconductor ecosystem that we desperately need today. [00:04:31.76] Now, what I'd like to do is walk you through the last 50 years, kind of a scroll down memory lane, from semiconductor tests. [00:04:39.40] So, building the ecosystem wasn't done overnight. Rome was not built in a day. [00:04:45.32] So in the last 50 years we had the advent of ATEs designed for tests, we had the advent [00:04:52.32] of bringing in high speed electrical, we had the advent of developing wafer probers going [00:04:58.32] from 150 millimeters all the way to 300 millimeters over the last 50 years. [00:05:04.32] And also it's the entire ecosystem of analytics, of data management, of Sextia, of the MES [00:05:11.32] system. All this was developed over the last 50 years in order to be able to test billions [00:05:19.32] of devices, have high yield and world class quality, but extremely low cost per test. [00:05:27.32] And so this is really the goal. Everybody says photonics is very expensive to test. [00:05:32.32] So this is one thing that we strive to do is try to reduce the cost of tests. [00:05:38.32] So now photonics is really going to break traditional semiconductor tests because now we have to add all these new types of expertise to traditional semiconductor tests. [00:05:53.14] Now we have photonic device engineering, as you see today, every single slide was a new photonic type of device. [00:05:59.62] We have optical architecture system design and fiber coupling technology that is very, very important. [00:06:06.30] We have new testing methodologies that need to be developed and also having all the micro precision and optical alignment. [00:06:14.34] But as TSMC was showing today, there's going to be the need of new PDKs and all these other standards that need to be applied as well that haven't been applied to in the past. [00:06:24.88] So it's a whole new ballgame for photonics to really enter the semiconductor ecosystem. [00:06:31.44] So test really has to be able to flow effectively through manufacturing. [00:06:40.44] So when I talked about earlier having different types of devices to test, well of course we all start at the wafer level, [00:06:47.44] go through singulated die, go through assembly, which is something that we also know very well, [00:06:54.44] then have an optical engine and a module and a system. [00:06:58.44] Essentially, as ASE was also showing earlier, showing the different insertions. [00:07:04.38] So at the beginning, we have wafer tests, and I'm going to walk you through in a couple [00:07:08.12] of slides two different types of insertions. [00:07:11.38] Insertion one, which is top-side test, could be EIC or hybrid photonic EIC. [00:07:17.56] And then insertion two, which is a hybridized top-side electrical, bottom-side optical test. [00:07:23.62] Insertion three, which is our dye or optoelectrical test. [00:07:27.56] And then at the end is insertion four, which is the module test for a pre-system qualification. [00:07:33.06] So this is all before everything goes into the box, into the signal. [00:07:37.36] Now one of the major takeaways is as you increase device value, you increase the cost of the failure. [00:07:45.66] So you really want to catch your failures, of course it's common sense, you want to catch your failures very, very early on, [00:07:52.16] that you have all of your high yielding, you get a high yield towards the end of the module. [00:08:00.16] Because the end of the module is very expensive. [00:08:03.00] One of the key takeaways here is the important thing is to correlate and trace at every step [00:08:09.66] of the way. [00:08:10.74] So having a cohesive ecosystem, being able to correlate and trace every step of the way [00:08:16.88] is extremely important. [00:08:18.54] Because when you get to the system right now and you have a field failure that is kind [00:08:23.60] of the kiss of death to a manufacturer, you want to have the ability to backtrack and [00:08:29.22] trace all the way to the wafer to see what happens. [00:08:32.54] And this is what we offer to the community. [00:08:36.32] And so, you know, it's great that TSMC went this morning, so they trained you 100% on [00:08:40.86] COUPE. [00:08:41.86] So you guys are experts in COUPE, right? [00:08:43.86] So I don't need to go through the COUPE details. [00:08:47.30] But COUPE is a perfect example of how we can create this type of test ecosystem. [00:08:52.82] So insertion one is two different types of tests, the EIC test and the photonic test that has some electrical components with optical. [00:09:01.60] And that's tested separately. [00:09:03.42] And then it's brought together in an attachment process where the EICs are attached to the PIC layer. [00:09:10.90] Then insertion two is what we provide as well, is when the lens array is then bonded to the [00:09:20.10] fundamental structure of the wafer. [00:09:22.56] And then we flip it and we test it upside down, where we tested electrical top side [00:09:27.16] and optical bottom side. [00:09:29.46] And then from there we have singulations, so we have the dyes that are singulated and [00:09:34.34] put into trays and transferred to say an OSAT or some other place. [00:09:38.98] And then the other process that we also perform as ficonTEC is performing the receptacle attached [00:09:45.48] process. [00:09:46.48] So we epoxy a receptacle and align it to the substrate. [00:09:51.06] Then we have insertion three where we perform 100% chip test with receptacle. [00:09:57.56] We have other options of six axis alignment as well, but this is really the common one [00:10:02.30] that's out in the industry as well. [00:10:04.72] Now at the end, what is the goal after insertion three? [00:10:08.88] known good die. So you want to make sure this is your very, very last line of defense [00:10:14.56] in order to make sure you have 100% known good parts before you go to module attached. [00:10:22.16] Because that module cannot have any failures at all. And then at the end is insertion four, [00:10:29.02] which is the module attached. Now when you go and you look at the order of magnitude [00:10:35.32] of the cost of failure, it just increases as it goes tremendously. [00:10:41.80] Now what do we offer [00:10:43.16] to the industry in terms of a multi-insertion test line? [00:10:47.18] Well, we have our topside wafer-level prover, and I'll walk you through that in a couple of seconds. [00:10:52.04] We have our double-sided wafer prover that does optical [00:10:55.16] bottom side and electrical top side. We have our [00:10:58.86] singulated die hybrid electro-optical tester. [00:11:02.18] And then in the end we have our high volume HVM module test system. [00:11:10.58] Now our single sided wafer tester, I like to call it our Swiss Army knife. [00:11:14.58] It does a little bit of everything. [00:11:16.64] So essentially we can do EIC testing, we can do silicate photonic pit testing, we can do [00:11:21.90] vertically coupled, we can do edge coupled, we can do VCSELs as well on this tool. [00:11:27.38] We've adapted it for VCSELs. [00:11:29.50] But the other important thing that you're going to see this week as well is there's [00:11:34.50] a company that we've partnered with in Canada called Femto that does laser trimming and [00:11:39.90] laser cleaning. [00:11:40.90] A couple of the folks showed earlier today how dirty lenses get. [00:11:46.24] So we have a process where we could use our wafer tester and clean the lenses on the wafer [00:11:52.22] through laser ablation. [00:11:54.22] Now laser trimming is something different. [00:11:56.74] If you're familiar with the classical laser-trimming and stepping detectors, so imagine it's analogous [00:12:00.98] to that, where you could actually change the index of refraction of a waveguide or a ring [00:12:06.18] resonator and be able to tune it to the correct wavelength of its performance. [00:12:12.36] So what do you do? [00:12:13.48] You save on, you get better yield, and also you potentially save on power because thermal [00:12:19.50] tuners and things like that don't need to be used as much. [00:12:24.56] Now our double-sided wafer tester here, now I want to apologize to my colleague at Advent [00:12:29.24] Test who is also one of the sponsors because we also have it compatible to Advantest, [00:12:33.74] we just don't have the pretty pictures yet. [00:12:36.38] But essentially this is the world's first fully double-sided electrical optical tester [00:12:41.56] designed on the ground up for foundries that has full OHT eFEM loaded and it's fully hard [00:12:50.06] dockable to an ATV. [00:12:52.04] So this is what we're shipping right now. [00:12:54.04] And now it's SECS/GEM capable as of last week. [00:12:57.66] So full factory integration and it's able to both be compatible to Teradyne and to Adventest. [00:13:05.54] And so we're going to be shipping Adventest next month. [00:13:08.08] So good news there. [00:13:11.64] So walking through some of the challenges. [00:13:14.26] You guys don't want me to talk about only the good stuff. [00:13:16.66] I'm going to talk about the bad stuff too. [00:13:18.52] So this is a very, very difficult application. [00:13:22.40] So I'm going to talk to you about what's very difficult for us. [00:13:26.24] You know, we've designed a thermal check that we've patented that has a temperature tolerance of plus or minus 0.5 degrees. [00:13:33.94] So that's industry best for this type of technology. [00:13:37.02] And especially we handle, and you can imagine, when these wafers get stacked up, they have a tremendous amount of warpage. [00:13:46.38] more warpage than any standard silicon wafer. [00:13:50.00] So we've created a special profiling mechanism [00:13:53.16] where we can profile almost perfectly the wafer [00:13:55.96] to be able to contact with industry standard probe card. [00:14:00.00] And on the bottom side, we have a fiber optic array [00:14:03.16] that interfaces to this. [00:14:06.06] This is a fiber optic array over here. [00:14:08.56] So, you know, it's about the price of a small Honda Civic. [00:14:11.80] That's this little fiber array there. [00:14:13.84] And trust me, we've crashed in that so I can afford a G-Wagon. [00:14:16.90] So those are very, very expensive, but they're very high-performing. [00:14:21.46] Now, just to talk to you about the challenges of putting a tool like this in a foundry, [00:14:27.18] we have to have good correlation because it's not just repeatability within the tool from wafer to wafer, [00:14:32.94] but it's also to correlate from tool to tool at a foundry. [00:14:36.58] Because when you're dealing with electrical is one thing, [00:14:39.40] but when you're dealing with photonics, you're dealing with polarization-maintaining fiber, [00:14:43.84] you're dealing with insertion loss, you're dealing with all kinds of crazy things. [00:14:47.84] So having that correlation from machine to machine is extremely important. [00:14:51.84] And dealing, of course, with the operational efficiency and the high workage of the wafers as well. [00:14:58.84] So our double-sided chip tester, our DTE platform, so this we've been shipping for over six months now. [00:15:05.84] It's the world's first unit that does full 224 gigabits per second, full tray loading, [00:15:12.84] full electro-optical test, top side and bottom side. [00:15:16.84] And so that is running product right now at OSATs. [00:15:20.84] And so this is a tool that's now tested over a quarter of a million devices and more. [00:15:27.84] And essentially the challenges on this are very difficult because you have to keep a very high UVH. [00:15:37.12] You have to have a very precision handling of the component because that component is very tiny. [00:15:43.08] The pitch is very small. It's 130 micron or so in pitch for the copper bumps. [00:15:49.78] And the biggest issue is dirt. [00:15:51.36] So keeping things clean, keeping things tidy on the socket and other items is very, very complex. [00:15:59.36] And remember, we're also doing this at full 224 gigabits per second multiple channel. [00:16:06.26] So it's 70 gigahertz of analog bandwidth approximately, and so it's very, very high frequency. [00:16:13.20] So just to walk you through the stack up, we have the thermal chuck and the chip where [00:16:18.58] this thermal chuck is fully thermally controlled. [00:16:23.52] And we have a high speed socket with a high speed pro card interface and we have the OHA [00:16:28.72] or we can have a six axis alignment system with an FAU on the top. [00:16:34.68] So right now our uptime is extremely high. [00:16:38.56] we get close to 100% almost perfect contact rating in our sockets. [00:16:43.56] And our next one is insertion 4, which is our module characterization system that we are developing currently. [00:16:53.56] So I can't show too much because unless you want to sign an NDA, but we can walk you through a little bit about what we're doing here. [00:17:00.56] So the challenge is here, as you can see, and you can see the photographs that you've seen earlier today, [00:17:06.80] the complexity of this module is amazing because you have all these lasers that are going into this one component. [00:17:16.20] And you saw the box topology earlier today with all the ELSDPs that were connected at the front. [00:17:22.12] So essentially imagine hundreds of lasers going into this one little module, being able to manipulate it, [00:17:29.06] being able to contact, being able to manage all the fibers that are going in this in an automated platform. [00:17:35.38] So it's extremely challenging, and especially to keep everything clean. [00:17:40.64] So as you know, the biggest problem with fibers is to make sure that every time you connect it, [00:17:45.84] you have to look at it and you have to clean it. [00:17:47.98] Because yield on this is extremely important. [00:17:51.82] Every single optical engine needs to yield at 100%. [00:17:56.28] And so any dirt, any contamination, anything to affect performance is fantastic. [00:18:02.16] And so just to walk you through some of the challenges, it's a multi-thermal zone type of system where we have lower power thermal that goes around into the optical engines. [00:18:14.90] And we have higher power thermal that's in the center where we have the switch or the GPU chip. [00:18:19.74] And there's going to be, of course, a tremendous amount of force that's going to be pushing down this module into a load board or into the socket. [00:18:30.90] And especially the fiber interface is going to be extremely complicated because you have to have accurate precision for all these fibers and being able to have cleanliness and repeatability to all the fibers around. [00:18:45.52] So some folks have maybe 12 connectors around, some other companies have 32 or 36 optical engines. [00:18:53.52] So a great degree of parallelism is necessary in order to make sure that this can happen effectively. [00:19:01.52] So the next one is, okay, well how do we scale that to production? [00:19:06.52] How do we load them? How do we move them around? How do we do that? [00:19:10.52] And it's our module test platform. [00:19:12.52] So this is something that we're going to start shipping at the end of September, early October. [00:19:16.98] We've started shipping this for OSFPs, and so we're testing 100% fully automated in a dark fab OSFPs at full data rate at 1.6 key. [00:19:29.54] We're going to be also doing ELSFPs as well, the same way, and we're also going to be doing these large area modules the same way as well. [00:19:38.26] So this is a robotic load, robotic unload, fully autonomous type system. [00:19:46.18] And so how are we going to scale? [00:19:48.52] So everybody knows ficonTEC as being a German company, quite small company, just 100 and some odd people. [00:19:55.98] How are we going to build 1,000 systems this year? [00:19:59.00] So we've partnered with folks here in Taiwan. [00:20:03.40] So we're going to be adopting the strategy designed in Germany, built in Taiwan for the foreseeable future. [00:20:10.26] And so the Taiwanese partners that we're working with, they have scalability, they have facilities. [00:20:17.10] We're going to be doing an exclusive photonic partnership, meaning co-development here in Taiwan, of new types of platforms. [00:20:24.50] And these partners that we have, have a tremendous amount of test experience. [00:20:28.90] So just to sum everything up, AI is definitely scaling faster than testing. [00:20:35.90] Everybody knows it. [00:20:36.90] There have been many complaints today about tests, so I'm here to address them. [00:20:40.90] Photonics, they really need to meet semiconductor scale. [00:20:45.90] The last 25 years is not enough. [00:20:47.90] We need to really accelerate. [00:20:49.90] And test has to follow the product. [00:20:52.90] The most important thing is correlation and traceability between all the different insertions. [00:20:57.90] And one thing, of course, we need to take away is all the multiple disciplines that are required in order to make this happen. [00:21:04.90] Disciplines that the semiconductor industry does not have yet and needs to hire or bring in from other experienced sources. [00:21:12.90] And the next challenge is to scale. So really the bottom line is the semiconductor industry took decades to scale to where it is today. [00:21:21.90] And now we in photonics need to do it in a fraction of the time. So thank you very much. [00:21:27.90] Appreciate it. [00:21:35.90] Thank you, Andre. [00:21:36.90] We have a couple of questions. [00:21:41.90] While the microphone goes up, what are the lead times though? [00:21:44.90] I mean, those volumes are staggering. [00:21:49.90] So if I wanted to buy a tool, okay, well. [00:21:53.90] You want the sales approach? [00:21:54.90] But let's say there's an extra tool from a reputable customer of yours, I guess, priority. [00:22:01.90] What are the lead times? [00:22:03.90] So with and without a forecast, I guess that's the sales of it. [00:22:07.90] So we can get lead times down to 12 weeks, 12 to 16 weeks, which is pre-lining material. [00:22:14.90] It's really pre-lining material that's the biggest issue. [00:22:17.90] So once we pre-line material assembly, it's very easy. [00:22:21.90] I have a question on that. Yes, I have a question. In the insertion 2, you showed FAU, right? Is it a temporary FAU or it's a permanent FAU? [00:22:33.90] Permanent. So, define your version of permanent to temporary. What do you mean by permanent to temporary? [00:22:41.90] I mean, is it for only test purpose only or? [00:22:45.90] Yes, it doesn't get epoxy or anything like that. It is a test vehicle on a wafer prober. [00:22:54.90] So it gets used only for tests and it never touches the part. [00:22:59.90] Okay, so in the interface 3 you have this actual FW attached to the PIC, right? [00:23:07.90] No, no, no. It's the lens array. So the coop technology is a lens array on the bottom of the wafer and we align to the lens array on the bottom side of the wafer. [00:23:20.90] We don't touch it. We're about 100 microns away. [00:23:23.90] Okay, so in insertion 3 you still don't have PCFA? [00:23:26.90] No, in insertion 3 what I show here is our version with the fiber attached. [00:23:31.90] So the receptacle, there's a receptacle already on the chip that won't be attached in the previous process. [00:23:36.90] And then we connect the fiber, but we don't click it. [00:23:40.90] So we've developed with a vendor a special connector that doesn't need to be clicked for text. [00:23:47.90] We did that about a year ago. [00:23:51.90] Any other questions? [00:23:56.90] Just a minor curiosity of different materials. So when it comes to TFLN or say BTO, what are some of the potential modest adjustments you foresee on the paranormal? [00:24:09.90] That's probably Dr. Nase's talk. [00:24:18.90] That's not my discussion. [00:24:21.90] Yeah, yeah. [00:24:22.90] Okay. [00:24:23.90] Okay, good. [00:24:24.90] Well, let's thank Andre again. [00:24:26.90] Excellent talk. [00:24:27.90] Thank you. [00:24:28.90] Thank you. [00:24:29.90] And the next talk will be by Aether Lee from Who's the Global Global