PDF 原檔：報告_OCP2026_光寶科_800V到晶片供電_20261015_original.pdf
講者公開簡報（OCP 官方 Recorded Content 頁提供下載）。文字以 PyMuPDF 逐頁抽取，
### p<n>為頁碼；圖表內容見原檔。
圖片清單（已驗證 2026-10-19）
| 檔名 | 頁 | 分類 | 親眼所見內容 |
|---|---|---|---|
報告_OCP2026_光寶科_800V到晶片供電_20261015_p2.png |
p2 | 真資料圖 | 800V DC 機櫃到晶片供電示意：機櫃內 Power Board（2 顆 800-50V、Hot Swap、eFuse、MCU、EMC）經 50VDC 到 IT Board，再經 IBC 與 VRM 到 GPU |
報告_OCP2026_光寶科_800V到晶片供電_20261015_p4.png |
p4 | 真資料圖 | 800-50V DC-DC 10kW full-brick 實物與效率曲線：尺寸 119.4×63.5×14.2mm，1522 W/in3，峰值 98.7%（90A）、滿載 98.1%，標註 2027 年 12kW |
報告_OCP2026_光寶科_800V到晶片供電_20261015_p9.png |
p9 | 真資料圖 | 50-0.8V 單級 VRM 模組實物與效率比較圖：單顆 240A、4 並聯 800A，峰值 91.4%／800A 時 87%，對比 Google 與 Meta 兩級方案 800A 時 80.3%／83.5% |
報告_OCP2026_光寶科_800V到晶片供電_20261015_p10.png |
p10 | 真資料圖 | 800V 供電架構趨勢三張方塊圖：基準為兩個 tray、三級（800→50V IBC 16:1→6/12V→0.65V）；趨勢 1 為單 tray 兩級（DCX 16:1）；趨勢 2 為單級搭配晶片內 IVR（DCX 64:1／128:1／256:1 至 12/6/3.3V） |
報告_OCP2026_光寶科_800V到晶片供電_20261015_p12.png |
p12 | 真資料圖 | 鑽石基板加微通道先進封裝：照片與爆炸圖、熱阻 0.16 與 0.1 °C/W（單面／雙面）、耐壓超過 3kV 的漏電曲線（與劍橋大學合作） |
原始內容
p1
Powering the AI Revolution: Navigating the 800V-to-Chip Frontier Teng Long Professor, LITEON-EPIC University of Cambridge
p2
800V DC Rack-to-Chip Power Delivery 800-50 V 800-50 V Hot Swap MCU EMC IT Board 50 V DC EFuse VRM IBC Power Board GPU
p3
Power Distribution board (PDB) 800-50V Power Distribution board 800-50V DC-DC Power Brick
p4
800-50V DC-DC Power Brick (Full-Brick 10kW) Rating: 10kW full-brick Power density: 1522 W/in3 Function: High Voltage Bus Converter (HVBC 800-50V) Efficiency: peak 98.7%, full-load 98.1% 2027: 12kW 119.4mm 63.5mm 14.2mm Peak 98.7% @ 90 A 96.0% 96.5% 97.0% 97.5% 98.0% 98.5% 99.0% 20 40 60 80 100 120 140 160 180 200 Efficiency (%) Output Current (A)
p5
800-50V DC-DC Power Brick (Half-Brick 6kW) 65 mm 61 mm 14.2mm Rating: 6kW half-brick Power density: 1746 W/in3 Function: High Voltage Bus Converter (HVBC 800-50V) Efficiency: peak 98.2%, full-load 97.8% Peak 98.2% @ 55 A 95.0% 95.5% 96.0% 96.5% 97.0% 97.5% 98.0% 98.5% 10 20 30 40 50 60 70 80 90 100 110 120 Efficiency (%) Output Current (A)
p6
IT Board (50V) 2-Stage On-board Power Solution Power Distribution board (PDB) IT Board Computing Card
p7
First-Stage DC-DC converter for 12V Bus Peak 97.9% @ 500 W 95.0% 95.5% 96.0% 96.5% 97.0% 97.5% 98.0% 98.5% Efficiency (%) Output Power (W) Vin=40V Vin=48V Vin=54V Vin=60V Ta = 55°C 23.2mm 17.5 mm 7.8mm OCP compliance and qualification Mature LLC topology varient, In: 40-60V, Out: 10-15V Rating: 1500W, Size: 23.2x17.5x7.8 mm Power density: 7762 W/in3 Efficiency@54V input: peak 97.9%, full-load 96.9%
p8
First-Stage DC-DC converter for 6V Bus Peak 97.9% @ 300 W 93% 94% 95% 96% 97% 98% 99% Efficiency (%) Output Power (W) Vin=40V Vin=48V Vin=54V Vin=60V Ta = 55°C 23.2mm 17.5 mm 8.8mm OCP compliance and qualification Mature LLC topology variant, In: 40-60V, Out: 5-7.5V Rating: 1000W, Size: 23.2x17.5x8.8 mm Power density: 4587 W/in𝟑 Efficiency@54V input: peak 97.9%, full-load 96.6%
p9
50-0.8V Single-Stage Voltage Regulator Module [1] H. Gan et al., “Vertical Power Delivery for 1000 Amps Machine Learning ASICs,” APEC 2024. [2] S. Zou et al., “Vertical Power Delivery Module Design and Integration for 850A AI ASIC,” APEC 2026. Rating: 240A (single), regulated, 4 in parallel for 800A Current density: 1.28A/mm2 Function: 54-0.8 regulated and adjustable output voltage Efficiency: peak 91.4%, full-load 87% Significant higher efficiency and form factor than 2-stage 17 mm 11 mm 6.5 mm
p10
IT board Power board 800 V DC Power Delivery Architecture Trends Baseline: two-tray, 3 stages from 800V to core IT board 800 V Bus 50 V Bus 6 or 12 V Bus 0.65 V Trend 1: one-tray, two stages from 800V 800 V Bus 50V Bus 0.65V Trend 2: one-tray, single stage using IVR at core IT board 800 V Bus 12/6/3.3V Bus IBC 4:1 8:1 VRM GPU GPU GPU with IVR DC/DC DCX 64:1 128:1 256:1 DC/DC DCX 16:1 DC/DC IBC 16:1 IVR: Integrated Voltage Regulator
p11
AI assisted high frequency planar transformer design Non-autoregressive PIC-DeepONet for transient B–H hysteresis H = baseline + history + dynamic, AI assisted planer transformer winding design: Graph Neural Network for PCB Layer Current Sharing 6.50% core-loss error 2137 parameters
p12
Advanced Packaging (Diamond substrate with Microchannel) Conventional SiN AMB substrate top side bottom side Proposed diamond substrate with various silver metallization patterns Single crystalline PVD diamond Thin Ti (~10–50 nm) is annealed (≈500°C) to form TiC on diamond. Ag by PVD or plating to ~0.5–5 µm for high conductance with low stress. Electrical isolation is demonstrated >3kV limit (curve tracer limit). Thermal Resistance: 0.16 C˚/W (Single side) and 0.1 C˚/W (double side). In collaboration with Cambridge Integration and Cambridge University. 7.5µA leakage current diamond Silver Microchannel
p13
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