擷取方式：Chrome 直接開頁擷取（未用 defuddle）。Nature 全文為付費牆，僅取得公開的摘要、作者與單位、作者貢獻、利益揭露、致謝與完整參考文獻清單；論文正文與圖表未取得。參考文獻為全文照錄後節選（節選標準：與 CPO 架構、玻璃／TGV 中介層、microLED 光互連、業界產品直接相關者），節選段落已標明。
一、Nature Electronics 論文 metadata
- Article type: Review Article
- Title: Co-packaged optics for high-performance computing and artificial intelligence
- Journal: Nature Electronics, volume 9, pages 853–867 (2026)
- DOI: https://doi.org/10.1038/s41928-026-01681-6
- Received: 18 November 2025｜Accepted: 08 July 2026｜Published: 19 August 2026
- Subjects: Electrical and electronic engineering; Electronic devices; Inorganic LEDs; Optoelectronic devices and components
- 擷取當下 Accesses 1471、Altmetric 53
作者與單位（原文照錄）
Byungsoo Kim, Soo Ho Choi, Georgii Zograf, Young Jin Yoo, Yongmin Baek, Seokho Kim, Jongchan Kim, Jeehwan Kim, Sang Hoon Chae, Hyunseok Kim, Seunghoon Hong & Kyusang Lee
- Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA — Byungsoo Kim, Yongmin Baek, Seokho Kim & Kyusang Lee
- School of Electrical and Electronic Engineering, Yonsei University, Seoul — Byungsoo Kim & Jongchan Kim
- Department of Integrated Display Engineering, Yonsei University, Seoul — Byungsoo Kim & Jongchan Kim
- Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign — Soo Ho Choi & Hyunseok Kim
- School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore — Georgii Zograf & Sang Hoon Chae
- School of Materials Science and Engineering, Nanyang Technological University, Singapore — Georgii Zograf & Sang Hoon Chae
- Research Laboratory of Electronics, Massachusetts Institute of Technology — Young Jin Yoo & Jeehwan Kim
- AI Infra Optimization Team, SK hynix Inc., Seoul, Republic of Korea — Seunghoon Hong
- Department of Material Science and Engineering, University of Virginia — Kyusang Lee
Author notes: These authors contributed equally: Byungsoo Kim, Soo Ho Choi, Georgii Zograf, Young Jin Yoo, Yongmin Baek, Seokho Kim.
作者貢獻（原文照錄）
B.K., S. H. Choi, G.Z., Y.J.Y., Y.B. and S.K. contributed equally to this review article. B.K., S. H. Choi, G.Z., Y.J.Y., Y.B. and K.L. wrote the initial draft and researched data for this review article. B.K., Y.B., S.K., Jongchan Kim, Jeehwan Kim, S. H. Chae, H.K., S.H. and K.L. contributed to reviewing and editing before submission.
利益揭露（原文照錄）
Competing interests: S.H. is an employee of SK hynix Inc. The other authors declare no competing interests.
致謝之資金來源（原文照錄要點）
Air Force Office of Scientific Research YIP (FA9550-23-1-0159)；NSF ECCS-2332060、ECCS-2328839、IUCRC EEC-2231625、MRSEC DMR-2309037；National Research Foundation of Korea（RS-2025-24535263、RS-2025-25442127）；LAMP Program（RS-2024-00442483）；Korea Institute for Advancement of Technology, MOTIE（RS-2025-02263458）；MOE AcRF Tier 3（MOE-MOET32023-0003）；A*STAR Singapore AME IRG（M23M6c0109）。
摘要（原文照錄）
The large data movement required in high-performance computing and artificial intelligence workloads has exposed the fundamental limits of electrical interconnects, where resistive losses, capacitive loading and frequency-dependent distortion increasingly constrain bandwidth, latency and energy efficiency. Optical compute interconnects, which replace electrical links with co-packaged photonic channels, could provide low propagation loss, high bandwidth and superior signal integrity. Here, we examine the development of optical chip-to-chip interconnects and co-packaged optics for high-performance computing and artificial intelligence. We analyse the key domains, including electrical subsystems, electro–optical and opto–electronic conversion interfaces, and optical transmission networks, that determine system-level performance across bandwidth, energy and latency metrics. We also provide a technology roadmap from two-dimensional (2D) co-packaged optics, 2.5D interposer-based integration and 3D heterogeneous stacking, identifying critical challenges in thermal management, manufacturability and standardization that will need to be addressed to establish optical compute interconnects as a foundational communication technology for high-performance computing infrastructure.
參考文獻節錄（節選標準：CPO 架構／玻璃與 TGV 中介層／microLED 光互連／業界產品）
microLED 光互連 - Pezeshki, B. et al. 304 channel microLED based CMOS transceiver IC with aggregate 1 Tbps and sub-pJ per bit capability. OFC 2024 Technical Digest, Paper M3A.1 (Optica, 2024). - Benyahya, K. et al. MOSAIC: breaking the optics versus copper trade-off with a wide-and-slow architecture and microLEDs. ACM SIGCOMM 2025, 234–247. - Shin, J. et al. Vertical full-colour micro-LEDs via 2D materials-based layer transfer. Nature 614, 81–87 (2023). - Qi, L. et al. Monolithic full-color active-matrix micro-LED micro-display using InGaN/AlGaInP heterogeneous integration. Light Sci. Appl. 12, 258 (2023).
玻璃／TGV 中介層 - Ge, C. et al. High-speed wafer-level TGV interposer for 2.5D CPO. Opt. Commun. 579, 131517 (2025). - Yeary, L. et al. Co-packaged optics on glass substrates for 102.4 Tb/s data center switches. IEEE ECTC 2023, 224–227. - Zhao, J. et al. Development of high performance 2.5D packaging using glass interposer with through glass vias. J. Mater. Sci. Mater. Electron. 34, 1790 (2023). - Mirshafiei, M. et al. Glass interposer for short reach optical connectivity. Opt. Express 24, 12375 (2016). - Li, X. et al. Die-embedded glass interposer with minimum warpage for 5G/6G applications. IEEE ECTC 2023, 2247–2254. - Yoon, S. et al. Stitching-loss-tolerant silicon nitride waveguides on glass for panel-level optical interconnects. Opt. Lett. 51, 1903 (2026). - Yu, C. et al. Application of through glass via (TGV) technology for sensors manufacturing and packaging. Sensors 24, 171 (2024).
CPO 架構與業界產品 - Lee, B. G. et al. Beyond CPO: a motivation and approach for bringing optics onto the silicon interposer. J. Lightwave Technol. 41, 1152–1162 (2023). - Fathololoumi, S. 4 Tb/s optical compute interconnect chiplet for XPU-to-XPU connectivity. IEEE Hot Chips 36 (2024). - Stojanovic, V. A UCIe optical I/O retimer chiplet for AI scale-up. IEEE Hot Chips 37 (2025). - Winterbottom, P. Photonic interconnect for accelerated computing celestial AI photonic fabric module—the world's first SoC with in-die optical IO. IEEE Hot Chips 37 (2025). - Lightmatter announces Passage L200, the fastest co-packaged optics for AI. Lightmatter press release (31 March 2025). - Daudlin, S. et al. Three-dimensional photonic integration for ultra-low-energy, high-bandwidth interchip data links. Nat. Photon. 19, 502–509 (2025). - Tan, M. et al. Co-packaged optics (CPO): status, challenges, and solutions. Front. Optoelectron. 16, 1 (2023). - Buscaino, B. et al. External vs. integrated light sources for intra-data center co-packaged optical interfaces. J. Lightwave Technol. 39, 1984–1996 (2021). - Coenen, D. et al. Thermal scaling analysis of large hybrid laser arrays for co-packaged optics. IEEE JSTQE 31, 1501009 (2025). - Wu, S. et al. Simulation and experimental investigation of liquid-cooling thermal management for high-bandwidth co-packaged optics. Front. Optoelectron. 18, 11 (2025). - Cao, R. et al. Thermomechanical and compression analyses for large-scale co-packaged optics (CPO) assembly. IEEE TCPMT 14, 2079–2087 (2024). - Liang, D. et al. An energy-efficient and bandwidth-scalable DWDM heterogeneous silicon photonics integration platform. IEEE JSTQE 28, 6100819 (2022). - Gholami, A. et al. AI and memory wall. IEEE Micro 44, 33–39 (2024).
二、SK hynix 官方新聞稿（2026-08-20，原文要點照錄）
標題：SK hynix's technology roadmap for co-packaged optics features in 'Nature Electronics,' as AI competition shifts from chips to systems
新聞稿揭露、但不在論文摘要中的三個目標值（原文）
Based on this architecture, the researchers define clear technical targets for next-generation AI infrastructure, including more than 100 Tb/s of bandwidth per node, energy consumption below 1 pJ/bit, and chip-to-chip latency of less than 10 nanoseconds.
bandwidth wall 論述（原文要點）
compute throughput has tripled every two years, while interconnect bandwidth has only advanced 1.4-fold over the same period
光學中心架構（原文要點）
In the long term, the evolution of CPO is expected to extend optical interconnects all the way to the memory interface. Moving beyond the physical constraints of conventional packaging, the proposed optics-centric architecture uses a photonic interposer to directly connect memory and processors, maximizing the efficiency of data movement across the system. With this architecture, multiple AI accelerators can share a large memory pool.
Kyusang Lee 訪談原文（節錄）
Extending optical interconnects to the memory interface would overcome the physical constraints surrounding compute chips, removing limitations on both memory capacity and the number of electrical connections. It would also allow multiple AI accelerators to share a large memory pool.
The technology has already moved beyond the laboratory and entered the early stages of commercialization. Significant challenges remain, from integrating low-power photonic devices to developing coherence protocols and improving system reliability.
We will continue working with industry partners to demonstrate pathways toward even greater energy efficiency through technologies such as ultrathin photonic material integration and massively parallel optical interconnects based on microLED (µLED) technology.
Seunghoon Hong 訪談原文（節錄）
CPO integrates optical transceivers (TRx) into the same package as the processor, enabling chips to exchange data using light instead of long electrical interconnects.
Memory companies are evolving beyond the role of supplying individual components to becoming partners that help strengthen the competitiveness of customers' entire systems through technologies such as CPO.
三、擷取者註記（非原文）
- 新聞稿與論文均未提供任何量產時程、客戶或產品計畫。
- 新聞稿標題稱「SK hynix's technology roadmap」，但論文作者結構顯示初稿由 UVA 等學術單位撰寫、SK hynix 僅 1 位作者且僅參與投稿前審閱編輯；致謝之資金來源亦無 SK hynix。引用時應區分「企業承諾」與「學術綜述」。
- 另有一則以 agy 搜尋取得的 BusinessKorea 連結（idxno=248386）經開頁驗證為無關報導（新韓銀行動畫新聞），已捨棄不採用。