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報告_Citi_台積電2330_20260513

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報告_Citi_台積電2330_20260513

PDF 原檔：報告_Citi_台積電2330_20260513_original.pdf

原始內容

(RIC: 2330.1W, BB: 2330 11)

TWD

2,250

2,000

1,750

1,500

1,250

1,000

750

13 May 2026 09:17:01 ET │ 21 pages

Jun

Sep

Dec

Mar

TSMC (2330.TW)

Competitive Landscape Holding Steady

CITI’S TAKE

We note that there is rising concern on long term competition for TSMC as its customers are considering other alternatives in foundry and advanced packaging. While Intel’s EMIB-T presents an alternative packaging strategy, the technology is dependent on the readiness of the ABF substrate ecosystem, a critical factor for next-generation AI scaling. TSMC’s predictable yields, cycle times, and cost control at high volumes provide a significant advantage, giving it an edge over competitors. In this note, we provide more detailed comparison from advanced node and design rule differences between EMIB-T and CoWoS.

TSMC’s Advanced Node and Packaging Strategy -During TSMC ’ s latest technology symposium, TSMC elaborated on its N2 platform, including N2P and N2X, and the AI-focused A16 node with Super Power Rail, underscoring a shift towards system-level scaling over pure transistor shrink. Separately, advanced packaging, through CoWoS, SoIC, and SoW, is central to AI compute scaling, with expanded roadmaps enabling larger, more integrated AI systems. The chip reticle cycle is moving from current 5.5-reticle CoWoS toward 9.5-reticle and eventually beyond 14-reticle package integration by 2028-2029. We estimate CoWoS capacity could continue growing at nearly 85% YoY and 60% YoY into 2026/2027 on continued strong hyperscaler AI demand, and SoIC will see substantial increase in 2027/2028 with CoPoS to follow in 2029/2030. We believe TSMC’s comprehensive AI manufacturing ecosystem provides a significant competitive advantage.

Competitive Landscape and Intel’s EMIB-T -We see no significant change in TSMC’s competitive landscape. Major AI and HPC companies have long-term foundry platform decisions locked in. Intel’s EMIB-T packaging ecosystem presents a different approach to heterogeneous integration compared to TSMC’s CoWoS-L, with the former having a greater reliance on advanced ABF substrate technology. While we believe AI chipmakers may try to diversify their sources and explore Intel’s EMIB-T technology, the compute logic of an AI die may remain identical, and the packaging interface often cannot use the same design.

ABF technology readiness is critical for EMIB-T Adoption -Given EMIB-T ’ s design methodology, the readiness of the ABF substrate ecosystem for ultra-high-density routing, precise bridge embedding, and advanced power delivery is critical for EMIBT adoption. We believe the capacity and technology readiness will be key checkpoint for EMIB-T penetration in the next 2-3 years.

Earnings Summary

Year to 31DecNet Profit (NT$M)DilutedEPS (NT$)EPSgrowth (%)P/E (x)P/B (x)ROE (%)Yield (%)
2024A1,173,26845.2439.949.113.430.30.6
2025A1,717,88366.2446.433.510.635.40.8
2026E2,563,45698.8549.222.57.940.41.2
2027E3,410,850131.5233.116.9640.62
2028E4,263,281164.392513.54.638.92.5

Source: Powered by dataCentral

See Appendix A-1 for Analyst Certification, Important Disclosures and Research Analyst Affiliations.

n Buy

Short-Term View: Upside, expires 26-JUN-26

Price (13 May 26 13:30)

NT$2,220.00

Target price

NT$2,875.00

Expected share price

return

29.5%

Expected dividend yield

1.2%

Expected total return

30.7%

Market Cap

NT1,826,002M

Price Performance (RIC: 2330.TW, BB: 2330 TT)

Laura (Chia Yi) Chen AC

+886-2-8726-9090

laura.cy.chen@citi.com

Jack Chen +886-2-8726-9091 jack1.chen@citi.com

Nicholas Lai +886-2-8726-9093 nicholas.lai@citi.com

Citi Research

See Appendix A-1 for Analyst Certification, Important Disclosures and Research Analyst Affiliations.

2330.TW: Fiscalyearend31-Dec2330.TW: Fiscalyearend31-Dec2330.TW: Fiscalyearend31-Dec2330.TW: Fiscalyearend31-Dec2330.TW: Fiscalyearend31-DecPrice:NT$2,220.00; TP:NT$2,875.00;Market Cap:NT$57,570,203m;Recomm:Buy
Profit&Loss(NT$m)202420252026E2027E2028EValuation ratios202420252026E2027E2028E
Sales revenue2,894,3083,809,0545,253,4527,071,3498,762,189PE(x)49.133.522.516.913.5
Cost of sales-1,269,954-1,527,760-1,811,170-2,505,095-3,075,722PB(x)13.410.67.96.04.6
Gross profit1,624,3542,281,2943,442,2824,566,2545,686,467EV/EBITDA(x)28.421.314.010.58.3
Gross Margin (%)56.159.965.564.664.9FCFyield (%)1.62.02.34.25.7
EBITDA(Adj)1,984,8502,624,1883,931,2705,150,2146,401,563Dividend yield (%)0.60.81.22.02.5
EBITDAMargin(Adj) (%)68.668.974.872.873.1Payout ratio (%)3127283333
Depreciation-662,797-688,096-946,363-1,203,501-1,483,358ROE(%)30.335.440.440.638.9
Amortisation00000Cashflow(NT$m)202420252026E2027E2028E
EBIT (Adj)1,322,0531,936,0922,984,9073,946,7134,918,205EBITDA1,984,8502,624,1883,931,2705,150,2146,401,563
EBIT Margin (Adj) (%)45.750.856.855.856.1Working capital68,25727,877-455,087-30,215-60,205
Net interest67,78186,20699,885160,216215,053Other-147,949-215,723-421,452-535,863-654,923
Associates8282,5462,0002,0002,000Operating cashflow1,905,1572,436,3423,054,7324,584,1365,686,435
Non-Op/Except/Other Adj15,17616,81925,16635,35743,811Capex-956,007-1,272,411-1,725,763-2,150,000-2,400,000
Pre-tax profit1,405,8392,041,6633,111,9594,144,2855,179,068Net acq/disposals74,369122,881140,20688,926-330,102
Tax-233,407-326,266-549,476-735,652-918,557Other00000
Extraord./Min.Int./Pref.div.8362,4869732,2172,770Investing cashflow-881,638-1,149,530-1,585,557-2,061,074-2,730,102
Reported net profit1,173,2681,717,8832,563,4563,410,8504,263,281Dividends paid-363,055-466,779-716,556-1,127,769-1,417,854
Net Margin (%)40.545.148.848.248.7Financing cashflow-313,242-590,737-668,609-1,083,140-1,355,192
CoreNPAT1,173,2681,717,8832,563,4563,410,8504,263,281Net change in cash627,147615,273709,6371,348,9931,510,211
Per share data202420252026E2027E2028EFree cashflow to s/holders949,1511,163,9311,328,9692,434,1363,286,435
Reported EPS($)45.2466.2498.85131.52164.39
Core EPS($)45.2466.2498.85131.52164.39Revbreakdownbynode202420252026E2027E2028E
DPS($)14.0018.0027.6343.4954.67FinSumm-TimeSeriesdataitem3nanananana
CFPS($)73.4693.95117.79176.77219.272nm(%)001429na
FCFPS($)36.6044.8851.2593.86126.733nm(%)20252930na
BVPS($)165.37208.98280.20368.24477.965nm(%)33372823na
Wtdavgordshares(m)25,93425,93325,93325,93325,93310/7nm(%)1815139na
Wtdavgdiluted shares (m)25,93425,93325,93325,93325,93316/20nm(%)8753na
Growthrates202420252026E2027E2028E21nmto32nm(%)8753na
Sales revenue (%)33.931.637.934.623.933nmto45nm(%)3221na
EBIT (Adj) (%)43.546.454.232.224.646nmto65nm(%)3221na
CoreNPAT(%)39.946.449.233.125.066nmto90nm(%)1110na
CoreEPS(%)39.946.449.233.125.00.10u to 0.13u (%)1100na
BalanceSheet(NT$m)202420252026E2027E2028E
Cash&cashequiv.2,127,6272,767,8563,370,2884,567,2935,868,991Revbrkdnbygeography202420252026E2027E2028E
Accounts receivables272,088281,791582,266691,824879,972N. America (%)70nananana
Inventory287,869288,109428,376507,275643,042Asia-Pacific (%)10nananana
Net fixed &other tangibles3,235,7713,691,8414,524,1955,618,4697,157,885China (%)11nananana
Goodwill &intangibles00000EMEA(%)3nananana
Financial &other assets769,374903,4261,126,0061,261,3321,490,863Japan (%)5nananana
Total assets6,692,7297,933,02410,031,13212,646,19316,040,753
Accounts payable74,22784,330113,188137,050169,985
Short-term debt59,858136,926182,927223,123280,244
Long-term debt958,429896,062896,062896,062896,062
Provisions &other liab1,275,8491,354,9111,530,2871,795,9932,252,299
Total liabilities2,368,3622,472,2292,722,4643,052,2283,598,590
Shareholders’ equity4,288,5455,419,5967,266,4969,549,57612,395,003
Minority interests35,03141,19942,17244,38947,159
Total equity4,323,5765,460,795 -1,734,8697,308,668 -2,291,2999,593,965 -3,448,10812,442,162 -4,692,685
Net debt (Adj)-1,109,340
Net debt to equity (Adj) (%)-25.7-31.8-31.4-35.9-37.7

Figure 1. loMe - Advanced node technology roadmap

High-End

(Premium Mobile,

Data Center Server.|

Al Accelerator.

Gaming, Networking,

ADAS)

Mainstream

(Mid-to-Low-End

Mobile, Consumer.

Base Station)

@ 2026 Citigroun Inc. No redistribution without Citicroun’s written nermission.

NSP

N7A

N6

N4

N3

N4P/N4X

N3E

NSA

N4P

N2

N3P/N3X

N4C

N2P

N3A

N3C

N2X

A16

A14

N2U

N2U

A1S

A12

Figure <. loMe - Advanced node pertormance comparison

N2P PPA (vS. N3E)

Power Reduction at Same Speed

Logic Density

-36%

-1.2X

TSMC A16TM PPA*

Speed Improvement

Power Reduction at Same Vdd

8-10%

Speed Improvement at Same Power

~18%

Technology

A16

(Ref: N2P)

at Same Speed

15~20%

>= 1.15X

Chip Density

1.07-1.10X

Leading position in the most advanced node and packaging remains intact Chip Density

At the latest TSMC Technology Symposium, the company made it amply clear that its future competitiveness is no longer based purely on transistor shrink, but on building a long-duration process ecosystem spanning multiple optimized node variants. The most important message was that N2 is becoming an entire platform family rather than a one-time technology transition. TSMC reiterated that N2 entered risk production trajectory successfully for second-half of 2025, followed by N2P in 2H26 and N2X afterward for higher-performance HPC applications. More importantly, TSMC emphasized A16 as the key AI/HPC-oriented node that introduces its backside power delivery architecture called Super Power Rail (SPR).

TSMC highlighted direct backside contact architecture to reduce IR drop and improve routing efficiency. From an industry perspective, this is strategically critical because AI accelerators are increasingly constrained by power delivery and routing congestion rather than transistor density alone. TSMC claims A16 can deliver roughly 8-10% performance improvement or 15-20% lower power versus N2P, alongside modest density gains. It is also worth noting that TSMC stated that it does not urgently require High-NA EUV through at least 2029, reflecting confidence in its existing EUV optimization capability and cost structure advantage versus competitors aggressively pursuing High-NA insertion.

Figure 1. TSMC - Advanced node technology roadmap

Figure 2. TSMC - Advanced node performance comparison

© 2026 Citigroup Inc. No redistribution without Citigroup’s written permission.

Source: Citi Research, TSMC

© 2026 Citigroup Inc. No redistribution without Citigroup’s written permission.

Source: Citi Research, TSMC

Advanced Packaging has been the Core of AI Scaling Strategy

In the symposium, TSMC also reinforced that advanced packaging is now central to AI compute scaling. It presented an expanded roadmap for CoWoS, SoIC, and System-on-Wafer (SoW) technologies under its 3DFabric strategy with bigger reticle cycle from current 5.5-reticle CoWoS configurations toward 9.5-reticle and eventually beyond 14-reticle package integration by 2028-2029. This is extremely significant because it enables far larger AI systems to integrate more compute dies and HBM stacks into single packages. TSMC also highlighted SoWX, a future wafer-scale integration platform potentially capable of integrating up to 64 HBM stacks and delivering compute capability approaching an entire server rack within a single integrated system. It shows that the industry is now entering

igure 3. TSMC - Advanced packaging technology roadmap and will be in production in 2029

Interposer Size

3.3-reticle

8хHBM3

2024

2023

2025

5.5-reticle

12xHBM3E/4

2026

9.5-reticle

12х HBM4E

2027

2026 Citiornun Ine No redistrihution without Citioroun’s written nermission.

14-reticle an era where package size, memory integration, optical connectivity, and power delivery architecture determine AI system competitiveness more than transistor shrink alone.

Once again, the important strategic takeaway from the symposium was that TSMC is shifting the industry narrative away from traditional node naming competition toward full-system scaling capability . Instead of focusing purely on whether A16 competes with Intel 18A or Samsung SF2, TSMC is emphasizing total AI infrastructure optimization across compute, memory bandwidth, interconnect, optics, packaging, and power efficiency. We estimate CoWoS capacity could continue growing at nearly 85% YoY and 60% YoY into 2026/2027 on continued strong hyperscaler AI demand, and SoIC will see substantial increase in 2027/2028 with CoPoS to follow in 2029/2030.

Figure 3. TSMC - Advanced packaging technology roadmap

© 2026 Citigroup Inc. No redistribution without Citigroup’s written permission.

Source: Citi Research, TSMC

It is also worth noting that TSMC’s roadmap increasingly separates client/mobile optimization from HPC/AI optimization. Nodes such as A16 and future A12 are clearly positioned for high-power AI systems requiring backside power delivery and extreme routing density, while variants such as A13 appear more cost and area optimized. This indicates that smartphone scaling and AI datacenter scaling are diverging technologically. This is also the key that TSMC’s greatest competitive advantage is not transistor leadership alone but its advanced-node ecosystem, advanced packaging infrastructure, and AI supply-chain integration capability. Competitors may narrow transistor gaps, but replicating TSMC’s entire AI manufacturing ecosystem will likely be much more difficult over the next few years.

Competitive landscape not changing much

While we see the positives about Intel’s (covered by Atif; latest report: Intel Corp (INTC.O) - AI CPU Cycle + Terafab Foundry Opportunity = U/G to Buy) progress in 18A and rising expectation on 14A as Intel has already tied 18A to commercial products including Intel Panther Lake for notebooks and Intel Clearwater Forest for servers, key customers of TSMC such as Apple, NVIDIA and Broadcom, and others may evaluate Intel 18A/14A. This may need to be monitored closely in our view, but evaluation tape-outs are standard industry practice and do not imply big volume mass production. As a result, we don’t see competitive landscape changing much for TSMC as of now. In our view, the key debate is no longer just about transistor

>40-reticle

64xHBM

performance, but manufacturing stability and economic scalability. Other than technology leadership, TSMC’s advantage has always been on predictable yields, cycle times, defect density control, and acceptable wafer costs at high volume . Fabless companies require foundries that can perform reliably over years.

More importantly, major AI and HPC companies have already locked in their 2026/2027, or even 2028, platform decisions years ago, particularly around packaging ecosystems, IP portability, software compatibility, and supply-chain predictability. As a result, Intel’s initial foundry opportunity is more likely to come from strategic diversification programs, US-government-aligned projects, networking ASICs, or second-source manufacturing strategies rather than displacement of TSMC.

Intel EMIB-T vs TSMC CoWoS-L; Different Philosophy of Advanced Integration

As AI accelerator complexity continues to rise, hyperscalers and leading ASIC vendors are beginning to explore whether the same AI chip architecture could be deployed using either TSMC’s CoWoS-L platform or another alternative, such as Intel’s EMIB-T packaging ecosystem. The motivation is largely strategic: reducing dependency on a single packaging supply chain, mitigating CoWoS capacity constraints, improving negotiating leverage, and diversifying manufacturing risk.

It is becoming increasingly important that advanced packaging evolves from a backend assembly process into a critical system-level performance differentiator. Also worthy to note AI packaging architecture directly impacts bandwidth density, power efficiency, thermal behavior, scalability, and ultimately total system cost, and Intel EMIB-T and TSMC CoWoS-L basically represent two fundamentally different approaches to heterogeneous integration.

CoWoS-L extends TSMC’s CoWoS family by combining local silicon interconnect structures with RDL-based large-area routing , allowing very high bandwidth connectivity across large package footprints. Much of the fine-pitch routing burden is absorbed by silicon interposer-like structures and redistribution layers. This architecture is particularly well suited for large AI accelerators with multiple HBM stacks, where extremely wide memory interfaces and dense chip-to-chip interconnects are required.

By contrast, Intel EMIB-T relies on localized embedded silicon bridges rather than a full-size silicon interposer. The high-density interconnect is concentrated only where necessary, while a much larger portion of package-level routing responsibility is pushed into the ABF substrate itself . This significantly changes the substrate complexity, as the package substrate must now handle more power distribution, signal breakout, high-speed routing, via structures, and embedded trace management.

As a result, EMIB-T generally imposes greater demands on substrate technology, including:

  • n ultra-fine line/space routing

  • n advanced laser via structures

  • n higher layer counts

  • n tighter warpage control

  • n lower-loss ABF materials

  • n and more sophisticated embedded routing architectures

Intel remains heavily dependent on advanced substrate vendors such as Ibiden, Shinko, and Unimicron for its next-generation AI packaging roadmap. And substrate makers’ capacity and technology progress will be key checking points whether EMIB-T is ready to pick up in big scale in next one year or two.

Dual Packaging challenge

We see a growing possibility that AI chipmakers may try to diversify their sources and try Intel’s EMIB-T technology, and while the compute logic of an AI die may remain identical, the packaging interface often cannot use the same CoWoS design.

The first challenge lies in bump architecture and pad layout . A die originally optimized for CoWoS-L may place its HBM PHYs, die-edge interfaces, micro bump arrays, and power pads according to the routing assumptions of TSMC’s silicon interconnect architecture. EMIB-T, however, may require different bridge landing zones, alternative bump pitch optimization, and distinct signal escape topologies.

Another key consideration would be power delivery integrity . As AI accelerators move toward multi-kilowatt rack-scale systems, package-level power distribution becomes a limiting factor. CoWoS-L and EMIB-T distribute current differently across the package hierarchy. EMIB-T often places heavier reliance on substrateside power routing, while CoWoS-L can leverage larger silicon routing regions to assist in power and signal balancing.

In addition, the signal integrity and HBM routing become increasingly difficult at higher bandwidth generations. HBM4 and future memory architecture require massive parallel interfaces operating at extremely high speeds. CoWoS-L’s largearea routing capability may offer advantages in scaling memory connectivity, while EMIB-T must carefully optimize bridge placement and substrate escape routing to achieve similar bandwidth efficiency.

Given the different design rules, we expect the ecosystem support across validation and reliability complexity rise dramatically when supporting two packaging ecosystems simultaneously. And we believe Mediatek’s TPU progress at EMIB-T will be an important indicator to watch out.

ABF Substrate technology readiness is key for EMIB-T takeoff

Compared to TSMC’s CoWoS approach, Intel’s EMIB-T may place even greater importance on substrate engineering because more routing and system integration responsibility shifts from the silicon interposer toward the package substrate itself. The ABF substrate is responsible not only for structural support, but also for ultrahigh-density redistribution routing, power delivery integrity, signal integrity management, thermal stability, and integration of embedded bridge structures. It must accommodate extremely fine-line routing, precise bridge embedding, ultralow-loss high-speed signaling, and increasingly complex power distribution networks supporting AI accelerators consuming well above 1,000W package-level

Figure 4. Comparison of Intel’s EMIB-T and 15MC’s Cowos/sole

Intel EMIB-T

Modular bridge-based architecture using embedded silicon bridges within

substrate

Reduce cost and improve scalability of very large Al packages while

TSMC CoWoS / SolC

Large silicon interposer-centric architecture with highly integrated

routing

Maximize routing density and power. This significantly raises substrate complexity compared with traditional server CPUs. Full or partial silicon interposer

Lower bridge design

Suppliers capable of advanced ABF substrate manufacturing, fine-line build-up films, precision drilling, embedded bridge integration, and low-warpage control therefore become strategically important in the EMIB-T supply chain. In practice, this means substrate technology is no longer a secondary consideration; it is becoming one of the primary enablers determining whether next-generation AI racks can scale bandwidth, power, and thermal performance economically. In our view, the ABF substrate ecosystem’s readiness for EMIB-T is also an important check point for EMIB-T’s penetration in next 2-3 years.

Philosophy

Main Objective

Interconnect Method

Packaging Scalability

Dependence on Large Silicon

Interposer

Reticle Limit Exposure

Figure 4. Comparison of Intel’s EMIB-T and TSMC’s CoWoS/SoIC

Al Customer Adoption

Thermal Challenges

Cost Structure Potential

Key Competitive Advantage

Key Commercial Risk

@ 2026 Citiornun Ine No redistribution without Citioroun’s written nermission production learning

Limited but strategically importantDominant in Al GPU and ASIC
ecosystem Complex due to modular bridge distribution and high package powerComplex due to very large integrated package footprint Higher silicon interposer cost but highly
Potentially lower at very large package sizes Advanced modular chiplet flexibilityoptimized production flow Proven manufacturing scale, reliability,
with strong packaging integration Ecosystem readiness and productionand ecosystem trust Capacity constraints and rising
consistencymanufacturing complexity

© 2026 Citigroup Inc. No redistribution without Citigroup’s written permission. Source: Citi Research

Figure o. IsMe - Forward F/E band

NT$

2500

2000

1500

1000 -

500 -

0 +

  • TSMC

  • 11.4x

  • 13.3x -

— 15.2x

17.1x

C 2026 Citioroun Inc. No redistribution without Citigroun’s written nermission.

Figure 1. 15MC - Forward P/D band & KUE

NT$

2500

2000

1500

1000

Reiterate Buy with TP NT$2,875

500

We remain positive over TSMC’s growth outlook as we are looking for a strong +30% sales CAGR in the next three years, supported by secular AI demand growth and its technology leadership in advanced node and packaging. We reiterate Buy and our target price for TSMC is at NT$2,875 based on 25x the average of our 2026-27E EPS, slightly higher than its 3-year average, which we believe is justified by TSMC’s leading and robust AI demand growth outlook. Our target price equates to 2026E/27E P/E of 29x/22x and 2026E/27E P/B of 10x/8x.

Figure 5. TSMC - Citi Estimates vs Consensus

2026E2026E2026E2027E2027E2027E2028E2028E2028E
(NT$mn)CitiCons.Diff.CitiCons.Diff.CitiCons.Diff.
Sales5,253,4525,191,1101.2%7,071,3496,558,1337.8%8,762,1897,898,79710.9%
Gross profit3,442,2823,406,8741.0%4,566,2544,261,6727.1%5,686,4675,067,63112.2%
Operating profit2,984,9072,972,0410.4%3,946,7133,718,8296.1%4,918,2054,383,23412.2%
Net income2,563,4562,542,2900.8%3,410,8503,177,8327.3%4,263,2813,824,66011.5%
EPS(NT$)98.8597.970.9%131.52122.627.3%164.39146.8312.0%
Gross margin65.5%65.6%-0.1 ppt64.6%65.0%-0.4 ppt64.9%64.2%+0.7 ppt
Operating margin56.8%57.3%-0.4 ppt55.8%56.7%-0.9 ppt56.1%55.5%+0.6 ppt
Net margin48.8%49.0%-0.2 ppt48.2%48.5%-0.2 ppt48.7%48.4%+0.2 ppt

© 2026 Citigroup Inc. No redistribution without Citigroup’s written permission.

Source: Citi Research, Bloomberg

Figure 6. TSMC - Forward P/E band

© 2026 Citigroup Inc. No redistribution without Citigroup’s written permission.

Source: Citi Research, company data

ROE

45%

35%

30%

25%

© 2026 Citigroup Inc. No redistribution without Citigroup’s written permission.

Source: Citi Research, company data

Figure s. 15MC - Forecast Summary

2025

2Q

933.8

-386.4

-84.5

547.4

-23.2

-61.3

Unit: NT$bn

Revenue

COGS

Gross Profit

Operating Expense

SG&A expenses

R&D expenses

EBIT

-345.9

-85.2

493.4

-28.6

-56.5

4Q

1,046.1

-394.1

652.0

-88.2

-23.3

-64.9

407.1

463.4

3Q

989.9

-401.4

588.5

-24.0

-87.8

-63.7

500.7

564.9

Figure 8. TSMC - Forecast Summary

Pre Tax Profit

493.0

430.9

Tax Expense/(Credit)

Net Profit

EPS (NT$)

Margins (%)

Gross Margin

Operating Margin

Net Margin

Sequential Growth (%)

Revenue

Gross Profit

EBIT

Net Profit

EPS

© 2026 Citigroun Inc. No redistribution without Citigroun’s written permission.

2025

3,809.1

-1,527.8

2,281.3

-345.2

-99.2

-246.4

1,936.1

86.2

19.4

2,041.7

2026E

5,253.5

-1,811.2

3,442.3

-457.4

-135.7

-323.4

2,984.9

99.9

27.2

3,112.0

2027E

7,071.3

-2,505.1

4,566.3

-619.5

-182.6

-436.9

3,946.7

160.2

37.4

4,144.3

-3,075.7

5,686.5

-768.3

-226.4

-541.8

4,918.2

215.1

45.8

5,179.1

4QE

1,518.0

-539.6

978.5

-129.0

-38.0

-91.1

849.4

27.9

8.1

885.4

1QE

1,681.4

-587.5

1,093.8

-139.8

-38.9

-100.9

954.0

34.5

8.9

997.5

2027

2QE

1,768.2

-623.0

1,145.2

-155.6

-49.5

-106.1

989.6

9.3

3QE

1,818.1

-639.0

1,179.0

-161.8

-49.1

-112.7

1,017.2

41.6

9.6

1,068.4

4QE

1,803.7

-655.6

1,148.1

-162.3

-45.1

-117.2

985.8

45.6

9.5

1,040.9

1Q

1,134.1

-382.8

751.3

-94.0

-26.2

-67.8

659.0

23.8

5.1

687.8

2026

2QE

1,239.6

-412.0

827.6

  • 111.6

-34.7

-76.9

716.0

22.9

6.7

745.7

3QE

1,361.7

-476.7

884.9

-124.4

-36.8

-87.7

760.5

25.3

7.3

793.0

70.2 95.586.9 115.0 149.186.9 115.0 149.186.9 115.0 149.186.9 115.0 149.1150.5 169.6150.5 169.6150.5 169.6150.5 169.6181.6 177.0 -326.3 -549.5 -735.7181.6 177.0 -326.3 -549.5 -735.7181.6 177.0 -326.3 -549.5 -735.7181.6 177.0 -326.3 -549.5 -735.7
361.673.6 452.3505.7572.5596.9134.8 658.7735.4828.4830.5887.4864.51,717.92,563.53,410.8-918.6 4,263.3
13.94398.3 15.36 17.4419.5022.0823.0225.4028.3631.9532.0234.2233.3466.2498.85131.52164.39
58.6 59.562.366.266.865.064.565.164.864.963.759.965.564.664.9
58.8 48.550.654.058.157.855.856.056.756.056.054.750.856.855.856.1
43.149.6 42.7 45.748.350.548.248.448.449.347.048.847.945.148.848.248.7
-311 69 10111153-132383524
-411 8111510111253 -340513325
-414 813179121243 -346543225
-410 14121310 12137-346493325
-410 141213410 12137-346493325

© 2026 Citigroup Inc. No redistribution without Citigroup’s written permission.

Source: Citi Research, company data

525.4

592.4

TSMC

Company description

TSMC is the founder and leader of the dedicated IC foundry segment. The company has built its reputation by offering advanced and “more-thanMoore” wafer production processes and unparalleled manufacturing efficiency. From its inception in 1987, TSMC has consistently offered the foundry segment’s leading technologies and TSMC-compatible design services.

Investment strategy

We rate TSMC shares as Buy. We expect TSMC to deliver sales growth of >30% in recent years thanks to strong growth from HPC/AI as well as stable demand growth from smartphone, IoT, and automotive on tech migration and a shortened replacment cycle. CPU outsourcing to TSMC offers further growth upside potential. A rising cash dividend should also support the share price. While TSMC has been increasing capex meaningfully since 2009, its cost structure is maintained through continuous product mix improvements, efficiency enhancements, and cost reductions.

Valuation

Our target price for TSMC shares of NT$2,875 is based on 25x the average of our 2026-27E EPS, higher than its three-year average forward PER, versus global peers’ average of 15-23x. We believe our PER target is justified by TSMC’s leading position in advanced process node and robust AI demand growth outlook. Given its continuing leadership in the semiconductor foundry industry, we believe TSMC’s stable order visibility and earnings outlook make it less vulnerable than peers to a potential global economic downturn. Our target price equates to 2026E/27E P/E of 29x/22x and 2026E/27E P/B of 10x/8x.

Risks

Key downside risks that could impede the shares from achieving our target price include: 1) weakness in the global semiconductor market; 2) largerthan-expected margin contractions due to depreciation cost hikes and strong NTD; 3) competitors entering the foundry business; 4) longer-than-expected digestion of inventory in the supply chain; and 5) a slowdown in demand either from a global economic downturn or a global trade disruption triggered by tariffs.

Intel Corp

(INTC.O; US$120.61; 1; 12 May 26; 16:00)

Company description

Intel is a semiconductor company that specializes in microprocessors and is the #1 supplier of microprocessors for desktop PCs, notebook PCs, and

servers with approximately 60% total market share. Intel also has a foundry business. Based in Santa Clara, CA, Intel has roughly 83,200 employees worldwide. Intel derives approximately 90% of its total revenue and 90% of total profits from the PC and Datacenter segments. Intel is a vertically integrated device manufacturer (IDM) with front-end wafer fabrication facilities in Oregon, Arizona, New Mexico, China, Ireland, and Israel and backend assembly and test operations in Malaysia, China, Costa Rica, and Vietnam.

Investment strategy

We are Buy rated on Intel shares given the AI-driven CPU cycle and we’re more positive on Intel foundry given better execution by Intel managment.

Valuation

We value INTC based on our SOTP valuation, our price target is $95. We apply a SOTP valuation framework to each of Intel’s reportable segments and to highlight our growth expectations for Intel Foundry.

Risks

PC end-market: Intel derives roughly 90% of sales from the PC and server segments, which are highly dependent on IT spending. Therefore, any major uptick/downtick in IT spending could result in upside/downside to our estimates and cause us to reassess our rating on INTC.

M&A: If Intel engages in a substantial accretive acquisition, it could result in upside to our estimates.

Competition: Intel competes directly with AMD in the microprocessor market. Consequently, any fluctuations in market share between Intel and AMD could result in risk to our estimates.

Customer risk: Intel’s largest PC OEM customers collectively represent roughly 45% Intel’s revenue. As a result, any major declines in orders from PC OEMs could have a negative effect on our estimates for Intel.

Macroeconomic: Intel’s geographic exposure spans multiple geographies including the U.S., Europe, and Asia. As a result, any prolonged macroeconomic downturn/upturn could result in downside/upside to our estimates and rating.

If the impact from the above risks turns out to be greater/less than we anticipate, the shares could fail to achieve or could exceed our target price.

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Appendix A-1

關係圖譜

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