PDF 原檔：報告_OCP2026_Google_NVIDIA_SST整合LVDC_20261015_original.pdf
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### p<n>為頁碼；圖表內容見原檔。
圖片清單（已驗證 2026-10-19）
| 檔名 | 頁 | 分類 | 親眼所見內容 |
|---|---|---|---|
報告_OCP2026_Google_NVIDIA_SST整合LVDC_20261015_p3.png |
p3 | 真資料圖 | 次世代 LVDC 架構：Google 由 Mt. Diablo sidecar（±400Vdc）出發，演進到設施級提案 1「Pathfinding」（13.8 kVac→SST→800 Vdc，SST 效率 98%）與提案 2「High Density」（34.5 kVac→SST→約 ±750 Vdc，目標效率 98.5%），均含 BESS 經 LVDC/LVDC 接入 |
報告_OCP2026_Google_NVIDIA_SST整合LVDC_20261015_p5.png |
p5 | 真資料圖 | SST 規格 Rev 0.3 低壓穿越（LVRT）要求：左為 ERCOT、FINGRID、ITIC、IEEE1547/2800 電網穿越曲線疊圖，右為 SST 需滿足的連續區 0.90–1.20 pu、強制恢復區 0.70–0.90 pu 與相位跳變 25°、V/Hz 等條件 |
報告_OCP2026_Google_NVIDIA_SST整合LVDC_20261015_p6.png |
p6 | 真資料圖 | SST 規格 Rev 0.3 兩種 LVDC 架構單線圖：分散式備援架構與 Catcher 備援架構，下方說明儲能支援交流側（LVRT、斜率）與負載側（備援、機器學習負載波動緩解） |
報告_OCP2026_Google_NVIDIA_SST整合LVDC_20261015_p7.png |
p7 | 文字卡 | SST 規格 Rev 0.3 對齊項目：800 Vdc 單極輸出、電壓容差 ±0.5% 紋波／±1% 靜態／±3% 動態（TBD）、過載 120% 5 秒、效率 ≥98%、爬升率 20–50 MW/min、DC 側不接地或 HRG、外型 10–20 呎×8 呎×8.5 呎 |
原始內容
p1
Satarupa Bal Senior Power Electronics Engineer, Google Ashish Upreti Staff Power System Engineer, Google Mike Tu Principal Electrical Engineer, NVIDIA Integrating Solid State Transformer (SST) to Data Center LVDC Ecosystem AI OPEN DATA CENTER: Power Distribution
p2
Agenda 01 Why Solid State Transformer (SST) for LVDC 02 LVDC Architecture Options 03 Alignment on Specification 04 Specification Flexibility 05 Next Steps 06 Call for Action
p3
Next Generation LVDC Architecture * * Snapshot from “Low-Voltage Direct Current Distribution with Solid State Transformer”, presented by Jing Wang, Krishnanjan Ravikumar, Google, in OCP Summit 2025
p4
Centralized Power Conversion Moves conversion units outside the Data Center Hall (DCH) to maximize premium space for AI/ML load racks. Increased Flexibility Enables greater adaptability in terms of rack types and connection configurations. Consolidated Backup Combines hundreds of in-rack batteries into a centralized row-level system for backup and load fluctuation mitigation. 1 Centralized SST 2 Energy Storage System (ESS) 3 DC Distribution 4 DC Protection Why DC Distribution and SST * Snapshot from “LVDC - Powering the Future Data Center: A Call to Action on Standardization and Native Designs”, presented by Jason Adrian, Krishnanjan Ravikumar, Google, in OCP EMEA Summit 2026
p5
SST Specification Rev 0.3: LVRT Requirement Grid VRT Requirements Blue line is the new ERCOT Requirement Voltage Ride Through the SST must meet SST compliance and capability profile Compliance Mandate Solid-State Transformers (SSTs) must satisfy stringent Over-Voltage Ride-Through (OVRT) and Low-Voltage Ride-Through (LVRT) compliance standards.
p6
SST Specification Rev 0.3: LVDC Architectures Distributed Redundancy Architecture Catcher-Based Architecture Energy Storage is a critical part of LVDC Architecture to support: a) AC Side: Utility Requirements such as Voltage Ride Through (LVRT) and Ramp rate. b) Load Side: Backup power and ML load fluctuation mitigation.
p7
SST Specification Rev 0.3: Alignment Electrical & Performance DC Output Interface 800 Vdc Unipolar output Voltage Tolerances & Regulation ±0.5% (switching freq. ripple) / ±1% static / ±3% dynamic (TBD) Overload Requirement 120% for 5s / Downstream protection: 150% for ~150ms Efficiency & Ramp Rate Eff: ≥98% (50-100% load) | Ramp: 20~50 MW/min System & Physical Specs DC Side Grounding Ungrounded or HRG for LVDC side (ground fault detection required) Dimensions Physical envelope range: 10-20’ L x 8’ D x 8.5’ H Environment Equipment Rating, Design Life, Humidity & Elevation Compliance Creepage, Clearance, Safety & EMI compliance
p8
SST Specification Rev 0.3: Flexibility SKU A MVAC Voltage 13.8 kVac ± 10% Power Rating (DC output) 5 MW Short Circuit Fault Current 18-40 kA symmetrical RMS 104 kA asymmetrical Basic Impulse Level (BIL) ≥110 kV @ 13.8 kV SKU B MVAC Voltage 34.5 kVac ± 10% Power Rating (DC output) 5 MW, 10 MW Short Circuit Fault Current 20-50 kA symmetrical RMS 130 kA asymmetrical Basic Impulse Level (BIL) ≥150-200 kV @ 34.5 kV NOTE:The 2 SKUs are defined to accommodate the different MV side Voltages between hyperscalers. The subsequent revisions will be built on these 2 SKUs ONLY.
p9
Looking Ahead : Key Milestones and Timeline Release Focus Spec Rev x.x Key technical specifications and system-level requirements included in the next milestone release. 01 Interface Specification for AC and DC sides 02 Telemetry and communication improved definitions 03 Medium Frequency Transformer (MFT) Partial Discharge (PD) requirements 04 Networking Requirements 05 System-level control for LVDC-level fluctuation mitigation
p10
Call to Action Ecosystem Drive Joint Effort Calling for joint collaborative efforts to drive the data center LVDC engineering ecosystem development. 01 SST Specifications Feedback Requesting feedbacks on the SST Specifications Rev 0.3 from Industry and Academia. SST Specification : SST Specification Rev 0.3 02 Build Test Case Libraries Requesting community collaborators to collectively build test case libraries covering: ● MV power quality from various types of energy sources ● LV load profile from different rack types running training or inference workloads
p11
Thank You!