flowchart LR
A[Agentic AI workloads<br/>多步驟推理 / tool use / orchestration] --> B[CPU orchestration layer<br/>Intel / AMD / Arm / NVIDIA Vera]
A --> C[GPU / accelerator layer]
B --> D[Host DRAM / memory interface<br/>Samsung / SK hynix / Micron / Montage / Renesas]
B --> E[BMC<br/>Aspeed / 信驊]
B --> F[CPU socket + PCIe / DRAM connector<br/>Lotes / FIT Hon Teng / 嘉澤]
B --> G[ABF substrate + server motherboard PCB<br/>Unimicron / NanYaPCB / Gold Circuit]
C --> G
D --> H[Storage<br/>NAND / eSSD / HDD]
G --> I[ODM / system integration<br/>Wiwynn / Lenovo / Inspur]
F --> I
E --> I
I --> J[Thermal / Power<br/>AVC / Auras / Delta / Lite-On]
K[Semi-cap / automation / EDA] --> B
K --> C
K --> D
classDef workload fill:#fff3bf,stroke:#8a6d00,color:#111;
classDef compute fill:#a5d8ff,stroke:#1c5d99,color:#111;
classDef memory fill:#c3fae8,stroke:#0b7285,color:#111;
classDef substrate fill:#b2f2bb,stroke:#2b8a3e,color:#111;
classDef component fill:#ffd8a8,stroke:#d9480f,color:#111;
classDef system fill:#d0bfff,stroke:#5f3dc4,color:#111;
classDef equip fill:#ffc9c9,stroke:#c92a2a,color:#111;
class A workload;
class B,C compute;
class D,H memory;
class G substrate;
class E,F,J component;
class I system;
class K equip;
各環節廠商
CPU / Compute
廠商
地位
備註
Intel
x86 CPU
Agentic AI 推動 CPU compute、wafer capacity、advanced packaging 需求
AMD
x86 CPU
1Q26 法說上修 server CPU TAM 口徑；Venice / Helios 為後續觀察
Arm
Arm CPU IP
AGI CPU demand 上修，hyperscaler Arm CPU 滲透率提高
NVIDIA
GPU + Vera CPU
AI compute solution provider，Vera CPU 帶動 CPU rack 觀察
Memory / Storage
廠商
地位
備註
Samsung / SK hynix / Micron
DRAM / HBM
MS 認為 agentic orchestration 推高 host DRAM 與 HBM cycle