PDF 原檔：報告_TrendForce_Lightmatter論壇_20260601_original.pdf
原始內容
矽光子異質整合封裝與測試之技術趨勢與挑戰
Technology Trends and Challenges in Packaging and Testing for SiPh Heterogeneous Integration
Jesse Wang Director, Supply Chain Operations 2026/05/28
Fidelity Google Ventures Sequoia Spark Capital
Viking T. Rowe Price Matrix Partners SIP Capital
MIT Stanford
Mountain View (HQ)
Hsinchu, Taiwan
Boston
Toronto
Nicholas Harris, PhD Founder, CEO
Simona Jankowski CFO
Roy Kim VP, Product
Boon Tan VP, Product Engineering
Darius Bunandar, PhD Founder, Chief Scientist
Ritesh Jain SVP, Engineering & Ops
Sujatha Wagle VP, Supply Chain Ops
Colin Sturt General Counsel
Steve Klinger VP, Ecosystem & Alliances
Praveen Kukkamalla VP, Sales
Thomas Graham Founder, Head of ML
Bob Turner SVP, Sales & Solution A rch
Beth Keil SVP, People
Kaushik Patel, PhD VP, Photonics & Si Eng
Kurt von Hausen VP, Cloud Services Sales
Granted & Pending
ywarwen@gmail.com 2026-06-22 from IP:125.228.95.152
The last 1,000x in AI performance was all about compute.
The next 1000x is all about interconnect.
CHIPS ARE GETTING BIGGER
I/O at the shoreline is not enough 3D-stacked photonics is the future
The Promise of Silicon Photonics
Moving Closer to the Chip
2025
GEN 1 Pluggables
17-20 pJ/bit
1x Speedup
2027
GEN 2 NPO/OBO/XPO
8-15 pJ/bit
2x Speedup
- Pre-packaged OE (PIC+EIC)
- LR SerDes, Re-timer
GEN 3 2D CPO
6-10 pJ/bit
8x Speedup
- I/O chiplet (PIC+EIC)
- In-package, XSR SerDes
2029+
GEN 4 3D CPO/Interposer
1-3 pJ/bit
100x Speedup
- 3D stacked PIC/EIC chiplet
- Standard pkg, UCIe
- Advanced package, OCS
From NPO to 3D Interposers, Lightmatter has the 10 year roadmap for photonics in validation racks today
Power Efficiency
Bandwidth
Reliability:
- Fewer Failure Points: It reduces discrete components and physical connectors, common points of failure in massive clusters.
- Thermal Stability: The integrated nature allows for unified cooling strategies, provide more stable temperature management for sensitive optical components.
Serviceability:
- Encouraging results with Pluggable Laser Sources (Remote Laser Module)
- Detachable Fiber Attach Unit (dFAU)
- Detachable Optical Engine
Advantages of CPO Technology
Why Hyperscalers Are Focusing on CPO Now
Power per bit must drop sharply
Cabling complexity must collapse
Reliability must improve at millionlink scale
System density must rise without copper/thermal overload
CPO Solves All 4 Simultaneously: Up to 1K XPUs at ¼ the power, 4X the Bandwidth, 5X Reliability
3D Stacking Needs Compact Optical Devices
Integrated Assembly and Test Process Flow
ywarwen@gmail.com 2026-06-22 from IP:125.228.95.152
Test Point Flow
Focus Areas for CPO development
KGOE Integration
Delivering Known Good Optical Engines (KGOE) for seamless mainstream packaging integration.
Cost Optimization
Economic solutions for Package, Assembly, and Test phases in high-volume flows.
Materials & FAU
Utilizing HVM-friendly materials and standardized FAU solutions for scalability.
Connect. Collaborate.
Fiber Attach
Driving breakthrough innovations in Fiber Attach Technology and detachable interfaces.
Deliver Known Good Optical Engines
xPU to OE link: routing on organic substrate xPU to OE link: routing on Silicon Bridge → EMIB Package Technology
xPU to OE link: routing on Silicon Bridge or Si Interposer → CoWoS_L/S Package Technology
Deliver Cost Effective Solutions
Backend Costs (PAT) are High. Driven by
- Assembly yield concerns due to fiber attach
- Higher test times
- Lack of standardization
Key Vectors:
- Design product with DFT/DFM upfront
- Drive Innovation in fiber attach
- Equipment & material development to improve throughput in assembly and test
SiPho Cost Breakdown
Note: Graph shown for demonstration purposes only
Deliver Scalable Fiber Attach Solutions
FAU cost
- -FAU is one of the main BOM cost
- -manual manufacturing process
- -Automated PM fiber orientation
- -Automated fiber insertion into MT ferrule
- -Standardization of connector spec
FAU facet with PM fiber
| High Yield |
|---|
| Meet Product Performance |
| High Throughput (UPH, units per hr) |
| Known Good OE |
| Scalable across package arch |
| Serviceability |
Materials
- -Single epoxy for the entire OE
- -Reflow compatible materials
- -Fast UV cure (<5 sec) instead of 30 sec to minutes
- -Low Tg (conforms with warpage change)
Deliver Scalable Solutions for HVM
Equipment
- -Transition to automated alignment in seconds, not minutes
- -Parallel processing: handling, alignment, dispense and UV cure
- -Re-configurable to support multiple products
LM Methodology & Partnership for HVM Readiness
Design/Architecture
- SI/PI
- Substrate Design
- Design for manufacturing /Reliability
- Thermal analysis
- Mechanical Design /Analysis
- Optical Analysis
Assembly/Test
- 2D and 3D Heterogeneous Integration & process dev.
- Wafer Electrical Sort and Optical Characterization
- Wafer and component test points through the process flow
Yield/Data Management
- Database with lot/unit level traceability
- Best known methods development to manage yield analysis
- Failure analysis and corrective action including binning strategies
Reliability/Validation
- Electrical and Compliance Tests -ESD, Latch Up, EMI/EMC
- Package/Environmental -TC, UHAST, HTS, S/V, Fiber Integrity
- Operational -HTOL
- Failure rate and Lifetime prediction
Lightmatter's Leadership in Photonics
10-year roadmap In sIlicon today
M1000 3D photonic superchip with recordbreaking 114Tbps bandwidth
Leading bandwidth density
World's first 16 -wavelength DWDM link: 800G/fiber bidirectional & 1.6T/fiber unidirectional
Rackscale quality and reliability
Validation data center with hundreds of photonic interconnects
3D Photonics Ecosystem
Custom ASIC Partners
Passage SerDes EIC Partners
Detachable Fiber Array Unit
Guide® VLSP Light Engine
ywarwen@gmail.com 2026-06-22 from IP:125.228.95.152
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