PDF 原檔：報告_OCP2026_Samsung_2030推論資料中心記憶體Pod_20261015_original.pdf
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圖片清單（已驗證 2026-10-19）
| 檔名 | 頁 | 分類 | 親眼所見內容 |
|---|---|---|---|
報告_OCP2026_Samsung_2030推論資料中心記憶體Pod_20261015_p3.png |
p3 | 真資料圖 | Inference AI Factories 示意：多個 Memory Pod（3D DRAM、HBM Over Optical、HBM5、SOCAMM）以光連結（Photonic Link）相連，GPU／NPU／ASIC／LPU／APU／CPU 等 rightsized compute 依工作負載掛上；標示 Exabyte→Zettabyte |
報告_OCP2026_Samsung_2030推論資料中心記憶體Pod_20261015_p4.png |
p4 | 真資料圖 | 2030 推論中心記憶體階層：L0 SRAM／zHBM、L1 HBM5／3D DRAM、L1.5 HBM Over Optical、L2 LPDDR／SOCAMM、L2.5 CXL Pool／zNAND-O、L3 KV SSD、L3.5 Ethernet SSD、L4 TLC／QLC SSD，右下表列各層延遲／頻寬／容量，對應 Decode／Prefill／MoE／In-Network Compute／Recovery Pod |
原始內容
p1
Inference Data Center 2030 Memory Pods Fabric with Rightsized Compute Mayank Saxena Chief Technologist Memory Solutions Lab Samsung Semiconductor
p2
GPU Data Center Divergence Today, AI Is Still in Its “Brute Force Era” Token Manufacturing Training A manufacturing cost to develop the product (models) that yields top quality tokens. Compute Centric GPU Cluster A revenue-generating factory serves the right token to the right customer at speed. Models Today: Compute-Centric AI Future: Memory-Centric Supercomputing Token Factory Inference Memory Centric Invert Pick Compute Right Size Everything Else Pick the Memory Fabric Right Size Compute
p3
Inference AI Factories Interconnected Data Ocean Linked by Photonics Memory Pod 3D DRAM Memory Pod HBM Over Optical Memory Pod 3D DRAM Memory Pod SOCAMM Memory Pod 3D DRAM Memory Pod HBM5 Memory Pod 3D DRAM Memory Pod HBM5 Memory Pod SOCAMM Memory Pod 3D DRAM Memory Pod HBM Over Optical Memory Pod 3D DRAM GPU NPU ASIC NPU Memory Pod Photonic Link Rightsized Compute Exabyte → Zettabyte GPU LPU LPU GPU CPU APU GPU ASIC Memory Pods Disaggregated 3D DRAM Tiers Scale-Free Photonic Fabric Exabyte → Zettabyte-Scale Access Rightsized Compute Attaches to the Fabric by Workload Model Data Becoming Fluid
p4
The Inference Centers of 2030 How Our Innovation Makes This Possible Blue = Memory Tiers Newly Introduced in the AI Era Memory Bandwidth Management Across All Layers of the AI Memory Hierarchy Hardware Evolution Deployment Tradeoff Memory-first architecture with composable compute, high-radix fabric with localized domains Decision You Make Today Define locality contracts and design fungible placement instrumentation per token path, not generic disaggregated memory HBM5, SOCAMM and glass substrates create high-density memory tiers Level Latency Bandwidth Capacity L0 < Tens of ns
Tens of TB/s Few MBs L0.5 TBD Few TB/s Few GBs L1 ~Tens of ns Few TB/s Tens of GBs L1.5 TBD Few TB/s Hundreds of GBs L2 ~Tens of ns Hundreds of GB/s Hundreds of GBs L2.5 Hundreds of ns Hundreds of GB/s Hundreds of GBs ~ 1 TB L3 ~Few µs ~Few GB/s Few TBs L3.5 ~Tens of µs Hundreds of GB/s Tens of TBs L4 ~Few ms ~MB/s Tens of TBs Power, Cooling, Fiber Global Control Plane & Memory Fabric L0/L1 Compute + Active State L1.5/L2 Context Memory Domain L3.5/L4 Shared Data + Recovery SRAM HBM Over Optical KV SSD zHBM LPDDR/SOCAMM Ethernet SSD 3D DRAM CXL Pool TLC SSD HBM5 zNAND-O QLC SSD Decode Pod GPU/NPU Prefill Pod GPU MoE/Kernel Pod In-Network Compute Recovery Pod CPU/DPU L0 L0.5 L0.5 L1 L1.5 L2 L2.5 L2.5 L3 L4 L4 Serviceable, Drained Failure Global Shared / Durable AI State Photonic Paths Across D omains Mem ory Scale s Context, Indepe ndently of Compute Short Electrical Path Compute <-> Active State L3.5
p5
Building the Future on Today’s Decisions Architecting AI Systems and Innovations Together Forum • Programming model • Benchmark suite • Reference solutions Partners • Ecosystem development • Commercial use cases Open Source & Standards • Software ecosystem • Common interfaces Academia • Use cases • Research and evangelization Open Innovation Ecosystem Design to Win Reconsider Your Strategy, Shift Innovation Focus, and Design To Win
p6
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p7
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