PDF 原檔：報告_OCP2026_Lumentum_Eliyan_Coherent_12.8T_VCSEL寬慢路線_20261015_original.pdf
講者公開簡報（OCP 官方 Recorded Content 頁提供下載）。文字以 PyMuPDF 逐頁抽取，
### p<n>為頁碼；圖表內容見原檔。
圖片清單（已驗證 2026-10-19）
| 檔名 | 頁 | 分類 | 親眼所見內容 |
|---|---|---|---|
報告_OCP2026_Lumentum_Eliyan_Coherent_12.8T_VCSEL寬慢路線_20261015_p2.png |
p2 | 真資料圖 | VCSEL 高密度互連賣點清單（可擴展、高頻寬密度、高能效、沿用組裝／光纖連接器生態、可靠度、量產）；右側 1060nm VCSEL HTOL 5000h（8mA、115C 烘箱→Tj 181C）之 Ith／光功率／電壓漂移曲線，5000 小時內漂移幾近平坦；左上 VCSEL 六角陣列晶片照 |
報告_OCP2026_Lumentum_Eliyan_Coherent_12.8T_VCSEL寬慢路線_20261015_p3.png |
p3 | 真資料圖 | Scalable Architecture 表：Pluggable 1.6T／3.2T、NPO 6.4T、CPO 12.8T；1.6T 每陣列通道數（含備援、FIT<1）：32G=54、50G=36、64G=30；CPO 示意 ~4mm、>6 Tbps/mm；介面 Ethernet／InfiniBand／UEC／PCIe／NVLink／UALink 與 D2D／UCIe |
報告_OCP2026_Lumentum_Eliyan_Coherent_12.8T_VCSEL寬慢路線_20261015_p4.png |
p4 | 真資料圖 | CMOS 整合兩種封裝剖面：Wafer-level Fan-Out Package（Heat spreader／DRV／V／RDL／Substrate）與 3D stacked（PD、VCSEL 疊在 PHY／TIA／CDR／Driver／ASIC 上）及對應晶片照 |
報告_OCP2026_Lumentum_Eliyan_Coherent_12.8T_VCSEL寬慢路線_20261015_p5.png |
p5 | 真資料圖 | PCIe 光互連 PoC：Lumentum 1060nm VCSEL+PD 光引擎（置於硬幣上）、Astera Labs Scorpio PCIe switch 四周接光引擎之拓撲、Corning 光纖、機櫃托盤實物（黃色光纖），右下 GUI 顯示 BER；文字：~1 Tb/s/mm、<2.5 pJ/bit 路徑、PCIe-5 OM3 無錯 |
原始內容
p1
Oleg Shchekin Lumentum VCSEL-based High Density Interconnects OCP SPECIAL FOCUS: PHOTONICS
p2
• Scalable architecture • High bandwidth density • High energy efficiency • Existing assembly methods • Existing fiber and connector ecosystem • Reliability • High-volume manufacturing VCSEL-based High Density Interconnects 1060nm VCSEL HTOL 5000 h 8mA 115C oven → Tj 181C 3D Sensing Supply chain
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Application Scale-up, Scale-out Scale-in Form Factor Pluggable NPO CPO Array 1.6T 3.2T 6.4T 12.8T Configuration examples Protocol/ Interface Ethernet, InfiniBand, Ultra Ethernet, PCIe, NVLink, UALink D2D, UCIe 32G, 64G NRZ Scalable Architecture Gearbox 8X4 50G NRZ 8 x 200G PAM4 Channel data rate 1.6T: Channels/array for with sparing for FIT < 1 32 Gbps 54 50 Gbps 36 64 Gbps 30
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CMOS Integration Wafer-level Fan Out Package (WLFOP) 3D stacked Heat Spreader DRV V Fan-out pkg DAF TIM RDL Substrate
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PCIe Optical Connectivity GUI with measured BER 1060nm VCSEL+PD Optical Engine High-density optical PCIe solution for AI scale-up/in Tens-of-meters reach over multimode fiber ~1 Tb/s/mm today; line of sight to ~4 Tb/s/mm Designed for emerging wide/slow and narrow/fast interfaces Proof-of-Concept Rack-level Demo: 1060nm 3D FOWLP VCSEL/PD Tx+Rx optical engines Scorpio PCIe switches in the same NPO / CPO-like rack tray Multiple 32 Gb/s NRZ channels running live Error-free PCIe-5 link over OM3 multimode fiber Optical engine path to <2.5 pJ/bit Live Demonstration of Optical PCIe Connectivity: Booth B34
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• Continue dialogue on • System requirements and key figures of merit • Energy efficiency (pJ/bit) — including definition of the system boundary • Reach, latency, and cost for key use cases • Establish consistent metrics to enable meaningful technology comparisons • Ecosystem of electronics, fiber solutions and connectors Call to Action
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Thank You!