PDF 原檔:報告_OCP2026_Huawei_開放NPO標準_20261015_original.pdf
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圖片清單(已驗證 2026-10-19)
| 檔名 | 頁 | 分類 | 親眼所見內容 |
|---|---|---|---|
報告_OCP2026_Huawei_開放NPO標準_20261015_p6.png |
p6 | 裝飾·logo·banner | Open NPO 專案組織圖:Global Computing Consortium 300+ 會員、Open AI Infra 分會 200+、Open NPO 專案 40+ 成員;列用戶單位與光互連產業鏈單位 logo 牆;2026.6 籌備、2026.7 啟動 |
報告_OCP2026_Huawei_開放NPO標準_20261015_p7.png |
p7 | 真資料圖 | Open NPO 專案 roadmap:~2025 LPO-800G 相容(800G@112G/L)、2026~2027 Phase I type1 電連接器(xxT@224G/L)、2027~2028 Phase II type2 高密度(1000+ Radix)、2029~2030 Phase III OIO 光介面;電連接器樣品與 NPO 模組(Hi-ONE)測試中 |
報告_OCP2026_Huawei_開放NPO標準_20261015_p8.png |
p8 | 真資料圖 | Open NPO 標準內容 1:電連接器公母座 3D 外觀、剖面(標註 5.0)與應用示意(模組兩側各一連接器) |
報告_OCP2026_Huawei_開放NPO標準_20261015_p12.png |
p12 | 真資料圖 | Open NPO 連接器 pinmap:26 列 x 16 欄,中間 12 欄為 TX/RX 差分對與 GND 交錯,首尾欄為電源與低速腳位;72 對差分(36 通道)、96 個電源與低速腳位 |
報告_OCP2026_Huawei_開放NPO標準_20261015_p15.png |
p15 | 真資料圖 | Open NPO 電連接器實測:插損(含測試板)、回波損耗(去嵌)、近端與遠端串擾(去嵌)、阻抗 TDR(約 87-90 ohm) |
報告_OCP2026_Huawei_開放NPO標準_20261015_p16.png |
p16 | 真資料圖 | SuperPOD 實作情境:2027-2028 L1 SW 與 L2 SW 間用 NPO、交換容量倍增;2028-2029 XPU 以 1~2 個 OE 光輸出組大型扁平 POD |
原始內容
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Qirui Fan Standard Representative Huawei Weiqiang Xu Standard Representative Huawei Open NPO Standards: Building the Optical Interconnect Ecosystem for SuperPOD OCP SPECIAL FOCUS: PHOTONICS
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• Emerging Trends in Optical Interconnect • What is OPEN NPO? • OPEN NPO Project – Overview of Electrical Connectors • Call to Action Contents
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Linear Optical Interconnects: Building the Physical Foundation for Scale-Up Superpods Under System τ Scaling Law • Refactor the system interconnection architecture to compress signal propagation delay • Linear optical interconnects are essential for boosting bandwidth, managing power and heat, while delivering ultra-low latency in superpods. Tao (τ) Scaling Law Released Past: Geometric Scaling Tao (τ) Scaling Law Future: Time Scaling Time scaling: Superpod performance leap system-level architecture reconstruction: xPU bus interconnect for superpod, And system time-scale miniaturization Physical connectivity as the cornerstone: Linear high-density optical interconnect solution Superpod Built on Linear High-Density Optical Interconnects
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NPO has become the preferred short-term option for scaling up optical interconnects NPO has been widely chosen by Chinese Internet enterprises, telecom operators, and system vendors as the primary optical interconnect technology for superpod deployment. • Maintainability: Easy to replace, good for customer maintenance • Open decoupling: Decoupling chips from OE enables diversified supply • Availability: Low process requirements, relatively mature manufacturing • Industry Implementation: The industry supply chain technology is well-developed and ready, allowing products to be launched quickly. Advantages of NPO Industry Applications
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Electrical connectors are the core bottleneck in NPO industry promotion • Computing / switching module: Requires differentiated design. • OE: Requires customization; not for multiple users. • Computing / switching and OE modules from different vendors are incompatible. The NPO aims to promote and apply it in the industry. Electrical connectors urgently require standardization and a unified technical roadmap. QDD Connector PCB Connector OE substrate EIC PIC … Socket Formation Clamp Plate Formation NPO electrical connectors feature multiple product designs and lack unified technical approaches. Impact
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What is OPEN NPO? • Open NPO optical interconnection project • All Open AI Infra community members may participate. OPEN NPO Project Address: https://openaiinfra.gccorg.com/projects/ai-cabinet Objective: Unify the NPO electrical connector and promote its industry implementation. 26.6 Preparation and Planning 26.7 Start-up An industry organization established by computing technology providers, manufacturers, system integrators, enterprise users, and research institutes. 300+ members 200+ members 40+ members User Organizational Unit Optical interconnection industry chain units … …
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OPEN NPO: Project Plan Optical Interconnect 2027~2028 2026~2027 standardized high-density electrical connectors. 3D miniaturization, 1000+ Radix Define type1 electrical interface • xxT capacity @ 224G/L • Integrated light source architecture • Standardized NPO electrical connector Define type 2 high-density electrical interface. Low latency, high bandwidth ~2025 Compatible with LPO-800G specs. • 800G@112G/L • Pluggable panel, mature standards Low latency, easy maintenance. 2029~2030 Define OIO optical interface. Concept image: Internet source. Current Industry Commercial Status Phase I Phase II Phase III apply Electrical connector sample testing in progress. The NPO module is being tested. The OPEN NPO project focuses on electrical connectors, planning a phased release of two types. Type 1 connector and NPO module samples are currently being tested.
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OPEN NPO: Standard Content 1 – Electrical Connectors Electrical Connector Shape and Appearance It offers strong versatility and compatibility, adapting to NPO modules of various specifications and sizes. Electrical Connector Application Scenarios
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OPEN NPO: Standard Content 2 – Male Electrical Connector Drawing 3D drawings are contributed to the Open AI Infra community.
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OPEN NPO: Standard Content 3 – Female Electrical Connector Drawing 3D drawings are contributed to the Open AI Infra community.
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OPEN NPO: Standard Content 4 – Footprint Connector footprint on the OE side for soldering the board to the connector. Host-side connector footprint for soldering the board to the connector. Pad Definition
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OPEN NPO: Standard Content 5 – Pinmap Power Supply & Low Speed GND TX RX 72 differential pairs (36 channels) and 96 power and low-speed pins. Differential pairs occupy the middle 12 columns; power and low-speed pins occupy the first and last columns.
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OPEN NPO: Standard Content 6 – Mechanical and Reliability Specifications Mechanical and reliability specifications for electrical connectors. item Specifications Number of pins High-speed differential: 72pair Low speed & power supply: 96pin Terminal Configuration and Spatial Layout Low-speed areas are at both ends, with high-speed areas in the middle. Total Insertion Force Maximum 150N Total extraction force Initial removal force: 20 N min @ full mating Maximum removal force during the entire removal process: 80 N Wafer Retention Force Minimum 2N Terminal forward force Initial: 30gf min @0.25mm compression; 15gf min @0.15mm compression; After high temperature: 12gf min @0.12mm compression; durability 50 times Resilience to Stress The connector's pressure-bearing surface is at the four corners of the female connector; the center bears no pressure. Instantaneous pressure-bearing capacity: 380N min. Long-term pressure-bearing capacity: 183N min.
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OPEN NPO: Standard Content 7 - Electrical Specifications Electrical specifications of the electrical connector item Specifications rated current 1A/pin (Applicable to pins located in low-speed and power supply domains) rated voltage 12V DC (Applicable to pins located in low-speed and power supply domains) Impedance Magnitude Impedance of the connector body: 80-90 ohm ; SI IL≤1.5dB@10MHz~56GHz EL ERL≥11dB ,The calculation conditions are based on the OIF CEI-224G-Linear standard. cross talk The test board contains the MCB and HCB, 100 mil traces, vias, and connectors. Frequency- domain crosstalk specifications are for reference only. Single-channel near-end crosstalk: NEXT:<= -50dB@10MHz~56GHz;<= -45dB@56GHz~67GHz; Single-Path Far-End Crosstalk: FEXT:<= -45dB@10MHz-56GHz;<= -40dB@56GHz~67GHz; Maximum temperature rise under rated current conditions 30℃
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OPEN NPO: Electrical Connector Test Data Return Loss Insertion Loss Near-end Crosstalk Far-end Crosstalk Impedance After de-embedding After de-embedding With test board With test board After de-embedding
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OPEN NPO: SuperPOD Implementation Solution and Plan SW Interconnection and XPU Light Output establish diverse computing power clusters. SW SW SW SW compute rack L2 SW L2 SW L2 SW L2 SW L2 SW L2 SW L2 SW L2 SW L1 SW Bus Device SW SW SW SW (2027–2028) Scenario 1: Super POD, SW (L1) ↔ SW (L2). NPO doubles networking switching capacity. • XPU: 1~2 x OE • SW: OE Computing board SW Bus Device switch SW SW SW SW XPU XPU module (2028–2029) Scenario 2: The XPU, deployed in a large flat-layer POD, provides ultra-low latency optical signals via the NPO. SW SW SW SW SW SW SW
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• We are willing to contribute content related to the OPEN NPO project to OCP and welcome more companies and organizations to participate in this project together. • How to get involved in the project/sub-project community:At the current stage, contact wangdongwei@gccorg.com first. • Timeline for contribution availability: first step 2026.12.30 • Where to find additional information (URL links) • Project address : https://openaiinfra.gccorg.com/projects/ai-cabinet Call to Action
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Thank You!