PDF 原檔:報告_OCP2026_AsteraLabs_NPO與CPO_ScaleUp_20261015_original.pdf
講者公開簡報(OCP 官方 Recorded Content 頁提供下載)。文字以 PyMuPDF 逐頁抽取,
### p<n>為頁碼;圖表內容見原檔。
圖片清單(已驗證 2026-10-19)
| 檔名 | 頁 | 分類 | 親眼所見內容 |
|---|---|---|---|
報告_OCP2026_AsteraLabs_NPO與CPO_ScaleUp_20261015_p8.png |
p8 | 真資料圖 | 七種互連形態示意與距離:Passive DAC 至 3m、ACC 4m、AEC 7m、AOC/LPO/NPO/CPO 皆 >50m,附功耗與延遲等級;右圖為銅纜隨速率變粗、光纜粗細不變 |
報告_OCP2026_AsteraLabs_NPO與CPO_ScaleUp_20261015_p11.png |
p11 | 真資料圖 | NPO 對 CPO 比較表:灘頭密度、功耗、可維修性、外型一致性、製造複雜度、最可能用途(NPO 近期多櫃 scale-up、CPO 下一代 switch/XPU) |
報告_OCP2026_AsteraLabs_NPO與CPO_ScaleUp_20261015_p14.png |
p14 | 真資料圖 | 混合銅光 pod 與全光 pod 機櫃示意:混合 pod 為櫃內銅背板、NPO 櫃間,目標 72–576 顆加速器;全光 pod 用 NPO/CPO,目標 >576 顆 |
原始內容
p1
Chris Blackburn Director of Platform Solutions Architecture, Astera Labs Jignesh Shah Sr. Director of Product Marketing, Signal Connectivity Group, Astera Labs Light on the Horizon: Architecting Scale-Up Fabrics with NPO & CPO for the Next-Gen Data Center OCP SPECIAL FOCUS: PHOTONICS
p2
AI is Rewriting the Rules of the Data Center Model sizes doubling every 12–18 months with parameter counts moving from hundreds of billions to trillions Scale-up fabric is now a first- order design constraint, not an afterthought GPU/accelerator clusters scaling from dozens to thousands of endpoints The interconnect is the bottleneck — compute is only as fast as the fabric allows
p3
Trend Today Tomorrow Scale-Up Pod Size 8–72 XPUs / pod 144–1000+ XPUs / pod Topology Scale-Up then Scale-Out Increased Scale-Up Domain Bandwidth PCIe 5/6, 200G/lane PCIe 7 → 8, 400G+/lane Three Forces Reshaping Scale-Up Fabrics • Scale-up size increasing to keep pace with AI workloads (ex. Agentic inference, Recursive Self-improvement) • Single-hop topologies reduce latency and increase XPU utilization — critical for all-reduce collective operations • PCIe 6→7→8, UALink & ESUN 200G/lane → 400G/lane: bandwidth doubling, increased frequencies, shrinking electrical channel distance System architectures are evolving to align with these key trends
p4
The Five Pillars of Customer Decision Making No single technology wins on all five dimensions. The right answer depends on the application. Power Cost Speed to Deployment Reliability & Serviceability • Watts per XPU-XPU bit • Total rack / pod power envelope • Power usage effectiveness (PUE) • CAPEX (NRE & BOM) • OPEX (power, spares, maintenance, uptime) • Supply chain readiness • Cabling complexity • Production & installation timelines • MTBF • Redundancy architectures • Fabric healing • Hot-swap • FRU granularity • Diagnostics Performance • Signal integrity • Maximum interconnect distance at Nyquist frequency • Bundle size and density
p5
One Size Does NOT Fit All Optics Copper Training Cluster Longer Links • Long sustained all-reduce collectives • High bisection bandwidth is critical • Large physical distances between nodes Inference Cluster Shorter Links • Short burst, latency sensitive traffic • TCO sensitivity, prioritizes bandwidth per dollar • Shorter physical differences between nodes (but growing!) Technology choice is not binary – copper and optics will coexist
p6
• NVLink, PCIe, & UALink scale-up protocols viable over copper for this generation and next generation • Copper cable backplanes are ubiquitous scale-up interconnect architecture today • DACs, ACCs, AECs handle inter-rack scale-up connections Today’s Fabrics: Proven, Copper-based, and Evolving
p7
Copper Delivers the Backbone for Next-Gen Scale-Up Power Cost Speed to Deployment Reliability & Serviceability Performance Copper will not disappear. The question is where the boundary sits — and that boundary is evolving. Lowest bandwidth per dollar Lowest power per bit Continues to support next-gen data rates Proven, ready supply chain Decades of maturity
p8
Data Rate Thickness of Cu Copper Cable Limitiations, www.silicon-line.com • Pod sizes beyond 144 GPUs require physical distances that need the reach of Optics • High Radix Switches and XPUs require higher density connectivity solutions • Increasing data-rates brings optics closer to the Silicon • Lower system power, lower link latency with optics Why Optics is Coming to Scale-Up Up to 7m Medium Power Medium Latency
50m High Power High Latency 50m Low Power Ultra Low Latency 50m Low Power Ultra Low Latency 50m Lowest Power Ultra Low Latency Up to 4m Low Power Low Latency Up to 3m Lowest Power Ultra Low Latency
p9
• Density: Higher beachfront density of NPO than front panel pluggable modules • Power: Significantly lower than retimed pluggable • Latency: Ultra-low with linear optics • Optical connectivity: Requires robust on-board fiber routing • Serviceability: Electrically pluggable, fiber-pigtailed • Ecosystem maturity: Uses existing front panel module manufacturing and test ecosystem • Yield / Cost: Increased lane count as compared to pluggables NPO: Near-Packaged Optics
p10
• Density: High Radix scalability, Highest beachfront utilization • Power: Best-in-class W/Tbps • Latency: Ultra-low — no additional signal conditioning in end-to-end link • Optical connectivity: Detachable Fiber-to-package interface • Serviceability: Not easy as Co-packaged ‘Optics + Switch’ • Ecosystem readiness: WIP for Supply chain, Advanced packaging, Testing and Standards • Yield / cost: Increased package complexity affects overall yield CPO: Co-Packaged Optics
p11
NPO CPO Beachfront Density Enough for near-term applications Scalable for future high radix applications Power Significantly lower than pluggables Lowest of all optical architectures Serviceability Good, Electrically detachable like pluggables Difficult, if optical engine integrated with Switch/XPU Form Factor Commonality Cu and Optics Optics only Manufacturing Complexity Low, leverages existing ecosystem High, new ecosystem of partners needed Most Likely Use Case Near-term multi-rack AI scale up Next-generation switch and XPU platforms NPO & CPO Comparison
p12
The Sweet Spot: Hybrid Copper & Optics Copper Optics • Utilize copper for links within chassis, within rack, and for rack to rack • Use retimers and redrivers to extend the reach of copper where necessary • Optimize for cost and power • Utilize optics for links from rack to rack and across the pod • Use linear optics, NPO, & CPO technologies to reduce pJ/bit • Optimize for physical reach and density Flexibility in Connectivity enables Optimized AI Infrastructure
p13
Copper & Optics Form Factor Commonality Pluggable Form Factors DAC / ACC / AEC AOC Transceiver Near-Packaged / Co-Packaged Copper Optics
p14
Hybrid (Copper & Optics) Pod Architecture Hybrid Copper / Optical Pod Full Optical Pod • Continue to use copper cable backplanes to scale up within the rack • Use NPO to scale up rack to rack • Direct to GPU or Switch-Switch • Targeted towards scale up sizes between 72 and 576 accelerators • Dedicated compute and switch racks • Use NPO / CPO to scale-up whole pod • Targeted towards scale-up sizes >576 accelerators Optics Copper
p15
The Path is Clear. Let’s Build it Together. The next generation of AI infrastructure will be defined by the interconnect, not the compute. Copper built the foundation. Optics will build the ceiling. The architectures that win will use both — intelligently, in the right places, for the right reasons. NPO and CPO are not a threat to existing investments. They are the natural evolution of a fabric that has to scale by orders of magnitude in the next five years. Copper continues to thrive as Optics comes alive
p16
• Engage across OCP & other industry standards to drive ecosystem alignment • Visit the Astera Labs Booth B34 to learn more about the switches that enable these architectures • Visit AsteraLabs.com for more information • Come chat with us at the show or drop us a line: Jignesh.Shah@AsteraLabs.com & Christopher.Blackburn@AsteraLabs.com Call to Action
p17
Thank You!