PDF 原檔:報告_MS_記憶體創新_20260901_original.pdf
圖片清單(已驗證 2026-10-23)
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52KB | 真資料圖 | 折線圖(對應 Exhibit 2「NOR flash demand and supply growth rates」):Demand growth(藍)與 Total wafer supply growth(黃)年增率,2012–2028 |
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44KB | 真資料圖 | 長條圖(對應 Exhibit 3「NOR flash demand growth and supply growth by density」):2019–2028 的 Demand growth、Total wafer supply growth、Low density wafer supply growth、Mid-high density wafer supply growth |
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105KB | 真資料圖 | 柱狀+折線圖(Exhibit 4「DDR4 quarterly supply and demand summary」):Supply/Demand(mn Gb,左軸)與 Oversupply/(undersupply) ratio(右軸),1Q23–約 4Q28e,ratio 2026 起維持約 -15% 至 -20% 區間 |
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88KB | 真資料圖 | 堆疊柱狀圖(Exhibit 6「Quarterly supply breakdown (mn Gb)」):Samsung/Hynix/Micron/CXMT/Nanya/Winbond/PSMC/JHICC 各季 DDR4 供給,1Q23–4Q28e,總量由約 36,000 降至約 5,000 mn Gb |
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73KB | 真資料圖 | 折線圖(Exhibit 8「DDR4 8Gb (1Gx8) pricing chart」):Spot(藍)終點 29.08、Contract(黃)終點 20.00,2019-01–2026 年中 |
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120KB | 真資料圖 | 折線圖(Exhibit 5):DDR4 Oversupply/(undersupply) ratio 對照 Nanya pricing Q/Q change 與 Winbond pricing Q/Q change,1Q23–4Q28e |
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93KB | 真資料圖 | 堆疊柱狀圖(Exhibit 7「Quarterly demand breakdown by product (mn Gb)」):Smartphone/PC/Server/TV/Switch/Cache DRAM/Others,1Q23–4Q28e |
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101KB | 真資料圖 | 折線圖(Exhibit 9「DDR5 16G (2Gx8) 4800/5600」):Spot 終點 45.00、Contract 終點 37.50,2023-01–2026 年中,2025 下半年起急升 |
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73KB | 真資料圖(股價與目標價沿革) | 股價(藍線)與目標價階梯(紅虛線)圖,2023/09–2026/09;目標價標示 500、555、666、580、300、235、390、415、435、475、555、607、700、777、1000、1555、1666(最右段 1666);圖上無公司名稱,PT 序列與愛普(6531)既有 1,555 吻合 |
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57KB | 真資料圖(股價與目標價沿革) | 股價與目標價階梯圖;目標價標示 26.5、26、24、23.5、16.5、29、40、48、72.5、93、121、202、220(最右段 220);圖上無公司名稱,PT 220 與旺宏(2337)既有 PT 吻合 |
報告_MS_記憶體創新_20260901_011.png |
39KB | 真資料圖(股價與目標價沿革) | 股價與目標價階梯圖,資料自 2026 年初起;目標價標示 212、310、432(最右段 432);圖上無公司名稱,依報告估值段落推定為 Montage(6809.HK) |
報告_MS_記憶體創新_20260901_012.png |
65KB | 真資料圖(股價與目標價沿革) | 股價與目標價階梯圖,2023/09–2026/09;目標價標示 63、68、70、80、65、83、90、88、100、190、274、377(最右段 377);圖上無公司名稱,377×1.15≈432 與 011 的 HKD 目標價吻合,推定為 Montage(688008.SS) |
圖號與報告 Exhibit 編號並非按序(抽圖順序為 Ex2、Ex3、Ex4、Ex6、Ex8、Ex5、Ex7、Ex9)。Exhibit 1(DRAM/NAND 各品項 QoQ 價格預測表,Trendforce/MS 估)為文字表格,本 md 未收錄,內容見原檔 PDF 第 3 頁。
原始內容
M September 1, 2026 06:03 PM GMT
Greater China Semiconductors | Asia Pacific
Memory Innovation - The Focus from SEMICON Taiwan
SEMICON Taiwan highlighted memory value creation shifting from bit scaling toward architecture-level innovation. OW on AP Memory for emerging 3D WoW stacking. OW on Montage for memory interface opportunities. OW on Macronix for SLC NAND.
Key Takeaways
- Architecture-level innovations span memory interfaces 3D integration, computing-near-memory, and new AI use cases on NAND.
- Inference shifts Al bottleneck to memory bandwidth, capacity, and data movement.
- 3D stacking is likely to be the next major architecture beyond today's 2.5D HBM, supporting new opportunities for Top Pick AP Memory.
- NAND moves up the Al memory hierarchy; creates new opportunities beyond storage.
- Memory and computing are converging through PIM, custom HBM, and nearmemory architectures.
For a broader discussion of these technologies, please refer to our Global Insight: Innovating the Next-Generation Memory.
Memory is becoming a system-level differentiator: AI performance is increasingly constrained by memory rather than computing. Longer context, agentic workflows, and KV cache growth are raising the importance of bandwidth, capacity, and latency, with tokens/$ and tokens/W becoming more relevant metrics. We see this reinforcing the strategic importance of memory architecture as AI inference scales.
3D stacking is likely to be the future trend beyond today's 2.5D architecture: .
Samsung's zHBM and broader DRAM-on-logic concepts point to memory moving from beside computinge toward vertically integrated architecture. This should increase the importance of hybrid bonding, WoW integration, and thermal co-design. We see AP Memory as a potential beneficiary of emerging 3D WoW stacking opportunities.
Memory interfaces are becoming more strategic: As AI systems adopt heterogeneous memory tiers across HBM, DRAM, CXL, SRAM and flash, connectivity and control between computing and memory become complex. Google mentioned that CXL is used to leverage old DDR4. We believe this raises the value of memory interface solutions and reinforces our OW view on Montage.
(Continued in the following section)
Idea
| Morgan Stanley Taiwan Limited+ Daniel Yen, CFA Equity Analyst Daniel.Yen@morganstanley.com | +886 2 2730-2863 |
|---|---|
| Charlie Chan Equity Analyst Charlie.Chan@morganstanley.com | +886 2 2730-1725 |
| Daisy Dai, CFA Equity Analyst Daisy.Dai@morganstanley.com | +852 2848-7310 |
| Ethan Jia Research Associate Ethan.Jia@morganstanley.com | +852 3963-2287 |
| Greater China Technology Semiconductors | Greater China Technology Semiconductors |
| Asia Pacific Industry View | Attractive |
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