報告_MS_科技供應鏈_20260706

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原始內容

M July 6, 2026 02:20 AM GMT

Asia-Pacific Technology | Asia Pacific

Connecting Dots in Tech Supply Chain: CoPoS, T-Glass/TPU, Glassbridge/FAU

TSMC has reportedly pulled forward CoPoS to address Intel EMIB-T competition. MediaTek TPU volumes have upside after securing Japan T-Glass. Taiwan's CPO supply chain development remains on track; Glassbridge seems remote at this stage.

What's new? Investors are asking how we reconcile views and research from tech supply chain analysts, which may sometimes look inconsistent. Last year's most popular example was upstream CoWoS capacity-implied chips vs. AI server rack consumption ( link ). We try to connect the dots here.

1. T-Glass shortage vs. TPU volume upside: MediaTek gets more T-Glass supply from Japan for its 3nm Google TPU project . In MediaTek: Upside in both cloud and edge chip business; OW (23 Jun 2026) , we noted that MediaTek can assist Google (covered by Brian Nowak) in sourcing more T-Glass from the Japanese fiber material vendor to secure supply. Hence, we see upside to our shipment and revenue assumptions for 3nm ZebraFish TPU - we now forecast 3mn units in 2027. The question here is - how can MediaTek source even more T-Glass supply?

Our Japan manufacturing analyst, Yoshihito Hasegawa, believes that Nitto Boseki, which he covers, is the leading T-glass supplier for Google's TPU. According to our hardware analyst, Howard Kao, Zhen Ding is likely MediaTek's key second source for 3nm TPU substrates alongside Unimicron. However, Howard believes Zhen Ding's primary value drivers are its exposure to China AI chip ABF substrates, optical transceiver module PCBs, and AI server PCBs rather than TPUs ( Zhen Ding: Strong preliminary May profits [22 Jun 2026]) . See Howard's analysis of CoWoS capacityimplied substrate demand vs. ABF substrate supply gap ( Exhibit 3 ).

1. TSMC CoPoS pulled forward? According to news reports , TSMC's CoPoS will collaborate with Ibiden (covered by Shoji Sato) for substrates, and with Innolux (covered by Derrick Yang) focusing on TGV (Through Glass Vias) for Nvidia's Feynman GPU. TSMC guided that CoPoS mass production should be from 2028/2029. Glass core substrates are critical to large reticle size chips, mainly but not limited to the CoPoS packaging (meaning it can be used for large CoWoS packaging as well), although our checks indicate that glass core substrate and CoPoS do not have to be adopted at the same generation of GPU.

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For analyst certification and other important disclosures, refer to the Disclosure Section, located at the end of this report.

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From our foundry supply chain checks, CoPoS could be adopted in the Feynman Ultra in 2029, while the first generation Feynman in 2028 would use TSMC's 3D stack (die to wafer) for GPU stacking with SiC carriers to assist with chip thermal management. The key question is whether TSMC will bring forward the CoPoS timeline for Feynman in 2028.

According to Derrick Yang (Greater China - Displays: Progress for Glass in Advanced Packaging among Panel Makers [29 Jun 2026]), we do see the potential of glass panels in semiconductors, as the package size gets bigger - though a more realistic timing for HPC adoption looks to be 2028/2029. Innolux will conduct the TGVs (Through Glass Vias) process on a glass panel (510mm*515mm), before sending that to Ibiden for substrate processes. For Innolux, the challenges lie in forming TGVs and the subsequent copper plating, because this is not part of the regular display panel production. Our understanding is that Innolux will need to procure new equipment for glass cores. The major CoPoS fab will be TSMC AP7 (see Exhibit 5 ), located in Tainan, Taiwan, close to Innolux's factory. Innolux's TGV production is likely to be in 2028, and we see a small chance of early adoption at Feynman.

Howard Kao, who covers Greater China substrate names, indicated there could be more substrate vendors apart from Ibiden to supply the glass core substrates in future. We believe the major technology bottleneck is the TGV process given glass scrap issues; again, we think 2029 is more likely timing for CoPoS.

1. GlassBridge to replace or complement to FAU in CPO? Fiber Array Units (FAU) are used to connect the optical fibers to the optical engines around the networking chips. According to our hardware analyst Andy Meng's report, Greater China Technology Hardware: GlassBridge and Fiber -to -PIC's Implications for AI Transceiver and FAU Makers (28 Jun 2026), Corning GlassBridge is a fiber to PIC connector platform that brings optical fiber directly to a photonic integrated circuit (PIC). For AI transceiver companies (e.g. Eoptolink, covered by Andy), the impact should be limited as GlassBridge can be used in both CPO and NPO. However, GlassBridge adoption timing remains to be seen, along with whether it would complement FAU based approaches by offering a wafer based, passively aligned alternative.

According to our semiconductor analyst, Tiffany Yeh (see her latest report, link), we do not rule out that GlassBridge could hamper FAU's TAM in the long run, but we are yet to see any projects in TSMC's COUPE platform that have adopted this technology. On the other hand, GlassBridge mainly serves edge coupling, and can only currently support one -dimension fiber layouts. However, TSMC's mainstream COUPE platform and key customers' solutions, such as NVIDIA, AMD (both covered by Joseph Moore), and Ayar Labs, are still sticking to grating coupling for the next few years, as it is easier to achieve mass production - which we expect in 2H26. Lastly, CPO requires integrated design and discussion across the whole ecosystem - including foundry (OE), chip designer, FAU, laser, and even system integrator - so it is hard to change a design overnight. GlassBridge is an ideal solution but we believe it remains far from mass production. We see TSMC scaling PIC capacity to 25kwpm in 2028, with Ins2 test efficiency improving. We stay overweight on CPO enablers, as investor expectations are already on the floor.

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ELECTRO-MECHANICS

Connecting Dots in Asia Tech - Key Exhibits

Google

Design customers /

Hyperscalers

MEDIATEK

IC Design

Unimicron

Exhibit 1: Key Asian supply chain companies under our coverage

Source: Morgan Stanley Research

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Exhibit 3: Expecting ABF substrate under-supply gap to widen by 2030 vs. our prior estimates

T mm²

Source: Morgan Stanley Research (e) estimates.

Exhibit 4: Increased demand assumptions causing CY29-30 under-supply gap to widen vs. our prior estimates

Source: Morgan Stanley Research (e) estimates.

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Overview of Technologies discussed in this Report

CoPoS

Chip-on-Panel-on-Substrate (CoPoS) is an emerging TSMC technology aimed at scaling package size and reducing cost: By moving toward panel-level or large-area RDL-based packaging, CoPoS enables much larger integration footprints beyond the reticle limits of silicon interposers. This makes it attractive for next-generation AI systems that require integrating many large dies. Its advantages lie in scalability and potential cost efficiency at large sizes, but it is less mature than CoWoS and offers lower interconnect density. As such, it is not yet ideal for the most bandwidth-critical interfaces, and is still evolving in terms of ecosystem and manufacturability.

However, given the recent needs of larger sizes of chip design, and competition from Intel (covered by Joseph Moore), we believe the schedule for TSMC CoPoS could be pulled forward earlier to 2028, in the hope of meeting the needs of those GPU or AI ASICs adopting 2nm process or below.

Exhibit 5: TSMC's advanced packaging fab planning

Source: Company data, Morgan Stanley Research

Exhibit 6: Comparison between TSMC's CoWoS, CoPoS, SoIC, and Intel's EMIB-T

Source: Morgan Stanley Research

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Group

COMPARISON OF WLP AND PLP

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Size does matter!

-10% cost decrease

300x300mmª panel

16 interposers

Area efficiency -81%

Exhibit 7:

CoWoS, CoPoS and FoPLP comparison

600x600mm? Panel

64 interposers

Area efficiency -81%

Source: Yole

Glass Core Substrates

Though the ultimate goal of glass-core substrates is to support multiple high-performance computing chips, they can also serve applications with less demanding specifications. Therefore, before glass sees adoption as an interposer in advanced packaging, we believe it could gain traction as a substrate core, replacing the conventional resin and glass-cloth composite core used in select high-end organic substrate applications. This should not be interpreted as glass cloth becoming obsolete. We expect glass-core adoption to be gradual, while mainstream ABF and other organic substrates should continue to rely on glass-cloth-reinforced resin cores in the near term.

Glass has several advantages over organic cores, including:

• Fine line width/space and via pitch: Down to 2um in line width/space, 75um on via pitch can accommodate more I/Os for more chips with more complex functions (50% more dies on a chip) or reduce the metal layers
• Higher bump density: Die-to-die bump pitch is less than 35um on substrate to reduce die area and power consumption
• High speed I/O: Smooth copper interconnects, ultra low-loss dielectric and fine TGV pitch together can enable high speed transmission at lower cost vs. optical solutions
• Better mechanical strength : Less warpage and distortion amid elevated temperatures during the packaging process
• Similar CTE as chips: Less mismatch of coefficient of thermal expansion (CTE) can mitigate the warpage issue

300mm wafer

7 interposers

Area efficiency -45%

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Organic Substrate

Glass Core Substrate

TGV

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Organic substrates leverage traditional PCB-like cores with woven glass laminates

> Provides a low cost, easily manufacturable material set with off

500

the shelf laminates available from leading suppliers

Exhibit 8: Glass Core Substrate vs. Traditional Organic Substrate

electrical and mechanical properties

Dimensional stability → Improved feature scaling

Source: Intel

Exhibit 9: Glass Core Substrates in Panel Form

Source: Intel

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Exhibit 10: Packages with Glass Core Substrates

Source: Intel

Exhibit 11: TGV on Glass Core Substrate

Source: DNP

Glassbridge/FAU

On June 24, Corning (covered by Meta Marshall) officially launched its GlassBridge glass optical interconnect assembly at the AI Data Center Optical Communications and Interconnect Technology Conference held in Seoul. Based on Corning's document:

1) Corning GlassBridge is a fiber -to -PIC connector platform that brings optical fiber directly to a photonic integrated circuit (PIC).

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2) Fiber -to -PIC technology refers to the optical interface that couples optical fiber directly into a PIC rather than through a long fiber assembly.

3) Traditional Fiber Array Units (FAU) become complex to assemble and scale at very high fiber counts. GlassBridge complements FAU -based approaches by offering a wafer -based, passively aligned alternative that supports higher density, improved scalability, and detachable system integration.

In CPO development, FAU makers are likely to face disruption risk with GlassBridge emerging as a new technology approach. For AI transceiver companies, the impact should be limited as GlassBridge can be used in both CPO and NPO. Wider application in NPO could potentially offset CPO risk.

Exhibit 13: GlassBridge supports NPO and CPO architectures

Source: Corning sepinoanen ool peseo-1e

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Exhibit 12: GlassBridge core product features

Source: Corning

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Exhibit 14:

"Optics on Interposer"

Source: Song, S., Mehta, N., Nedovic, N., Rekhi, A., Kalogerakis, G., Xu, L., … Gray, C. T. (2026). A 32Gb/s/λ 256Gb/s/Fiber Half-Rate BandpassFiltered Clock-Forwarding DWDM Optical Link in a 3D-Stacked 7nm EIC/65nm PIC Technology.

Exhibit 15: ReLFACon enables direct transmission of external photonic signals with MCM modules to achieve reliable signal transmission

Source: FOCI

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