報告_Citi_台積電_20260703

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原始內容

(RIC: 2330.1W, BB: 2330 11)

TWD

2,500

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1,750

1,500

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Prepared for Kevin Lu

03 Jul 2026 11:05:54 ET │ 20 pages

Sep

Dec

Mar

Jun

TSMC (2330.TW)

Scaling growth through technology, packaging and capacity

CITI'S TAKE

TSMC will host 2Q26 analyst meeting on July 16. We think there is a higher likelihood for TSMC to further lift its revenue growth target for 2026 and long-term revenue CAGR given sustained leading-edge demand and improving visibility in the longer term . GM should continue to be resilient thanks to high UTR and efficiency despite rising depreciation and N2 dilution. We see demand extending well beyond GPUs, custom ASICs, TPUs, networking silicon and optical interconnects, and upside from CPU. These all supports broad-based utilization across advanced nodes. We also see wafer pricing trending up into next year on the back of strong N2 and N3 demand. We believe TSMC remains a primary beneficiary of AI semiconductor content growth regardless of customer mix.

Capacity expansion to continue in both advanced node and packaging -Compared to other leading foundry peers, TSMC's largest advantage is not solely process technology but manufacturing scale. Our estimates suggest combined A14, N2/A16 and N3 capacity could approach c350-400k wpm by the end of 2028. The company also maintains priority access to EUV tools, even without high-NA EUV adoption, allowing faster capacity expansion while preserving industry-leading yields. This scale advantage should continue supporting wafer pricing, customer stickiness and GM sustainability despite increasing foundry competition. We lift our capex estimate for 2027/2028 to US$75-80bn (from US$68bn and US$75bn respectively) while maintaining our 2026 capex unchanged at US$55bn.

CoPoS to follow CoWoS and SoIC in 2029 onward -We also update advanced packaging capacity in this note; however, using CoWoS capacity growth alone to estimate its customer share gains or AI accelerator shipment is becoming increasingly misleading. As package architecture shifts from conventional 2.5D integration toward heterogeneous 3D stacking, the packaging content, manufacturing cycle time and material intensity per product are diverging rapidly. Looking further ahead, glass core and CoPoS represent the next potential packaging evolution by enabling larger package sizes, improved dimensional stability and finer routing density, potentially supporting future AI accelerators beyond today's organic substrates. We view glass as complementary for CoWoS, with hybrid bonding, SoIC and advanced interconnect likely remaining the key differentiators in next few years.

Reiterate Buy with TP NT$3,800 -We lift our TP of TSMC to NT$3,800 (25x of our 2027 EPS). AI infrastructure investment remains as its key multi-year growth driver.

Earnings Summary

Source: Powered by dataCentral

See Appendix A-1 for Analyst Certification, Important Disclosures and Research Analyst Affiliations.

n Buy

Catalyst Watch: Upside

Price (03 Jul 26 13:30)

NT$2,445.00

Target price

NT$3,800.00↑

from NT$2,875.00

Expected share price

return

55.4%

Expected dividend yield

2.0%

Expected total return

57.4%

Market Cap

NT$63,404,645M US$2,001,472M

Price Performance (RIC: 2330.TW, BB: 2330 TT)

Laura (Chia Yi) Chen AC

+886-2-8726-9090 laura.cy.chen@citi.com

Jack Chen +886-2-8726-9091 jack1.chen@citi.com

Nicholas Lai +886-2-8726-9093 nicholas.lai@citi.com

Prepared for Kevin Lu

Prepared for Kevin Lu

Technology Leadership Extends Beyond Process Nodes into Advanced Packaging

Compared to other leading foundry peers, TSMC's largest advantage is not solely process technology but manufacturing scale. Our estimates suggest combined A14, N2/A16 and N3 capacity could approach approximately c350-400k wafers per month by the end of 2028. The company also maintains priority access to EUV tools, even without high-NA EUV adoption, allowing faster capacity expansion while preserving industry-leading yields. This scale advantage should continue supporting wafer pricing, customer stickiness and gross margin expansion despite increasing foundry competition.

While competitors continue narrowing the transistor density gap, putting more capex and aggressive on advanced packaging. TSMC's competitive advantage increasingly comes from its integrated platform combining leading-edge logic with advanced packaging. TSMC's advanced packaging including CoWoS platform, SoIC and COUPE has become the industry's de facto standard for AI accelerators due to its superior HBM integration, manufacturing maturity and ecosystem support. Intel's EMIB remains an attractive architecture for certain chiplet applications by reducing silicon interposer size and lowering packaging cost, but it has yet to demonstrate comparable scalability for large AI systems requiring extremely high memory bandwidth (see our previous report of TSMC (2330.TW) Competitive Landscape Holding Steady). Looking further ahead, glass core and CoPoS represent the next potential packaging evolution by enabling larger package sizes, improved dimensional stability and finer routing density, potentially supporting future AI accelerators beyond today's organic substrates. We view glass as complementary for CoWoS, with hybrid bonding, SoIC and advanced interconnect technologies likely remaining the key differentiators over the next several years.

We expect TSMC to continue aggressive investment across CoWoS and SoIC under its 3DFabric roadmap; in 1Q26, we expected CoWoS capacity reaching roughly 200k wafers/month by 2027 while SoIC expanding toward 70-80k wafers/month in 2028. We now also expect TSMC may start CoPoS production in 2029/2030 with initial capacity plan at 40-50kwpm. Importantly, packaging demand is broadening beyond AI GPUs into AI ASICs, CPUs and high-speed networking processors, suggesting advanced packaging will remain one of TSMC's fastestgrowing businesses. We also expect future packaging innovation-including glass core, chip-to-wafer hybrid bonding and larger multi-reticle integration-to further strengthen TSMC's technology leadership.

Figure s. lome - advanced node capacity expansion torecast

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© 2026 Citigroun Inc. No redistribution without Citigroup's written permission..

C 2026 Citigroun Inc. No redistribution without Citigroun's written permission.

customer

(k wafer)

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1,000

750

Figure 1. TSMC -advanced packaging capacity forecast

250

© 2026 Citigroup Inc. No redistribution without Citigroup's written permission. Source: Citi Research

Figure 2. TSMC -advanced packaging allocation by customer

Nvidia

© 2026 Citigroun Inc. No redistribution without Citigroup's written permission..

2028

© 2026 Citigroup Inc. No redistribution without Citigroup's written permission. Source: Citi Research

Figure 3. TSMC - advanced node capacity expansion forecast

© 2026 Citigroup Inc. No redistribution without Citigroup's written permission.

Source: Citi Research

Advanced packaging getting more complex; the CoWoS capacity myth.

The rapid adoption of advanced 3D integration and applications are making CoWoS capacity a much less relevant proxy for investor to project GPU/ASIC shipment growth than it was in previous AI GPU cycles. Products such as AMD's MI455, which stacks six logic dies using SoIC, and next-generation platforms such as Feynman introduce significantly higher packaging complexity, making the conversion between wafer starts, SoIC output and effective CoWoS capacity increasingly difficult. In other words, one 'unit' of CoWoS capacity no longer represents the same amount of compute, silicon area, or packaging content across different products.

Prepared for Kevin Lu

2024

Figure 4. 15Me - capex trend and capex intensity

(US$mn)

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• Capex (US$mn)

C 2026 Citioroun Inc. No redistribution without Citioroun' s written nermission I

Prepared for Kevin Lu

60%

50%

40%

At the same time, investors are overlooking another important bottleneck: CoWoS expansion is no longer determined solely by TSMC's packaging capacity. The ecosystem is becoming increasingly constrained by upstream ABF substrate availability, particularly as larger package sizes, higher layer counts and more complex substrate designs accompany advanced 3D architectures . As a result, incremental CoWoS capacity additions do not necessarily translate into proportional shipment growth for every customer.

2026

2027

2028

Therefore, using CoWoS capacity growth alone to estimate customer share gains or AI accelerator shipment growth is becoming increasingly misleading. As package architecture shifts from conventional 2.5D integration toward heterogeneous 3D stacking, the packaging content, manufacturing cycle time and material intensity per product are diverging rapidly. Future customer growth should be evaluated based on package architecture, SoIC content, substrate consumption and overall packaging complexity, rather than relying on a simple CoWoS capacity multiplier.

Capacity Expansion Supports a Multi-Year Growth Cycle

TSMC continues accelerating global capacity expansion across Taiwan, Arizona and Japan while reallocating existing fabs from N5 to N3 and from N3 toward N2 to reflect changing customer demand. We expect N3 capacity is expected to reach 170k wafers/month during 2026 and surpass 200k by 2028, while N2/A16 capacity could grow from approximately 80kwpm to 150kwpm in 2028. And A14 will start contribution firstly in 2028 with initial capacity at 50kwpm by our estimate. This aggressive expansion is supported by rising capex, which we expect projects could approach US$75-80bn annually in 2027-2028, following around US$55-56bn in 2026. We believe this capacity roadmap not only accommodates accelerating AI demand but also reinforces TSMC's pricing power and long-term technology leadership across both foundry and advanced packaging.

Figure 4. TSMC - capex trend and capex intensity

© 2026 Citigroup Inc. No redistribution without Citigroup's written permission. Source: Citi Research

packaging tracilities

Taiwan 12 inch fabs

Fab

Fab 12

Fab 14A

Fab 14B

Fab 15A

Fab 15B

Fab 18A

Fab 18B

Fab 20

Fab 22

Fab 25

Fab 26

Taiwan advanced packaging

Fab

AP 1

AP 2

AP 3

AP 5

AP 6

AP 7

AP 8

@ 2026 Citioroun Ine No redistribution without Citioroun's written nermission

Tainan

Tainan

Taichung

Taichung

Tainan

Tainan

7/10nm, 16/20nm

45nm

12/16nm

28nm

6/7nm

4/5nm

N3

Note

Expanding N3 capacity

Expanding N3 capacity packaging facilities

Overseas fabs

Fab

Fab 21

Figure 5. TSMC - Taiwan 12 inch fabs and advanced packaging facilities Expanding N2/A16 capacity

Location

US Arizona

Current Process Focus

4nm

Phase 2 for N3 in 2027, Phase 3

for N2/A16 afterwards

Figure 6. TSMC - overseas 12 inch fabs and advanced packaging facilities

China Nanjing

Japan Kumamoto

Germany Dresden

22/28nm, 12/16nm

22/28nm, 12/16nm

In construction

Phase 2 for N3 with mass production in 2028

Mass production for 22/28nm,

12/16nm after 2027

M 2026 Citioroun Ine No redistribution without Citioroun's written nermission

© 2026 Citigroup Inc. No redistribution without Citigroup's written permission.

Source: Citi Research

© 2026 Citigroup Inc. No redistribution without Citigroup's written permission.

Source: Citi Research

Reiterate Buy with NT NT$3,800

On the back of solid visibility in the longer term, we raise our 2027/2028 earnings estimates by 13%/21% and lift our TP of TSMC to NT$3,800 (25x of our 2027 EPS estimate, with unchanged PER but move to 2027). AI infrastructure investment remains the key driver behind TSMC's multi-year growth outlook. We think there is a higher likelihood for TSMC to further lift its revenue growth target for 2026 and long-term revenue CAGR given sustained leading-edge demand and improving visibility in the longer term. GM should continue to be resilient thanks to high UTR and efficiency despite rising depreciation and N2 dilution. We see demand extending well beyond GPUs, custom ASICs, TPUs, networking silicon and optical interconnects, and upside from CPU. These all supports broad-based utilization across advanced nodes. We also see wafer pricing trending up into next year on the back of strong N2 and N3 demand.

TSMC

Prepared for Kevin Lu

Figure o. loMe - Forward P/E band

NT$

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500 -

0

+

2010

2012

• TSMC -

2014

— 11.4x

2016 2018

2020

2022

13.2x — 15.0x

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16.8x

@ 2026 Citioroun Ine No redistribution without Citioroun' s written nermission

Prepared for Kevin Lu

Figure y. IsMe - Forward P/D band & RUt

NT$

3000

2500

2000

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1000

Figure 7. TSMC - Estimates Revisions

© 2026 Citigroup Inc. No redistribution without Citigroup's written permission.

Source: Citi Research

ROE

45%

35%

30%

25%

20%

Figure 10. 15MC - Forecast Summary

2025

20

933.8

-386.4

547.4

-84.5

-23.2

-61.3

463.4

Unit: NT$bn

Revenue

COGS

Gross Profit

Operating Expense

SG&A expenses

R&D expenses

EBIT

Net Interest Income

-85.2

493.4

-28.6

407.1

19.8

20.3

30

989.9

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-87.8

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21.3

500.7

Figure 10. TSMC - Forecast Summary

Pre Tax Profit

Tax Expense/(Credit)

Net Profit

EPS (NT$)

Margins (%)

Gross Margin

Operating Margin

Net Margin

Sequential Growth (%)

Revenue

Gross Profit

EBIT

Net Profit

EPS

Prepared for Kevin Lu

2027

2QE

1,878.8

-628.1

1,250.7

-165.3

-52.6

-112.7

1,085.4

30E

1,943.0

-608.7

1,334.3

-172.9

-52.5

-120.5

1,161.4

45.2

10.2

4QE

1,958.4

-629.7

1,328.7

-176.3

-49.0

-127.3

1,152.4

49.9

10.3

1Q

1,134.1

-382.8

751.3

-94.0

-26.2

-67.8

659.0

23.8

5.1

2026

20E

1,239.6

-407.5

832.2

-111.6

-34.7

-76.9

720.6

22.9

6.7

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1,454.4

-473.8

980.6

-132.9

-39.3

-93.7

847.7

25.3

7.8

4QE

1,666.0

-540.4

1,125.7

-141.6

-41.7

-100.0

984.0

28.5

8.8

10E

1,818.8

-595.9

1,222.9

• 151.2

-42.1

-109.1

1,071.7

36.4

9.6

2025

3,809.1

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2,281.3

-345.2

-99.2

-246.4

1,936.1

86.2

19.4

2026E

5,494.2

-1,804.5

3,689.7

-478.4

-141.9

-338.2

3,211.3

100.5

28.4

2027E

7,599.1

-2,462.5

5,136.6

-665.7

-196.1

-469.6

4,470.9

172.9

40.0

2028E

6,833.5

-883.0

-260.3

-622.8

5,950.5

248.7

52.3

© 2026 Citigroup Inc. No redistribution without Citigroup's written permission.

Source: Citi Research, company data

-56.5

4Q

Prepared for Kevin Lu

Adding Upside 30-Day Catalyst Watch on TSMC (2330.TW)

Direction:

Upside

Duration:

Within 30 Days Earnings

Catalyst:

TSMC will host 2Q26 analyst meeting on July 16. We open a 30-day upside catalyst watch as we expect the company to further lift its revenue growth target for 2026 and long term revenue CAGR given sustained leading-edge demand and improving visibility in the longer term.

NT$

4,002

3,335

2,668

2,001

1,334

667

Jul 25

° Higher-than-expected utilization

• Bull case TP to be based on its upcycle valuation of 27x PER

NT$ 2,200.00

• 10% Downside

4 64% Upside

NT$ 3,800.00

• 55% Upside

Bull/Bear: TSMC (2330.TW)

BASE Assumptions

• Solid sales CAGR of >35% in 2025-2028E
• GPM to be maintained above 60% level
• BEAR Assumptions

• Weaker-than-expected HPC demand globally

• Worse-than-expected margin contraction

• Bear case TP to be based on its valuation of 15x PER

Prepared for Kevin Lu

Prepared for Kevin Lu

TSMC

Company description

TSMC is the founder and leader of the dedicated IC foundry segment. The company has built its reputation by offering advanced and "more-thanMoore" wafer production processes and unparalleled manufacturing efficiency. From its inception in 1987, TSMC has consistently offered the foundry segment's leading technologies and TSMC-compatible design services.

Investment strategy

We rate TSMC shares as Buy. We expect TSMC to deliver sales growth of >35% in recent years thanks to strong growth from HPC/AI as well as stable demand growth from smartphone, IoT, and automotive on tech migration and a shortened replacment cycle. CPU outsourcing to TSMC offers further growth upside potential. A rising cash dividend should also support the share price. While TSMC has been increasing capex meaningfully since 2009, its cost structure is maintained through continuous product mix improvements, efficiency enhancements, and cost reductions.

Valuation

Our target price for TSMC shares of NT$3,800 is based on 25x the average of our 2027E EPS, higher than its three-year average forward PER, versus global peers' average of 15-23x. We believe our PER target is justified by TSMC's leading position in advanced process node and robust AI demand growth outlook. Given its continuing leadership in the semiconductor foundry industry, we believe TSMC's stable order visibility and earnings outlook make it less vulnerable than peers to a potential global economic downturn. Our target price equates to 2026E/27E P/E of 36x/25x and 2026E/27E P/B of 13x/10x.

Risks

Key downside risks that could impede the shares from achieving our target price include: 1) weakness in the global semiconductor market; 2) largerthan-expected margin contractions due to depreciation cost hikes and strong NTD; 3) competitors entering the foundry business; 4) longer-than-expected digestion of inventory in the supply chain; and 5) a slowdown in demand either from a global economic downturn or a global trade disruption triggered by tariffs.

Analyst: Laura (Chia Yi) Chen

Prepared for Kevin Lu

TWD

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If you are visually impaired and would like to speak to a Citi representative regarding the details of the graphics in this document, please call USA 1-888-500-5008 (TTY: 711), from outside the US +1-210-677-3788 JF M AM JJ A SON DIFMAM/JAS

Date

Appendix A-1

3718-Jan-2410:40:18

*740.00

588.00

1/

1009-Apr-25 07:55:10

*950.00

819.00