產業_SEMICON2026矽光子論壇_Soitec逐字稿_20260831

場次：2026 SEMICON Taiwan 矽光子國際論壇（2026-08-31） 講者：Yannick Larvor（Head of Photonics & Sensing Segment, Soitec） 題目：Advancing TFLN and InP Silicon Photonics Hybridization to Enable Next-Generation High-Speed Modulators 對應簡報：產業_SEMICON2026矽光子論壇_Soitec簡報_20260831

[00:00:00.00] So, hopefully you didn't cover most of your talk. [00:00:12.00] So, first I'm delighted to talk in front of this vibrant and inspiring ecosystem from Cypher. [00:00:20.00] Soitec has invested in photonics for the past 15 years and seeing 2026 as this inflection point in the silicon photonics business is really a reward for the whole ecosystem thanks to this collective innovation. [00:00:41.36] So my talk today is about advancing hybrid integration of TFLN and InP to really boost the Silicon Photonics platform. [00:00:54.36] Today we will start with a quick introduction on Soitec, a portfolio right level and also [00:01:06.36] about our work process. [00:01:09.36] We all guide as well from our traditional facility to how we expand our SOI substrate [00:01:17.36] Then we have a couple of words, some have been discussed at length already today, about the trend of optical interconnect market trends, to give a bit more context on the core of the talk that will be enhancing the silicon photonics platform with hybrid integration of InP and LNOI. [00:01:44.86] and then we will dive into the specifics of the platform substrate that Soitec is offering to the industry. [00:01:57.78] Okay, so quick introduction of Soitec and our role in the ecosystem. [00:02:03.78] So we've been incorporated in the 90s and we have a very unique position in the ecosystem. [00:02:14.78] We are not a provider, we are not a foundry, we sit really in between because we design [00:02:24.78] and engineer substrate that are the foundation of multiple chips [00:02:32.50] by communication [00:02:41.50] infrastructure yeah more than 2,000 pro-empleased and revenue of 600 million [00:02:51.02] euro last year and growing thanks to the silicon photonics uptake. So what's our secret sauce? [00:03:00.22] If you're not familiar with Soitec, what we do is that we have a core process called Smart Cut [00:03:08.62] that allows us to transfer a neutral thin monocrystoline layer onto a support wafer with [00:03:15.98] atomic precision. And what does it mean for the photonics and silicon photonics application? [00:03:23.98] It means that we give unmatched fitness uniformity for building a photonics REC, and we do it with [00:03:35.98] we do it with gross efficiency because of the recycling process we have from the donor [00:03:42.58] with her and we address [00:03:51.74] capable to integrate heterogeneous material and this at an industrial scale [00:04:01.54] Okay, I heard a few minutes back this presentation from the AC. [00:04:09.54] There was this uptake of the optical engine revenue. [00:04:16.54] It was a graph from Yole. [00:04:19.54] Well, it's definitely an opportunity, but at the same time it's a challenge. [00:04:26.54] and we want to update you today on where we stand in supplying SOI, because SOI is really under a strong domain at the moment. [00:04:39.34] So we do operate this market process at scale, because innovation and such a process without high volume is irrelevant. [00:04:49.04] So we do have now our BFAB based in France, fully now onboarding the Photonics SOI challenge. [00:05:01.04] So B1 is our 200mm facility, the historical one, I would say now running at full capacity to supply Photonics. [00:05:13.04] We do have B2, SOI 300mm platform expanding and serving customers worldwide. [00:05:24.04] B4 is the new kids on the globe, I would say, for Photolix. [00:05:29.04] We are now expanding the acetine B4 to serve mainly 300mm SOI. [00:05:37.04] And next to this we have our B3 FAT for piezo type of material running LTOI and LNOI for RF application. [00:05:49.04] We are planning and also ramping I would say 150mm LNOI for optical grade application. [00:05:59.04] I will come back on more details on this later in the talk. [00:06:03.04] And the extension towards 200 millimeter diameter is ongoing. [00:06:09.04] But, yeah, France operations are running well, [00:06:14.04] but the key update is really from an industrial perspective. [00:06:21.04] The PR1 facility in Singapore, [00:06:26.04] We started to ship in volume Photonics product last quarter and doing well and we are now catching up with the demand which is also a very good hub based in Siakor to serve Asian customers. [00:06:44.04] Next to this we have partners in China, so far not onboarded in the photoly journey, but this is an update. [00:06:57.04] We know that SOA is on strong demand and continue to give you this update. [00:07:02.04] Let's move now to the context, a bit more context on the market trends and innovation that are needed to cope with those trends. [00:07:17.84] So we've discussed this morning and we've certainly quite at length the architecture or topology of the racks. [00:07:30.48] today no doubt RAC are based on 100% copper electrical domain doing a good job to serve tens of XPU sharing a unified memory into the scale up domain [00:07:46.48] but what we see and what is really driving the attack on the graph is this move to a larger number of XPU per scale up domain [00:07:58.48] And as we see from a substrate perspective and we are kind of quite at the bottom of the value chain, so we have quite a broad view on the market is that there will be two steps. [00:08:12.48] One step where the raw scale scale up will be kind of hybrid, copper inside the rack, optics connecting the switch across the racks. [00:08:25.48] And then moving forward, like we from 2029 onwards, we will see, like I've seen in the show this morning, this kind of 100% optic track where compute networking are completely disaggregated, leveraging the optical interconnect. [00:08:47.48] and the benefits are quite well understood. [00:08:52.48] Next to disaggregation that you can achieve with optics, [00:08:56.48] you can have higher heat rate to cope with a service speed increase. [00:09:02.48] You will have better power efficiency because you per bit. [00:09:06.48] You will have latency that you could, let's say, [00:09:12.48] giving you flexibility for design and the density of intercollecting trees. [00:09:19.48] So scale-out, scale-cross, we saw that in our presentation, I've already moved 100% to optics. [00:09:27.48] From 2027 and this inflection point that we are seeing now, it's really all about this new scale-up domain [00:09:35.48] steadily moving to optics. [00:09:40.48] So, optical engine, we've seen so far multiple, let's say, explanation on this. [00:09:49.66] We'll focus on really where Soitec has a play, and our play is on the optical engine in the peak. [00:09:59.32] We are leveraging our smart cut technology to really have web guides and modulators in the peak. [00:10:08.02] But what we see is really, let's say, complete, evenly spread type of optical imaging. [00:10:19.46] Could be in the plug-able, that is the historical and traditional way to connect racks. [00:10:28.32] There are multiple implementations, plug-able optics, linear or real-time optics. [00:10:35.22] What we see coming, which is new, is not new in the past, but new in the fact that it will [00:10:47.22] be actually deployed, is really NPOs, halfway between pluggable and CPO, where the optical [00:10:55.22] engine sits on the PCB inside the cylinder or switch board. [00:11:01.22] And we see this kind of application ramping up for a scale of domain. [00:11:06.22] And of course the most elegant application or embodiment of an optical engine is CPO or optical IO, [00:11:15.22] depends if the OE is on the substrate of the package or if it's directly integrated on the silicon interposer. [00:11:22.22] but we see this in terms of just moving from r d to real deployment [00:11:33.66] and i think this morning we had a tsnc talk asking us to trigger our imagination [00:11:42.14] of what could be next and i think from a substrate perspective what we see coming and a couple of [00:11:49.98] talks have addressed that is really a photonic interposer. Why? And why it is, it's a package [00:11:57.34] scale active silicon photonics interposer aiming at connecting chiplets. And that's [00:12:04.86] really what we think is the ultimate destination of silicon photonics. We are not there yet, [00:12:11.50] there's a lot on this journey to achieve such deployment, but the benefits are clear. [00:12:20.50] You expand the shoreline to cope with a huge, or ever-growing IOM bandwidth. [00:12:28.50] You reduce at this minimum level the latency and the power consumption because with 3D integration, [00:12:35.50] integration as we saw in the imec talk, the copper [00:12:40.12] connection are limited to the bare minimum. [00:12:43.62] And you create opportunity, like the question we had, [00:12:47.04] on disaggregating different elements, different chiplets. [00:12:53.04] And of course, we had in mind the disaggregation of memory [00:12:57.10] from the logic chiplets on the interposer. [00:13:01.10] We can debate if this interposer can be active, [00:13:03.98] can be passive if you move to an active option then you can imagine as well to [00:13:11.58] have built-in optical switching on this interposer with reconfigurability [00:13:21.42] possible between the cheat set and this is not science fiction we see and I [00:13:29.26] spotted some say realization with different level of maturity of such interposer couple of names are [00:13:39.02] being mentioned from startup to uh fabless or rto so really it's a this silicon photonics interposer [00:13:49.18] will really benefit from a heterogeneous integration because it will add a new function [00:13:56.94] and it will also boost performances [00:14:04.06] so a few words first you know before doing i agree or e-toginous integration you need a [00:14:11.82] solid foundation this this is the so i portfolio overview 200 millimeter full prediction [00:14:21.02] ideal candidate for plugable and legacy type of process notes. [00:14:28.02] We do see extreme acceleration of 300mm platform. Why? Because first you can scale in terms of production, [00:14:39.02] but you can also have better lithography and for CPO, optical I.O. you have access to advanced packaging, [00:14:48.02] packaging which is one of the critical elements to make CPU and optical I.O. an industry of reality. [00:14:55.02] We do have as well SOI plus EPI for some niche applications related to sensing. [00:15:02.02] And the value proposition of SOI, very quickly, the smart cut is controlled at atomic level precision [00:15:13.02] which means that a couple of hundred of nanometers of top silicon minimize loss dark current [00:15:22.38] the box also comes with different requirements depending on edge coupling or also the the [00:15:31.10] bonding interface is being designed such the the loss and the scattering of the light is minimal [00:15:37.34] And we do have, as well on the silver handle, some specificity in order to control the density of the blood micro defect, which is important for 3D stacking when we pick up the IC or 3D stack. [00:15:56.84] An example of the standard product we deliver to the market is 1.4 nanometer of uniformity [00:16:04.84] on top-circuit, wafering wafer, we can achieve on some custom program 0.1 nanometer. [00:16:14.84] Ok, moving to the core of the talk is really about hybrid integration. [00:16:21.84] why do we need hybridization of signal performance? I think there are three main reasons. One is to [00:16:30.72] for the dictor lane higher modulation speed. We also need to continuously improve the [00:16:36.56] picojoule per bit energy efficiency and we need partly on the photonic interposer side to bring more value [00:16:43.92] to integrate more devices, be it laser, be it switches. [00:16:48.92] And at Soitec, we see really two main candidates [00:16:54.92] material platform. [00:16:55.92] One is lithium niobate for high speed modulation, [00:16:59.92] but could be also, and we saw this in the UMC talk, [00:17:03.92] could be also for other devices, sensing, quantum. [00:17:08.92] And on the InP side, no doubt, [00:17:11.92] the laser source, integrating active elements, amplifiers, photodiodes will really bring [00:17:18.92] even more value to the peak. [00:17:23.92] Ok, we can take on our three pillars at Soitec. [00:17:30.92] Photo des Soirais, I mentioned the effort we are doing to expand the capacity and catch [00:17:37.92] and catch up with the high demand. [00:17:40.82] We are in full production, not only 300 millimeter. [00:17:44.02] LNOI, critical material, [00:17:47.36] partly from a geopolitics standpoint, [00:17:51.60] to ensure a supply chain that is a future problem. [00:17:56.66] We are ramping up 150 millimeter. [00:17:59.50] I will come back on the specifics on this platform. [00:18:03.20] And we do have as well some effort to explore [00:18:07.28] smart cut value for InP platform this is an R&D pass finding type of program so far but those are the three pillars with different level of maturity. [00:18:19.28] Ok moving to the specifics of LNOI why did we select LNOI and why do we invest on this one [00:18:29.28] basically the modulation speed and also the lower consumption that it brings versus silicon. [00:18:36.28] It's easy to compare and to do some bias, let's say analysis, but if you look at the [00:18:46.28] pin curve, you will see exactly a good match to complement the silicon photonics. [00:18:53.28] you can modulate at high speed with better energy efficiency [00:18:57.64] and in terms of scalability, integration, reliability, [00:19:02.32] silicon photonics is the perfect host for LNOI. [00:19:07.54] So yeah, LNOI provide those benefits while other materials [00:19:13.22] like B2O polymer that we discussed through IMEC [00:19:17.56] are still at the level of development and maturation [00:19:23.28] They come with great benefit, but we see them as a longer-term candidate. [00:19:31.28] So, LNOI platform, a few words on where we stand in the deployment. [00:19:37.28] I see a lot of pictures, the slides will be shared, but we have a new platform, [00:19:44.28] 150mm is currently sampling, 200mm will sample early next year. [00:19:52.28] I can give you a color of our current funnel within our 10 to 15, let's say, customers [00:20:00.96] or partners developing. [00:20:01.96] We see three categories, thin box towards more thick box. [00:20:08.78] The main differences is really that thin box, so bare oxide in between the LN and the [00:20:14.46] are more for wafer to wafer, die to wafer, [00:20:18.46] or microtransfer printing type of integration. [00:20:21.46] While we see also a category of partners [00:20:26.46] looking at thick box, eight, even ten micrometer box [00:20:31.46] for standalone TFLN peak, it depends on the application [00:20:38.46] for both cons and cons. [00:20:41.46] We are happy to be agnostic from a substrate perspective and then the main advantage is [00:20:51.46] to boost the speed and increase the power efficiency. [00:20:59.46] A few words now on the InP, even if it's a more, let's say, future R&D program. [00:21:09.82] We do see needs because of the material scarcity. [00:21:13.72] We do see need to have a better manufacturing, manufacturing and integration. [00:21:20.30] We do see Smart Cut having a role in the thermal side of the InP. [00:21:25.74] And also looking at InPOSi, InPOSi from a device perspective, we can explore performance, improvement and also optimize process flows. We have already some partners who have developed some devices. I can point you to the article. [00:21:47.74] The technology substrate platform that we are looking at and developing with partners [00:21:54.74] comes with the IP seed layers, bare dock side. [00:21:57.74] We do have an option with no box, which we see has resonated with some partners. [00:22:05.74] And the handle sequence is adding high resistivity, [00:22:09.74] which could be also an end with a track reach. [00:22:12.74] The benefits are clear, supplying security, trying to improve the current situation of [00:22:19.74] InP scarcity and we are welcoming any company who will help us to explore the benefit of [00:22:28.74] Smart Cut for InP. [00:22:30.74] We think there is a strong play here and as an ecosystem we can probably improve that. [00:22:39.74] Takeaways, looking at the time, I'm a bit late, but you've seen photonics for AI starts at Materio. [00:22:49.74] We do have this 3 PR strategy, we have the proven industrial production scale, and we see a bright future for silicon photonics. [00:22:59.74] Someone was saying it's just the early start of the wave and yes, biosensing will come [00:23:08.74] into the next area where silicon photonics can have a play. [00:23:12.74] And before taking questions, if I still have time, I want to have two statements here. [00:23:17.74] First, recognition of the European Commission for the support provided to a part of this [00:23:25.74] work through the European chip GU project the consortium is starlight and also to invite you [00:23:33.82] to you can photonics adoption and and ecosystem is very important for us so we are organizing [00:23:42.06] at ECOC at the end of September photonics workshop the speaker lineup is quite self-explanatory some [00:23:50.54] great names, it's a great opportunity to connect. [00:23:55.68] So please refer to our social network channels [00:24:00.78] and subscribe and you are welcome. [00:24:04.14] Thanks for your attention. [00:24:09.94] Thank you, Danny. [00:24:10.78] We have time for one question. [00:24:12.50] I have a question around the stresses that you need to handle at the waiver level. [00:24:24.50] Is there a concern? [00:24:26.50] What have you done to alleviate the difference? [00:24:29.50] What do you mean the boom and the war? [00:24:31.50] Exactly, because you're doing TFR and you're doing it in Norway, you're doing... [00:24:36.50] So we do have a kind of strong benefit already on SOI that we will definitely replicate for our LNOI. [00:24:45.50] And moving InP on the silicon substrate will be much robust than InP. [00:24:55.50] So those are definitely some real continuous improvement on our side. [00:25:02.50] And what kind of thickness seeds do you have in your phosphatides? [00:25:06.50] Our ideal phosphat is an AP seed layer, so we're working with partners to prove that growing AP with a certain thickness [00:25:16.50] does not alleviate the performance of the substrate. [00:25:19.50] So on InP, I would say it's a moving target depending on the target application. [00:25:25.50] Excellent. Let's thank the speaker again.