video_OCP2026_Ciena_OpenCPX可插拔NPO插座_20261015

Thank you. >> Thanks, Eric. >> Yep. Good afternoon, everybody. Okay, so I'll talk about OpenCPE and why it's so important to have these NPO CPO connectors. So, first of all, pluggables are great. But, not only at the front panel. So, when you move the these pluggables in closer to the ASICs, they enable retimer-free mixed-media ecosystems for passive copper, active copper, and linear optics. And that's important for scale-up because it enables multi-rack high-bandwidth all-electrical, all-copper scale-up domains. And in the scale-out domain, it enables you to put to devote more rack space to revenue-generating XPUs than to the network parts, to the switches of your system. The table here on the bottom summarizes the difference between front-panel pluggable and CPO NPO. And you always hear about power reduction, latency, and jitter reduction, reliability, less link flaps, that this is a difference between the two. But, what you don't hear so often about, and I'll focus quite a bit on that, is about the density, the tray and rack density that CPO really enables relative to pluggables. And that's an much overlooked uh aspect. So, let me first talk a little bit about retimer-free copper, active copper. What you see here is Ciena's Nitro Redriver chip. And that allows you to do 3 and 1/2 m of copper cable at 1.5 pJ per bit. That's pretty significant. And if you compare that to active electrical cables, retimed cables, that yeah, they have like a meter more, but at 10 times almost the power consumption. So, in terms of bangs for your buck, the ACC is a really, really good solution. You see here how this re-driver does 70 dB of loss um with very good brief uh pre-FEC bit error performance. Now, what can you do with this stuff? You can now reach across three racks. You can build yourself a an all copper scale up domain that has 256 XPUs connected at 25 terabit of scale up bandwidth. All copper. Um a mix out of passive and active copper without a re-driver inside. So, no latency issues, no latency jitter issues at an average of 1 picojoule per bit that you spend for that advantage in the scale up domain. So, that's where mixed media is really important and comes in. In terms of optics, you see the co-packaged optics coming in. And why is that important? Not just because you shrink that red trace that you usually have to the front panel, and you really enable a robust TP2 compliant um linear optical ecosystem, but also because of density. If you put a 50 terabit switch inside the box, your front panel is peppered with OSFPs and is full. You can't escape more. You can put many more chips inside that tray because liquid cooling can do it, and now we have liquid cooling. So, you can easily put 200 terabit, maybe even 2 * 200 terabit ASICs switch ASICs in one tray. But how do you get 400 terabit worth of data out of a 1 RU box? That's impossible with any pluggables out there today, even with XPO. If you use only optical connectors on the front panel, you get 600 terabit single wavelength DR, not bidirectional, not WDM. All of these are multipliers. Of 400G, all of these are multipliers compared to 200G DR, 600 terabit out of a 10U front panel. And that's what you can fill into the front panel or into the box, as we'll see in a little bit. So, why why does rack density matter? It matters because switches don't produce tokens. It's the XPUs that produce tokens. And you don't want to assign real estate in the data center by having lots of switch racks. You want lots of XPU racks. What the table here shows is uh the the X um axis sort of for this this dimension here. What do we Where are we here? Oops, doesn't work. Okay. So, you have on the um on the vertical, you have the number of XPUs per tray, like four, six, or eight XPUs that you stuff in one tray. On the horizontal, you have how many switch ASICs you stuff per tray. And those are all 200 200 terabit uh switch ASICs. So, one, two, three, or four. And you see, for example, a typical tray would have four XPUs, and a typical switch tray today would have one 200 terabit switch. In that case, for a 500K XPU mega data center, you have 1/3 of the of the area in the data center be occupied by switch racks. If you put two switches in a tray, it's only 20%. If you put three, it's only 14%. Now we are talking. Because now the majority of your area is really XPUs and is not switches. So, that's important. So, hold that thought. You'll see, I'll come back to that. So, to enable all of this, to enable this co-packaged ecosystem, we created the OpenCPX um MSA. And uh that MSA was formed just before OFC this year, and within 6 months, we had the standard out. You can download the standard specification on the website. Version 1.0 is out. And that MSA specification standardizes a 6.4 and 7.2 T pluggable interface for co-packaged and near-packaged copper and optics. So, very flexible mixed media. You don't need compression hardware. Those are sockets that just snap in place. And it's a very robust ecosystem. You see here all the member companies. We are, I think, above 60 at this point and and growing. So, um this has really been a great ride so far. We're not at the end yet. Just to give you um an idea of what the Open CPX MSA has specified, it has specified two types of socket. The type one socket that you see to your left and the type two socket that you see to your right. The type one socket is smaller and allows you to mount the RF portion and the power and control portion on different mounting planes. For example, for true co-packaging where you want to mount the RF directly on your package substrate. That would be the right solution. The type two socket has a single pin field and is more for NPO or ICA NPO kind of applications where you don't care about the two um mounting planes and it has everything in one socket. And for either socket, you can now put in external laser modules, meaning CPX modules that require external laser sources. And laser integrated modules. Those are the bigger ones that have the laser already in integrated. It's now This is a system trade-off what you want to do. Just to show you, this is a Open CPX type two external laser module. So, that's the size, 6.4 terabit, right? Here is Here are two applications, both for an XPU that shows how you could enable 50 terabit per second of mixed scale up scale out. How you division it is up to you, but 50 terabits per second per XPU of bandwidth using today's uh open CPX modules. This is not future. This is sampling today. You can have this today. And on the right you see a 200 terabit switch with ICAs enabled by today's modules. So and that all works with the loss budget and everything that is all doable. And now you can put multiple of those in a tray of those switches. You see here a couple of examples. So on the very left you see a single 200 terabit switch inside and one of you tray with external laser open CPX modules. And here you see an an ELSFP that's not an ELSFP. I call it ELXPO. What the XPO form factor is really great at, it has super high density and can escape a lot of power because it's in module liquid cooled. So with one XPO form factor worth of lasers you can feed between 10 and 20 of these modules. So the argument that external lasers pepper the entire front panel with external laser sources, external modules, external laser modules, that is history. With an ELXPO you can really solve that problem very nicely. And then you can put two 200 terabit switches in a box. Maybe even three. Three might stretch it, but I still wanted to put it down to show you there's a little bit of vision in there as well. If we shrink things a little further, but two I think is no problem. And you can liquid cool that. There should also be no problem. If you do it with an external laser module, that's the one on the very right, you see that the modules are larger, so we you probably only fit one switch in an OU box, but you don't have to worry about external laser module. So again, it it remains a trade-off here. Here is a timeline. We are not as I said, we are not stopping with 6.4T. This coming March at OFC, we're going to do a extended version one that also specifies copper media and it might specify a type three connector. And in June of next year, we'll have spec version two that goes to a 12.8T 200 gig per lane and 14.4. So, uh six 64 and 72 lanes at 200 gig. And then at the end of next year, early '28, we'll have a ref three with N by 400 gig sockets. N is not yet defined. But here you can see this is moving with a super high momentum. So, what are the takeaways? The first one is re-timer free mixed media interfaces are crucial for the scaling of AI and that pertains to passive and active copper and linear optics. And they enable multi-rack scale up and ultra-dense switch racks in your data center. These sockets are sampling now. They are available and we have a road map throughout the next year to scale that to 12.8T and 400 gig per lane. And here you just see one example of our Vista engine that shows 6.4T with super good TP2 compliance at a 15 dB link budget from the serdes to the bottom of the socket. That's a user link budget. So, all the TP2 requirements are met, which is not that easy for for that kind of application linear drive. They are met with margin. Okay, thank you. >> [applause] >> I questions or do I have or how does it work, Eric? >> [laughter] >> We can do an interview. Sure. >> [laughter] >> The The OCP wants us to have a 5-minute uh break in between, but you can That's boring. You can use a couple minutes and ask a few questions. >> Yeah, how about guys how about any questions? >> Let's use the OCP 5 minutes more productively than in silence. >> Uh good. >> No questions? >> You mentioned there are some >> Wait, wait, wait. >> Hi. Great great presentation. Like um you mentioned some of these sockets are already available or some of these parts are already available in production. Who produces that and >> Yeah, so uh this The sockets are being made by uh companies. I hope I don't forget one any now, but uh Samtec, Molex, TE, Amphenol. Um they all make the sockets and connectors. Modules are available um and sampling right now. You see them even on the on the show show floor. Um Coherent, Terrahop, uh Ciena, of course, uh Intel. So, there are multiple companies. This is a robust ecosystem. And if you go to the OpenCPX website, you see all the member companies and they're all there for a purpose because they want to participate and generate uh products in that space. >> You have 400 gig on your own map. Is this still silicon photonics at that point? >> Yeah, good question. Uh >> [laughter] >> that depends on the on uh who is making it and how they are making it. I think silicon photonics is feasible. Um and if you look at this small size, you need something really small to do that. And uh obviously we're all working towards that. What it What it will be, how it will perform, there are multiple options there. >> Good. have time? Ah, no. Okay. Thanks, Eric. >> Thank you very much, Peter. Thank you for coming.